PCchips M847FLU Manual page 9

Built-in Ethernet LAN (optional)
 10Base-T/100Base-TX Physical Layer Solution
 Dual Speed – 100/10 Mbps
 MII Interface to Ethernet Controller/Configuration & Status
 Auto Negotiation: 10/100, Full/Half Duplex
 Meet All Applicable IEEE802.3, 10Base-T and 100Base-
TX Standards
USB 2.0
 Compliant with Universal Serial Bus Specification
Revision 2.0
 Compliant with Intel's Enhanced Host Controller
Interface Specification Revision 0.95
 Compliant with Universal Host Controller Interface
Specification Revision 1.1
 PCI multi-function device consists of two UHCI Host
Controller cores for full-/low-speed signaling and one
EHCI Host Controller core for high-speed signaling
 Root hub consists 4 downstream facing ports with
integrated physical layer transceivers shared by UHCI and
EHCI Host Controller
 Support PCI-Bus Power Management Interface
Specification release 1.1
 Legacy support for all downstream facing ports
IEEE 1394a (optional)
 Fully supports provisions of IEEE1394-1995 for high-
performance serial bus and the P1394a draft 2.0 standard
 Provides two fully compliant cables ports at 100/200/400
Mbits/s and available with one or two ports
 Supports optional 1394 Annex J electrical isolation barrier
at PHY-link interface
 Supports power-down feature to conserve energy in battery
powered application
 Node power-class information signaling for system power
management
1: Introduction
5