SOLTEK SL-65MIV-C User Manual page 70

65MIV-C / 65MIV2
DRAM Timing by SPD When this item is Enabled, DRAM Timing is set by
DRAM Clock This item allows you to control the DRAM speed.
SDRAM Cycle Length Select CAS latency time in HCLKs of 2 or 3. The sys-
Bank Interleave Please use default setting.
DRAM Drive Strength Leave this item at Auto mode.
DRAM Drive Value When "DRAM Drive Strength" is set to "Auto", this
Memory Hole In order to improve performance, certain space in
P2C/C2P Concurrency This item allows you to enable/disable the PCI to CPU,
Fast R-W Turn Around This item controls the DRAM timing. It allows you to
System BIOS
Cacheable
SPD. SPD (Serial Presence Detect) is located on
the memory modules, BIOS reads information coded
in SPD during system boot up.
The choices: Host Clock; HCLK+33M; HCLK-33M.
tem designer already set the values. Do not change
the default value unless you change specifications of
the installed DRAM or the installed CPU.
The choices: Disabled; 2 Bank; 4 Bank.
The choices: Auto; Manual.
item will be unable to be selected. We don't recom-
mend user to adjust this item.
memory is reserved for ISA cards. This memory must
be mapped into the memory space below 16MB.
The choices: 15M-16M; Disabled.
CPU to PCI concurrency.
The choices: Enabled; Disabled.
enable / disable the fast read / write turn around.
The choices: Enabled; Disabled.
selecting Enabled allows caching of the system BIOS
ROM at F0000h-FFFFFh, resulting in better system
performance.
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