Infineon TRAVEO T2G Series Configuration And Setup
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Infineon TRAVEO T2G Series Configuration And Setup

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AN224434
Clock configuration setup in TRAVEO
T2G Body
™
High family

About this document

Scope and purpose
This application note describes how to set up various clock sources in TRAVEO
T2G Body High family MCUs
™
and provides examples including configuring phase locked loop/frequency locked loop and calibrating the
internal low-speed oscillator.
Intended audience
This document is intended for users who use the clock configuration setup in TRAVEO
T2G Body High family.
™
Associated part family
TRAVEO
T2G Body High family
™
Application note
Please read the sections "Important notice" and "Warnings" at the end of this document
002-24434 Rev. *E
www.infineon.com
2024-04-23

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Summary of Contents for Infineon TRAVEO T2G Series

  • Page 1: About This Document

    This document is intended for users who use the clock configuration setup in TRAVEO T2G Body High family. ™ Associated part family TRAVEO T2G Body High family ™ Application note Please read the sections "Important notice" and "Warnings" at the end of this document 002-24434 Rev. *E www.infineon.com 2024-04-23...

  • Page 2: Table Of Contents

    Clock configuration setup in TRAVEO T2G Body High family ™ Table of contents Table of contents About this document ..............1 Table of contents .
  • Page 3 Clock configuration setup in TRAVEO T2G Body High family ™ Table of contents Configuring the PCLK ..............66 5.9.1 Example of PCLK setting .

  • Page 4: Introduction

    Cortex -M7 processor with floating-point unit (single and dual precision) and manufactured in advanced 40-nm process technology. These products enable a secure computing platform and incorporate Infineon low-power flash memory along with multiple high-performance analog and digital functions. The TRAVEO T2G clock system supports high, and low-speed clocks using both internal and external clock ™...

  • Page 5: Clock System For Traveo

    Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ Clock system for TRAVEO T2G family MCUs ™ Overview of clock system The clock system in this series of MCUs are divided into two blocks. One block selects the clock resources (such as external oscillation and internal oscillation) and multiplies the clock (using FLL and PLL).
  • Page 6 Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ CLK_PATH0 Predivider CLK_HF0 (1/2/4/8) BYPASS_MUX0 ROOT_MUX0 PATH_MUX0 DSI_MUX0 CLK_PATH1 Predivider CLK_HF1 (1/2/4/8) PLL400 ROOT_MUX1 BYPASS_MUX1 EXT_CLK PATH_MUX1 DSI_MUX1 Predivider CLK_HF2 CLK_PATH2 (1/2/4/8) PLL400 ROOT_MUX2...
  • Page 7 Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ Generates high-frequency clock. There are two kinds of PLL—PLL200 and PLL400. PLL200 is without SSCG and fractional operation and PLL400 is with SSCG and fractional operation.
  • Page 8 Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ SDHC Ethernet CLK_HF0 SMIF ROM / SRAM / FLASH CLK_MEM Divider (1-256) CPUSS MEM_CLOCK_CTL register, Fast Infrastructure INT_DIV bit CM0+ CPUSS CLK_SLOW Slow Infrastructure Divider...
  • Page 9 Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ This peripheral clock divider #0 has many peripheral clock dividers to generate the peripheral clock (PCLK). See datasheet for the number of each divider. The output of any of these dividers can be routed to any peripheral.
  • Page 10 Clock configuration setup in TRAVEO T2G Body High family ™ 2 Clock system for TRAVEO T2G family MCUs ™ Divider CLK_GR5 CLK_HF2 CAN FD (1-256) PERI_GR5_CLOCK_CTL register , INT_DIV bit FLEX-RAY EFUSE Divider CLK_GR6 (1-256) PERI_GR6_CLOCK_CTL TCPWM[1] register , INT_DIV bit Divider CLK_GR9 (1-256)

  • Page 11: Basic Clock System Settings

    Basic clock system settings This section describes how to configure the clock system based on a use case using the sample driver library (SDL) provided by Infineon. The code snippets in this application note are part of SDL. For more information, see References.

  • Page 12: Configuration Of The Clock Resources

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Configuration of the clock resources This section explains the function of the clock. Setting the ECO The ECO is disabled by default and needs to be enabled for usage. Also, trimming is necessary to use the ECO. This device can set the trimming parameters that control the oscillator according to crystal unit and ceramic resonator.
  • Page 13 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources • Crystal unit vendor’s recommended value of negative resistance: 1500 ohm • Automatic gain control: OFF Note: These values are decided in consultation with the crystal unit vendor. Table 1 lists the parameters and Table 2...

  • Page 14: Sample Code For Initial Configuration Of Eco Settings

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Table 2 (continued) List of ECO trim settings functions Functions Description Value Disable FLL Wait cycle = Cy_SysClk_FllDisable WAIT_FOR_STABILIZATION Sequence(Wait Cycle) Disable PLL400M_0 PLL number = Cy_SysClk_Pll400M PLL_400M_0_PATH_NO Disable(PLL Number)
  • Page 15 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 1 General configuration of ECO settings /** Wait time definition **/ #define WAIT_FOR_STABILIZATION (10000ul) /* Define TIMEOUT Variable. */ #define CLK_FREQ_ECO (16000000ul) /* Define oscillator parameters to use for software calculation.
  • Page 16 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 2 AllClockConfiguration() function static void AllClockConfiguration(void) /***** ECO setting ******/ cy_en_sysclk_status_t ecoStatus; ecoStatus Cy_SysClk_EcoConfigureWithMinRneg( /* (1)-1. Trim settings for software calculation. See Code Listing CLK_FREQ_ECO, /* (1)-1.
  • Page 17 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 3 Cy_SysClk_EcoEnable() function cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) cy_en_sysclk_status_t rtnval; /* invalid state error if ECO is already enabled */ (SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_EN 0ul) /* 1 = enabled */ /* (2) Check if ECO_OK is already enabled.
  • Page 18 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 4 Cy_SysClk_EcoConfigureWithMinRneg() function cy_en_sysclk_status_t Cy_SysClk_EcoConfigureWithMinRneg(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel, uint32_t minRneg) /* Trim Calculation by software */ /* Check if ECO is disabled */ if(SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_EN 1ul) return(CY_SYSCLK_INVALID_STATE);...
  • Page 19 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources ftrim Cy_SysClk_SelectEcoFtrim(atrim); /* Get Ftrim Value. See Code Listing /* update all fields of trim control register with one write, without changing the ITRIM field: */ un_CLK_ECO_CONFIG2_t tempTrimEcoCtlReg;...
  • Page 20 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 5 Cy_SysClk_SelectEcoAtrim () function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoAtrim(float32_t maxAmplitude) /* Get Atrim Value. */ if((0.50f <= maxAmplitude) && (maxAmplitude < 0.55f)) return(0x04ul); else if(maxAmplitude <...
  • Page 21 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources return(0x00ul); else // invalid input return(CY_SYSCLK_INVALID_TRIM_VALUE); Code Listing 6 Cy_SysClk_SelectEcoAGCEN() function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoAGCEN(float32_t maxAmplitude) /* Get AGC enable setting. */ if((0.50f <= maxAmplitude) &&...
  • Page 22 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 7 Cy_SysClk_SelectEcoWDtrim() function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoWDtrim(float32_t amplitude) /* Get Wdtrim value. */ (0.50f <= amplitude) && (amplitude < 0.60f)) return(0x02ul); else if(amplitude <...
  • Page 23 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 8 Cy_SysClk_SelectEcoGtrim() function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoGtrim(float32_t gm_min) /* Get Gtrim value. */ (0.0f <= gm_min) && (gm_min < 2.2f)) return(0x00ul+1ul); else if(gm_min <...

  • Page 24: Setting Wco

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 9 Cy_SysClk_SelectEcoRtrim() function __STATIC_INLINE uint32_t Cy_SysClk_SelectEcoRtrim(float32_t freqMHz) /* Get Rtrim value. */ if(freqMHz > 28.6f) return(0x00ul); else if(freqMHz > 23.33f) return(0x01ul); else if(freqMHz >...

  • Page 25: Configuration

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Start Define Variables TIMEOUT Define variable to count timeout Configure TIMEOUT Value Configure the initial value of TIMEOUT Write "1" to the WCO_EN bit Write "1"...

  • Page 26: Sample Code

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Table 4 (continued) List of WCO settings functions Functions Description Value Disable PLL200M_0 PLL number = Cy_SysClk_PllDisable(PLL Number) PLL_200M_0_PATH_NO Disable PLL200M_1 PLL number = PLL_200M_1_PATH_NO Clock configuration –...
  • Page 27 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 11 General configuration of WCO settings /** Wait time definition **/ #define WAIT_FOR_STABILIZATION (10000ul) /* Define TIMEOUT variable. */ #define PLL_400M_0_PATH_NO (1ul) /* Define PLL number.

  • Page 28: Setting Imo

    Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Code Listing 12 AllClockConfiguration () function static void AllClockConfiguration(void) /***** WCO setting ******/ cy_en_sysclk_status_t wcoStatus; wcoStatus Cy_SysClk_WcoEnable(WAIT_FOR_STABILIZATION*10ul); /* WCO Enable See Code Listing CY_ASSERT(wcoStatus CY_SYSCLK_SUCCESS);...
  • Page 29 Clock configuration setup in TRAVEO T2G Body High family ™ 3 Configuration of the clock resources Note that ILO0 is used as the operating clock of the watchdog timer (WDT). Therefore, if ILO0 is disabled, it is necessary to disable WDT. To disable ILO0, write ‘0b01’ to the WDT_LOCK bit of the WDT_CTL register, and then write ‘0b00’...

  • Page 30: Configuration Of Fll And Pll

    Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Configuration of FLL and PLL This section shows the configuration of FLL and PLL in the clock system. Setting FLL 4.1.1 Operation overview To use FLL, it is necessary to set FLL. FLL has a current-controlled oscillator (CCO); the output frequency of this CCO is controlled by adjusting the trim of the CCO.

  • Page 31: Use Case

    Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL 4.1.2 Use case • Input clock frequency: 16 MHz • Output clock frequency: 100 MHz 4.1.3 Configuration Table 5 lists the parameters and Table 6 lists the functions of the configuration part of in SDL for FLL settings.
  • Page 32 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 14 General configuration of FLL settings /** Wait time definition **/ #define WAIT_FOR_STABILIZATION (10000ul) /* Define TIMEOUT Variable. */ #define FLL_TARGET_FREQ (100000000ul) /* Define FLL Target Frequency.
  • Page 33 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 16 Cy_SysClk_FllConfigureStandard() function cy_en_sysclk_status_t Cy_SysClk_FllConfigureStandard(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode) /* check for errors */ (SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE 0ul) /* 1 = enabled */ /* (1) Check if FLL is already enabled.
  • Page 34 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL else if(ccoFreq >= CY_SYSCLK_FLL_CCO_BOUNDARY3_FREQ) config.ccoRange CY_SYSCLK_FLL_CCO_RANGE3; else if(ccoFreq >= CY_SYSCLK_FLL_CCO_BOUNDARY2_FREQ) config.ccoRange CY_SYSCLK_FLL_CCO_RANGE2; else if(ccoFreq >= CY_SYSCLK_FLL_CCO_BOUNDARY1_FREQ) config.ccoRange CY_SYSCLK_FLL_CCO_RANGE1; else config.ccoRange CY_SYSCLK_FLL_CCO_RANGE0; /* 4. Compute the FLL reference divider value. */ config.refDiv CY_SYSCLK_DIV_ROUNDUP(inputFreq 250ul, outputFreq);...
  • Page 35 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL break; /* 8. Compute the CCO_FREQ bits will be set by HW */ config.ccoHwUpdateDisable 0ul; /* 9. Compute the settling count, using a 1-usec settling time. */ config.settlingCount (uint16_t)((float32_t)inputFreq 1000000.0f);...
  • Page 36 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 17 Cy_SysClk_FllManualConfigure() function cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config) cy_en_sysclk_status_t returnStatus CY_SYSCLK_SUCCESS; /* check for errors */ (SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE 0ul) /* 1 = enabled */ /* (1) Check if FLL is already enabled.*/ returnStatus CY_SYSCLK_INVALID_STATE;...
  • Page 37 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL SRSS->unCLK_FLL_CONFIG3.u32Register tempConfg3.u32Register; /* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */ un_CLK_FLL_CONFIG4_t tempConfg4; tempConfg4.u32Register SRSS->unCLK_FLL_CONFIG4.u32Register; /* Set CLK_FLL_CONFIG4 register. */ tempConfg4.stcField.u3CCO_RANGE (uint32_t)(config->ccoRange); /* Set CLK_FLL_CONFIG4 register.
  • Page 38 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 18 Cy_SysClk_FllEnable() function cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus) /* first set the CCO enable bit */ SRSS->unCLK_FLL_CONFIG4.stcField.u1CCO_ENABLE 1ul; /* (3) Enable CCO. */ /* Wait until CCO is ready */ while(SRSS->unCLK_FLL_STATUS.stcField.u1CCO_READY 0ul) /* (4) Wait until CCO is...

  • Page 39: Setting Pll

    Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Setting PLL 4.2.1 Operation overview To use PLL, it is necessary to set PLL. Figure 12 shows the steps to set PLL400 and PLL200. For details about PLL400 and PLL200, see the architecture TRM registers...

  • Page 40: Use Case

    Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL 4.2.2 Use case • Input clock frequency: 16.000 MHz • Output clock frequency: 340.000 MHz (PLL400 #0) 196.608 MHz (PLL400 #1) 160.000 MHz (PLL200 #0) 80.000 MHz (PLL200 #1) •...
  • Page 41 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Table 7 (continued) List of PLL 400 settings parameters Parameters Description Value CY_SYSCLK_FLLPLL_OUTPUT FLL output mode _AUTO CY_SYSCLK_FLLPLL_OUTPUT_AUTO: Automatic using lock indicator. CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR _NOTHING: Similar to AUTO, except the clock is gated off when unlocked.
  • Page 42 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Table 7 (continued) List of PLL 400 settings parameters Parameters Description Value manualConfig.feedbackDiv Control bits for feedback divider. p (Calculated value) manualConfig.referenceDiv Control bits for reference divider. q (Calculated value) manualConfig.outputDiv Control bits for output divider.
  • Page 43 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Table 8 (continued) List of PLL 400 settings functions Functions Description Value   Set PLL path No. and PLL manual configure PLL number = (PLL400 #0) PLL400_0_PATH_NO,  ...
  • Page 44 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Table 9 (continued) List of PLL 200 settings parameters Parameters Description Value pllConfig.outputMode Output mode CY_SYSCLK_FLLPLL_OUTPUT _AUTO 0: CY_SYSCLK_FLLPLL_OUTPUT_AUTO CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_N OTHING 2: CY_SYSCLK_FLLPLL_OUTPUT_INPUT 3: CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT manualConfig.feedbackDiv Control bits for feedback divider.

  • Page 45: Sample Code

    Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Table 10 (continued) List of PLL 200 settings functions Functions Description Value Set PLL path No. and PLL manual PLL number = PLL200_0_PATH_NO, Cy_SysClk_PllManual configure (PLL200 #0) PLL manual configure = manualConfig Configure(PLL Number, PLL...
  • Page 46 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 19 General configuration of PLL 400 #0 settings #define PLL400_0_TARGET_FREQ (340000000ul) /* PLL Target frequency. */ #define PLL400_1_TARGET_FREQ (196608000ul) /* PLL Target frequency. */ /** Wait time definition **/ #define WAIT_FOR_STABILIZATION (10000ul)
  • Page 47 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 20 AllClockConfiguration() function static void AllClockConfiguration(void) /***** PLL400M#0(PATH1) source setting ******/ status Cy_SysClk_Pll400MConfigure(PLL_400M_0_PATH_NO, &g_pll400_0_Config); /* PLL400 Configuration. See Code Listing CY_ASSERT(status CY_SYSCLK_SUCCESS); status Cy_SysClk_Pll400MEnable(PLL_400M_0_PATH_NO, WAIT_FOR_STABILIZATION);...
  • Page 48 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 21 Cy_SysClk_Pll400MConfigure() function cy_en_sysclk_status_t Cy_SysClk_Pll400MConfigure(uint32_t clkPath, const cy_stc_pll_400M_config_t *config) /* check for error */ uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPll400MNo(clkPath, &pllNo); /* Check if the valid clock path and PLL400 Number.
  • Page 49 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL manualConfig.sscgDepth config->sscgDepth; manualConfig.sscgRate config->sscgRate; status Cy_SysClk_Pll400MManualConfigure(clkPath, &manualConfig); /* PLL400 Manual Configure. See Code Listing return (status); Application note 002-24434 Rev. *E 2024-04-23...
  • Page 50 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 22 Cy_SysClk_Pll400MManualConfigure() function cy_en_sysclk_status_t Cy_SysClk_Pll400MManualConfigure(uint32_t clkPath, const cy_stc_pll_400M_manual_config_t *config) /* check for error */ uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPll400MNo(clkPath, &pllNo);/* Getting PLL400 PATH Number.
  • Page 51 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL un_CLK_PLL400M_CONFIG2_t tempClkPLL400MConfig2Reg; tempClkPLL400MConfig2Reg.u32Register = SRSS- >CLK_PLL400M[pllNo].unCONFIG2.u32Register; tempClkPLL400MConfig2Reg.stcField.u24FRAC_DIV config->fracDiv; /* (3) Fractional Divider Settings */ tempClkPLL400MConfig2Reg.stcField.u3FRAC_DITHER_EN config->fracDitherEn; tempClkPLL400MConfig2Reg.stcField.u1FRAC_EN config->fracEn; SRSS->CLK_PLL400M[pllNo].unCONFIG2.u32Register tempClkPLL400MConfig2Reg.u32Register; un_CLK_PLL400M_CONFIG3_t tempClkPLL400MConfig3Reg; tempClkPLL400MConfig3Reg.u32Register = SRSS- >CLK_PLL400M[pllNo].unCONFIG3.u32Register;...
  • Page 52 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 24 Cy_SysClk_PllCalucDividers() function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllCalucDividers(uint32_t inFreq, uint32_t targetOutFreq, const cy_stc_pll_limitation_t* lim, uint32_t fracBitNum, uint32_t* feedBackDiv, uint32_t* refDiv, uint32_t* outputDiv, uint32_t* feedBackFracDiv) uint64_t errorMin 0xFFFFFFFFFFFFFFFFull;...
  • Page 53 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL /* OUTPUT_DIV selection */ (uint32_t i_outDiv lim->minOutputDiv; i_outDiv <= lim->maxOutputDiv; i_outDiv++) uint64_t tempVco i_outDiv targetOutFreq; if(tempVco < lim->minFvco) continue; else if(lim->maxFvco < tempVco) break; // (inFreq / refDiv) * feedBackDiv = Fvco // feedBackDiv = Fvco * refDiv / inFreq uint64_t tempFeedBackDivLeftShifted...
  • Page 54 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL return (CY_SYSCLK_SUCCESS); Code Listing 25 Cy_SysClk_Pll400MEnable() function cy_en_sysclk_status_t Cy_SysClk_Pll400MEnable(uint32_t clkPath, uint32_t timeoutus) uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPll400MNo(clkPath, &pllNo); if(status CY_SYSCLK_SUCCESS) return(status); /* first set the PLL enable bit */ SRSS->CLK_PLL400M[pllNo].unCONFIG.stcField.u1ENABLE 1ul;...
  • Page 55 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 26 General configuration of PLL 200 #0 settings #define PLL200_0_TARGET_FREQ (160000000ul) /* PLL Target Frequency. */ #define PLL200_1_TARGET_FREQ (80000000ul) /* PLL Target Frequency. */ /** Wait time definition **/ #define WAIT_FOR_STABILIZATION (10000ul)
  • Page 56 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 27 AllClockConfiguration() function static void AllClockConfiguration(void) /***** PLL200M#0(PATH3) source setting ******/ status Cy_SysClk_PllConfigure(PLL_200M_0_PATH_NO , &g_pll200_0_Config); /* PLL200 Configuration. See Code Listing CY_ASSERT(status CY_SYSCLK_SUCCESS);...
  • Page 57 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 28 Cy_SysClk_PllConfigure() function cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config) /* check for error */ uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPllNo(clkPath, &pllNo); if(status CY_SYSCLK_SUCCESS) return(status);...
  • Page 58 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 29 Cy_SysClk_PllManualConfigure() function cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config) /* check for error */ uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPllNo(clkPath, &pllNo); if(status CY_SYSCLK_SUCCESS) return(status);...
  • Page 59 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL return (CY_SYSCLK_SUCCESS); Code Listing 30 Cy_SysClk_GetPllNo() function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_GetPllNo(uint32_t pathNo, uint32_t* pllNo) /* check for error */ ((pathNo <= SRSS_NUM_PLL400M) (pathNo > (SRSS_NUM_PLL400M SRSS_NUM_PLL))) /* invalid clock path number */ return(CY_SYSCLK_BAD_PARAM);...
  • Page 60 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 31 Cy_SysClk_PllCalucDividers() function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllCalucDividers(uint32_t inFreq, uint32_t targetOutFreq, const cy_stc_pll_limitation_t* lim, uint32_t fracBitNum, uint32_t* feedBackDiv, uint32_t* refDiv, uint32_t* outputDiv, uint32_t* feedBackFracDiv) uint64_t errorMin 0xFFFFFFFFFFFFFFFFull;...
  • Page 61 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL /* OUTPUT_DIV selection */ (uint32_t i_outDiv lim->minOutputDiv; i_outDiv <= lim->maxOutputDiv; i_outDiv++) uint64_t tempVco i_outDiv targetOutFreq; if(tempVco < lim->minFvco) continue; else if(lim->maxFvco < tempVco) break; // (inFreq / refDiv) * feedBackDiv = Fvco // feedBackDiv = Fvco * refDiv / inFreq uint64_t tempFeedBackDivLeftShifted...
  • Page 62 Clock configuration setup in TRAVEO T2G Body High family ™ 4 Configuration of FLL and PLL Code Listing 32 Cy_SysClk_PllEnable() function cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) uint32_t pllNo; cy_en_sysclk_status_t status Cy_SysClk_GetPllNo(clkPath, &pllNo); if(status CY_SYSCLK_SUCCESS) return(status); /* first set the PLL enable bit */ SRSS->unCLK_PLL_CONFIG[pllNo].stcField.u1ENABLE 1ul;...

  • Page 63: Configuration Of The Internal Clock

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Configuration of the internal clock This section explains how to configure the internal clocks as part of the clock system. Configuring the CLK_PATHx CLK_PATHx is used as the input source for root clocks CLK_HFx. CLK_PATHx can select all clock resources including FLL and PLL using DSI_MUX and PATH_MUX.

  • Page 64: Configuring The Clk_Hfx

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Table 11 Configuring CLK_PATHx Register name Bit name Value Selected clock and item CLK_PATH_SELECT PATH_MUX[2:0] 0 (Default) EXT_CLK DSI_MUX other Reserved. Do not use. CLK_DSI_SELECT DSI_MUX[4:0] ILO0...

  • Page 65: Configuring The Clk_Lf

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Table 12 shows the registers necessary for CLK_HFx. See the architecture TRM for more details. Table 12 Configuring of CLK_HFx (x = 0, 1, 2, 3, 4, 5, 6, 7) Register name Bit name Value...

  • Page 66: Configuring The Clk_Fast_0/Clk_Fast_1

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Configuring the CLK_FAST_0/CLK_FAST_1 CLK_FAST_0 and CLK_FAST_1 are generated by dividing CLK_HF1 by (x+1). When configuring CLK_FAST_0 and CLK_FAST_1, configure a value (x = 0..255) divided by the FRAC_DIV bit and INT_DIV bit of the CPUSS_FAST_0_CLOCK_CTL register and CPUSS_FAST_1_CLOCK_CTL register.
  • Page 67 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Start PERI_DIV_CMD.DISABLE=1 Disable the Peripheral Clock Divider. PERI_CLOCK_CTL.DIV_SEL=X_1 Select DIV to use. (X_1 = 0..255) PERI_CLOCK_CTL.TYPE_SEL=X_2 Select TYPE to use. (X_2 = 0, 1, 2, 3) Select “Clock Divider”...

  • Page 68: Example Of Pclk Setting

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock 5.9.1 Example of PCLK setting 5.9.1.1 Use case • Input clock frequency: 80 MHz • Output clock frequency: 2 MHz • Divider type: Clock divider 16.0 •...

  • Page 69: Sample Code (Example Of The Tcpwm Timer)

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Table 14 (continued) List of PCLK (Example of the TCPWM timer) settings parameters Parameters Description Value CY_SYSCLK_DIV_16_BIT Divider type CY_SYSCLK_DIV_8_BIT = 0u, 8-bit divider CY_SYSCLK_DIV_16_BIT = 1u, 16-bit divider CY_SYSCLK_DIV_16_5_BIT = 2u, 16.5-bit fractional divider...
  • Page 70 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 33 General configuration of PCLK (Example of the TCPWM timer) settings #define PCLK_TCPWMx_CLOCKSx_COUNTER PCLK_TCPWM0_CLOCKS0 /* Define PCLK_TCPWMx_CLOCKSx_COUNTER, Define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER. */ #define TCPWM_PERI_CLK_DIVIDER_NO_COUNTER 0u main(void) SystemInit();...
  • Page 71 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 35 Cy_SysClk_PeriphSetDivider() function __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue) (dividerType CY_SYSCLK_DIV_8_BIT) else if (dividerType CY_SYSCLK_DIV_16_BIT) PERI->unDIV_16_CTL[dividerNum].stcField.u16INT16_DIV dividerValue; /* (3) Division Setting to Clock Divider 16.0#0. */ else /* return bad parameter */ return...

  • Page 72: Setting Eco_Prescaler

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock 5.10 Setting ECO_Prescaler 5.10.1 Operation overview ECO_Prescaler divides the ECO, and creates a clock that can be used with CLK_LF. The division function has a 10-bit integer divider and 8-bit fractional divider.

  • Page 73: Configuration

    Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock 5.10.3 Configuration Table 16 lists the parameters and Table 17 lists the functions of the configuration part of in SDL for ECO prescaler settings. Table 16 List of ECO prescaler settings parameters Parameters...
  • Page 74 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 37 General configuration of ECO prescaler settings #define ECO_PRESCALER_TARGET_FREQ (1234567ul) /* Define ECO Prescaler Target Frequency */ #define CLK_FREQ_ECO (16000000ul) /* Define ECO Clock Frequency */ #define PATH_SOURCE_CLOCK_FREQ CLK_FREQ_ECO /** Wait time definition **/ #define WAIT_FOR_STABILIZATION...
  • Page 75 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 39 Cy_SysClk_SetEcoPrescale() function cy_en_sysclk_status_t Cy_SysClk_SetEcoPrescale(uint32_t ecoFreq, uint32_t targetFreq) // Frequency of ECO (4MHz ~ 33.33MHz) might exceed 32bit value if shifted 8 bit. // So, it uses 64 bit data for fixed point operation.
  • Page 76 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 41 Cy_SysClk_EcoPrescaleEnable() function cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleEnable(uint32_t timeoutus) // Send enable command SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_DIV_ENABLE 1ul; /* (2) Enable ECO Prescaler */ // Wait eco prescaler get enabled while(CY_SYSCLK_ECO_PRESCALE_ENABLE Cy_SysClk_GetEcoPrescaleStatus()) /* (3) Wait until...
  • Page 77 Clock configuration setup in TRAVEO T2G Body High family ™ 5 Configuration of the internal clock Code Listing 43 Cy_SysClk_EcoPrescaleDisable() function cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleDisable(uint32_t timeoutus) // Send disable command SRSS->unCLK_ECO_CONFIG.stcField.u1ECO_DIV_DISABLE 1ul; /* (4) Disable ECO Prescaler. */ // Wait eco prescaler actually get disabled while(CY_SYSCLK_ECO_PRESCALE_DISABLE Cy_SysClk_GetEcoPrescaleStatus()) /* (5) Wait until...

  • Page 78: Supplementary Information

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Supplementary information Input clocks in peripheral functions Table 18 Table 27 lists the clock input to each peripheral function. For detailed values of PCLK, see the “Peripheral clocks” section of the datasheet. Table 18 Clock input to TCPWM[0] Peripheral function...
  • Page 79 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Table 20 (continued) Clock input to LIN Peripheral function Operation clock Channel clock (clk_lin_ch) Ch10: PCLK (PCLK_LIN_CLOCK_CH_EN10) Ch11: PCLK (PCLK_LIN_CLOCK_CH_EN11) Ch12: PCLK (PCLK_LIN_CLOCK_CH_EN12) Ch13: PCLK (PCLK_LIN_CLOCK_CH_EN13) Ch14: PCLK (PCLK_LIN_CLOCK_CH_EN14) Ch15: PCLK (PCLK_LIN_CLOCK_CH_EN15) Ch16: PCLK (PCLK_LIN_CLOCK_CH_EN16) Ch17: PCLK (PCLK_LIN_CLOCK_CH_EN17)

  • Page 80: Use Case Of Clock Calibration Counter Function

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Table 24 Clock input to FLEX-RAY Peripheral function Operation clock Channel clock FLEX-RAY CLK_GR5 (Group 5) PCLK (PCLK_FLEXRAY0_CLK_FLEXRAY) Table 25 Clock input to SMIF Peripheral “clk_slow” “clk_mem” “clk_sys”...

  • Page 81: Use Case

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Start Configure ECO and ILO0 Set ECO to Conuter 1 Set ILO0 to Counter 2 Set Count value and Start Counter Check completion of Clock Calibration Calibration Counter Done Counter operation Get ILO Frequency Figure 20...

  • Page 82: Sample Code For Initial Configuration Of Clock Calibration Counter With Ilo0 And Eco

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Table 28 (continued) List of clock calibration counter with ILO0 and ECO settings parameters Parameters Description Value clockMeasuredInfo[].name Measurement clock CY_SYSCLK_MEAS_CLK_ILO0 = clockMeasuredInfo[].measuredFreq Store measurement clock frequency –...
  • Page 83 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Code Listing 44 General configuration of clock calibration counter with ILO0 and ECO settings #define CY_SYSCLK_DIV_ROUND(a, b) (((a) ((b) 2ull)) (b)) /* Define CY_SYSCLK_DIV_ROUND function. */ #define ILO_0 #define ILO_1 /* Define measurement clock (ILO0).
  • Page 84 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Code Listing 45 GetILOClockFreq() function uint32_t GetILOClockFreq(void) uint32_t counter1 40000ul; if((SRSS->unCLK_ECO_STATUS.stcField.u1ECO_OK 0ul) || (SRSS- >unCLK_ECO_STATUS.stcField.u1ECO_READY 0ul)) /* Check ECO status. */ while(1); cy_en_sysclk_status_t status; status Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_ECO, counter1, clockMeasuredInfo[0].name);...
  • Page 85 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Code Listing 46 Cy_SysClk_StartClkMeasurementCounters() function cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2) cy_en_sysclk_status_t rtnval CY_SYSCLK_INVALID_STATE; (!preventCounting /* don't start a measurement if about to enter DeepSleep mode */ SRSS->unCLK_CAL_CNT1.stcField.u1CAL_COUNTER_DONE 0ul/*1 = done*/)

  • Page 86: Ilo0 Calibration Using Clock Calibration Counter Function

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Code Listing 48 Cy_SysClk_ClkMeasurementCountersGetFreq() function cy_en_sysclk_status_t Cy_SysClk_ClkMeasurementCountersGetFreq(uint32_t *measuredFreq, uint32_t refClkFreq) if(SRSS->unCLK_CAL_CNT1.stcField.u1CAL_COUNTER_DONE 1ul) return(CY_SYSCLK_INVALID_STATE); if(clk1Count1 0ul) return(CY_SYSCLK_INVALID_STATE); volatile uint64_t counter2Value (uint64_t)SRSS->unCLK_CAL_CNT2.stcField.u24CAL_COUNTER2; /* Get ILO 0 Count value. */ /* Done counting;...

  • Page 87: Configuration

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Start Define a Target ILO 0 frequency Define ILO number Disable Watchdog Timer Get Current ILO 0 Frequency Calculate the Trimming Step Calculate difference frequency between current and target Get current trimming value Calculate new trimming value Set new trimming value...

  • Page 88: Sample Code For Initial Configuration Of Ilo0 Calibration Using Clock Calibration Counter

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Table 31 List of ILO0 calibration using clock calibration counter settings functions Functions Description Value WDT disable – Cy_WDT_Disable () Unlocks the watchdog timer – Cy_WDT_Unlock() Get current ILO 0 frequency –...
  • Page 89 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Code Listing 50 Cy_SysClk_IloTrim() function int32_t Cy_SysClk_IloTrim(uint32_t iloFreq, uint8_t iloNo) /* Nominal trim step size is 1.5% of "the frequency". Using the target frequency. */ const uint32_t trimStep CY_SYSCLK_DIV_ROUND((uint32_t)CY_SYSCLK_ILO_TARGET_FREQ 15ul, 1000ul);...

  • Page 90: Csv Diagram, And Relationship Of Monitored Clock And Reference Clock

    Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information /* (7) Set New trimming value */ else /* (7) Set New trimming value */ /* (7) Set New trimming value */ SRSS->unCLK_TRIM_ILO1_CTL.stcField.u6ILO1_FTRIM newTrim; /* (7) Set New trimming value */ return (int32_t)(curTrim...
  • Page 91 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information CLK_PATH0 CSV_HF0 Predivider CLK_HF0 (1/2/4/8) BYPASS_MUX0 ROOT_MUX0 PATH_MUX0 DSI_MUX0 CSV_HF1 CLK_PATH1 Predivider CLK_HF1 (1/2/4/8) PLL400 BYPASS_MUX1 ROOT_MUX1 EXT_CLK PATH_MUX1 CSV_HF2 DSI_MUX1 Predivider CLK_HF2 CLK_PATH2 (1/2/4/8) PLL400 ROOT_MUX2 BYPASS_MUX2 CSV_HF3 PATH_MUX2...
  • Page 92 Clock configuration setup in TRAVEO T2G Body High family ™ 6 Supplementary information Table 32 (continued) Monitored clock and reference clock CSV components Monitor clock Reference clock Notes CSV_HF2 CLK_HF2 CLK_REF_HF CLK_REF_HF is selected CLK_IMO, EXT_CLK or CLK_ECO. CSV_HF3 CLK_HF3 CLK_REF_HF CLK_REF_HF is selected CLK_IMO, EXT_CLK or...

  • Page 93: Glossary

    Clock configuration setup in TRAVEO T2G Body High family ™ 7 Glossary Glossary Table 33 Glossary Terms Description AUDIOSS Audio subsystem. See the “Audio subsystem” chapter of TRAVEO ™ architecture TRM for details. CAN FD CAN FD is the CAN with Flexible Data rate, and CAN is the Controller Area Network.
  • Page 94 Clock configuration setup in TRAVEO T2G Body High family ™ 7 Glossary Table 33 (continued) Glossary Terms Description SDHC The secure digital high-capacity host controller. See the “SDHC host controller” chapter of TRAVEO architecture TRM for details. ™ SMIF Serial memory interface. See the “Serial memory interface” chapter of TRAVEO architecture TRM for details.

  • Page 95: References

    Clock configuration setup in TRAVEO T2G Body High family ™ References References The following are the TRAVEO T2G family series datasheets and technical reference manuals. Contact ™ Technical Support to obtain these documents. Device datasheet ® ® • CYT4BF datasheet 32-Bit Arm Cortex -M7 microcontroller TRAVEO T2G family...

  • Page 96: Revision History

    Added flowchart and example codes in all instances. Updated Configuration of the Internal Clock: Added flowchart and example codes in all instances. Removed “Example for Configuring Internal Clock”. 2021-05-25 Updated to Infineon template. 2021-11-29 Corrected “Section 3.4. Setting ILO0/ILO1” 2024-02-19 Added specifications for CYT6BJ series in.

  • Page 97: Disclaimer

    Infineon Technologies, All Rights Reserved. information given herein in the real application. Infineon Technologies’ products may not be used in Infineon Technologies hereby disclaims any and all   any applications where a failure of the product or...

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