Download Print this page

NXP Semiconductors SAFE ASSURE Qorivva MPC5602P Reference Manual

Table Of Contents

page of 954

/ 954
Bookmarks

Advertisement

Quick Links

Download this manual

Qorivva MPC5602P Microcontroller

Reference Manual

Devices Supported:

MPC5601P

MPC5602P

MPC5602PRM

Rev. 4

28 Feb 2012

MPC5602P Microcontroller Reference Manual, Rev. 4

Freescale Semiconductor

1

Advertisement

Need help?

Need help?

Do you have a question about the SAFE ASSURE Qorivva MPC5602P and is the answer not in the manual?

Questions and answers

Summary of Contents for NXP Semiconductors SAFE ASSURE Qorivva MPC5602P

Page 1 Qorivva MPC5602P Microcontroller Reference Manual Devices Supported: MPC5601P MPC5602P MPC5602PRM Rev. 4 28 Feb 2012 MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 2 MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 3 Preface Overview The primary objective of this document is to define the functionality of the MPC5602P family of microcontrollers for use by software and hardware developers. The MPC5602P family is built on ® Power Architecture technology and integrates technologies that are important for today’s electrical hydraulic power steering (EHPS), electric power steering (EPS), airbag applications, anti-lock braking systems (ABS), and motor control applications.
Page 4 MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 5 Chapter 1 Introduction The MPC5602P microcontroller family ..................35 Target applications ..........................36 1.2.1 Application examples .....................36 1.2.1.1 Electric power steering ..................36 1.2.1.2 Airbag .......................37 Features ............................38 Critical performance parameters .....................41 Chip-level features ..........................41 Module features ..........................43 1.6.1 High performance e200z0 core processor ..............43 1.6.2 Crossbar switch (XBAR) ....................43 1.6.3...
Page 6 Chapter 2 MPC5602P Memory Map Chapter 3 Signal Description 100-pin LQFP pinout ........................63 64-pin LQFP pinout ........................64 Pin description ..........................64 3.3.1 Power supply and reference voltage pins ...............64 3.3.2 System pins ........................66 3.3.3 Pin multiplexing ......................66 CTU / ADC / FlexPWM / eTimer connections ................75 Chapter 4 Clock Description Clock architecture ...........................79...
Page 7 4.8.5 Register description ......................90 4.8.5.1 Control Register (CR) ..................90 4.8.5.2 Modulation Register (MR) ................92 4.8.6 Functional description ....................93 4.8.6.1 Normal mode ....................93 4.8.6.2 Progressive clock switching ................93 4.8.6.3 Normal Mode with frequency modulation ............94 4.8.6.4 Powerdown mode .....................96 4.8.7 Recommendations ......................96 Clock Monitor Unit (CMU) ......................96 4.9.1 Overview ........................96...
Page 8 5.7.2 System Clock Disable ....................120 5.7.3 System Clock Dividers ....................120 Auxiliary Clock Generation ......................120 5.8.1 Auxiliary Clock Source Selection ................123 5.8.2 Auxiliary Clock Dividers .....................123 Dividers Functional Description ....................123 5.10 Output Clock Multiplexing ......................124 5.11 Output Clock Division Selection ....................124 Chapter 6 Power Control Unit (MC_PCU) Introduction ...........................125...
Page 9 7.3.2.16 Peripheral Status Register 1 (ME_PS1) ............155 7.3.2.17 Peripheral Status Register 2 (ME_PS2) ............156 7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....156 7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .....157 7.3.2.20 Peripheral Control Registers (ME_PCTL0…143) .........158 Functional Description ........................159 7.4.1 Mode Transition Request ....................159 7.4.2 Modes Details .......................160 7.4.2.1...
Page 10 8.1.1 Overview ........................177 8.1.2 Features .........................178 8.1.3 Reset Sources ........................179 External Signal Description ......................180 Memory Map and Register Definition ..................180 8.3.1 Register Descriptions ....................182 8.3.1.1 Functional Event Status Register (RGM_FES) ..........182 8.3.1.2 Destructive Event Status Register (RGM_DES) ..........184 8.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ......185 8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ......186 8.3.1.5...
Page 11 9.5.2.5 INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–INTC_SSCIR4_7) ................205 9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) ..206 Functional description ........................209 9.6.1 Interrupt request sources ....................217 9.6.1.1 Peripheral interrupt requests ................217 9.6.1.2 Software configurable interrupt requests ............218 9.6.1.3 Unique vector for each interrupt request source ..........218 9.6.2 Priority management ....................218 9.6.2.1...
Page 12 10.2.2.2 System Memory Configuration register (MEMCONFIG) ......232 10.2.2.3 Error Configuration (ERROR) register ............233 10.2.2.4 Debug Status Port (DEBUGPORT) register ..........233 10.2.2.5 Password comparison registers ..............236 10.3 Functional description ........................237 10.4 Initialization/application information ....................237 10.4.1 Reset ..........................237 Chapter 11 System Integration Unit Lite (SIUL) 11.1 Introduction ...........................239 11.2 Overview ............................239 11.3 Features ............................240...
Page 13 Chapter 12 e200z0 and e200z0h Core 12.1 Overview ............................263 12.2 Features ............................263 12.2.1 Microarchitecture summary ..................264 12.2.1.1 Block diagram ....................264 12.2.1.2 Instruction unit features .................266 12.2.1.3 Integer unit features ..................267 12.2.1.4 Load/Store unit features .................267 12.2.1.5 e200z0h system bus features ................267 12.2.1.6 Nexus features ....................267 12.3 Core registers and programmer’s model ..................268...
Page 14 Chapter 15 Error Correction Status Module (ECSM) 15.1 Introduction ...........................281 15.2 Overview ............................281 15.3 Features ............................281 15.4 Memory map and registers description ..................281 15.4.1 Memory map ........................282 15.4.2 Registers description ....................283 15.4.2.1 Processor core type (PCT) register ..............283 15.4.2.2 Revision (REV) register .................283 15.4.2.3 Platform XBAR Master Configuration (PLAMC) .........284 15.4.2.4...
Page 15 Chapter 17 Flash Memory 17.1 Introduction ...........................307 17.2 Platform Flash controller .......................307 17.2.1 Introduction ........................307 17.2.1.1 Overview ......................308 17.2.1.2 Features ......................308 17.2.2 Modes of operation .......................309 17.2.3 External signal descriptions ..................309 17.2.4 Memory map and registers description ................309 17.2.4.1 Memory map ....................310 17.2.5 Functional description ....................311 17.2.6...
Page 16 17.3.7.1 Module Configuration Register (MCR) ............339 17.3.7.2 Low/Mid Address Space Block Locking register (LML) ......344 17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) ...345 17.3.7.4 Secondary Low/Mid Address Space Block Locking register (SLL) .....346 17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL) .........................347 17.3.7.6...
Page 17 18.5.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) ....393 18.5.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR) ......394 18.5.2.10 eDMA Clear Error Register (EDMA_CERR) ..........395 18.5.2.11 eDMA Set START Bit Register (EDMA_SSBR) ..........395 18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) ......396 18.5.2.13 eDMA Interrupt Request Register (EDMA_IRQRL) ........396 18.5.2.14...
Page 18 19.4 DMA request mapping ........................429 19.5 Functional description ........................430 19.5.1 DMA channels with periodic triggering capability ............430 19.5.2 DMA channels with no triggering capability ...............433 19.6 Initialization/application information ....................433 19.6.1 Reset ..........................433 19.6.2 Enabling and configuring sources ................433 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.1 Introduction ...........................437 20.2 Block diagram ..........................437...
Page 19 20.8.1.2 Slave mode .....................462 20.8.1.3 Module disable mode ..................462 20.8.1.4 Debug mode ....................462 20.8.2 Start and stop of DSPI transfers ...................462 20.8.3 Serial Peripheral Interface (SPI) configuration ............463 20.8.3.1 SPI master mode ....................463 20.8.3.2 SPI slave mode ....................464 20.8.3.3 FIFO disable operation ...................464 20.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ......464 20.8.3.5...
Page 20 Chapter 21 LIN Controller (LINFlex) 21.1 Introduction ...........................487 21.2 Main features ..........................487 21.2.1 LIN mode features ......................487 21.2.2 UART mode features ....................487 21.2.3 Features common to LIN and UART ................487 21.3 General description ........................488 21.4 Fractional baud rate generation .....................489 21.5 Operating modes ...........................491 21.5.1 Initialization mode ......................492...
Page 21 21.8.2 LIN mode ........................521 21.8.2.1 Master mode ....................521 21.8.2.2 Slave mode .....................523 21.8.2.3 Slave mode with identifier filtering ...............525 21.8.2.4 Slave mode with automatic resynchronization ..........527 21.8.2.5 Clock gating ....................529 21.8.3 8-bit timeout counter ....................529 21.8.3.1 LIN timeout mode ..................529 21.8.3.2 Output compare mode ..................530 21.8.4...
Page 22 22.4.6.1 Transmission abort mechanism ..............566 22.4.6.2 Message Buffer deactivation ................567 22.4.6.3 Message Buffer lock mechanism ..............568 22.4.7 Rx FIFO ........................569 22.4.8 CAN protocol related features ..................570 22.4.8.1 Remote frames ....................570 22.4.8.2 Overload frames .....................570 22.4.8.3 Time stamp .....................570 22.4.8.4 Protocol timing ....................571 22.4.8.5 Arbitration and matching timing ..............573 22.4.9...
Page 23 23.3.9 Auto-clock-off mode ....................591 23.4 Register descriptions ........................591 23.4.1 Introduction ........................591 23.4.2 Control logic registers ....................593 23.4.2.1 Main Configuration Register (MCR) .............593 23.4.2.2 Main Status Register (MSR) ................594 23.4.3 Interrupt registers ......................596 23.4.3.1 Interrupt Status Register (ISR) ...............596 23.4.3.2 Interrupt Mask Register (IMR) ..............596 23.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR) ......598 23.4.3.4...
Page 24 24.6.1 MDIS bit ........................620 24.6.2 STOP mode ........................620 24.7 Interrupts and DMA requests ......................620 24.7.1 DMA support ........................620 24.7.2 CTU faults and errors ....................620 24.7.3 CTU interrupt/DMA requests ..................621 24.8 Memory map ..........................623 24.8.1 Trigger Generator Sub-unit Input Selection Register (TGSISR) .........627 24.8.2 Trigger Generator Sub-unit Control Register (TGSCR) ..........629 24.8.3...
Page 25 25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers ..........653 25.5.7 EXT_CLK — external clock signal ................653 25.6 Memory map and registers ......................654 25.6.1 FlexPWM module memory map ..................654 25.6.2 Register descriptions ....................657 25.6.3 Submodule registers .....................657 25.6.3.1 Counter Register (CNT) .................657 25.6.3.2 Initial Count Register (INIT) .................657 25.6.3.3...
Page 26 25.8.4 PWM generation ......................691 25.8.5 Output compare capabilities ..................692 25.8.6 Force out logic ......................692 25.8.7 Independent or complementary channel operation ............694 25.8.8 Deadtime insertion logic ....................695 25.8.9 Top/bottom correction ....................696 25.8.10 Manual correction ......................698 25.8.11 Output logic ........................699 25.8.12 Fault protection ......................700 25.8.13 Fault pin filter .......................701 25.8.14...
Page 27 26.6.2.12 Interrupt and DMA enable register (INTDMA) ..........726 26.6.2.13 Comparator Load register 1 (CMPLD1) ............727 26.6.2.14 Comparator Load register 2 (CMPLD2) ............728 26.6.2.15 Compare and Capture Control register (CCCTRL) ........728 26.6.2.16 Input Filter Register (FILT) ................730 26.6.2.17 Input filter considerations ................731 26.6.3 Watchdog timer registers ....................731 26.6.3.1...
Page 28 27.2.3 Modes of operation .......................744 27.2.4 External signal description ...................744 27.2.5 Memory map and registers description ................744 27.2.5.1 Register protection memory map ..............745 27.2.5.2 Registers description ..................746 27.2.6 Functional description ....................748 27.2.6.1 General ......................748 27.2.6.2 Change lock settings ..................748 27.2.6.3 Access errors ....................751 27.2.7 Reset ..........................752...
Page 29 28.2.3.8 Timeout Enable Register (FCU_TER) ............773 28.2.3.9 Module State Register (FCU_MSR) ..............774 28.2.3.10 Microcontroller State Register (FCU_MCSR) ..........774 28.2.3.11 Frozen MC State Register (FCU_FMCSR) ...........776 28.3 Functional description ........................777 28.3.1 State machine ........................778 28.3.2 Output generation protocol ...................779 28.3.2.1 Dual-rail protocol ...................779 28.3.2.2 Time switching protocol ................780 28.3.2.3...
Page 30 30.5 Initialization and application information ..................796 30.5.1 Example configuration ....................796 Chapter 31 System Timer Module (STM) 31.1 Overview ............................799 31.2 Features ............................799 31.3 Modes of operation ........................799 31.4 External signal description ......................799 31.5 Memory map and registers description ..................799 31.5.1 Memory map ........................799 31.5.2 Registers description ....................800...
Page 31 33.5.4 Single chip boot mode ....................821 33.5.4.1 Boot and alternate boot ..................822 33.5.5 Boot through BAM .......................822 33.5.5.1 Executing BAM .....................822 33.5.5.2 BAM software flow ..................823 33.5.5.3 BAM resources ....................824 33.5.5.4 Download and execute the new code .............825 33.5.5.5 Download 64-bit password and password check ...........825 33.5.5.6 Download start address, VLE bit and code size ..........827 33.5.5.7...
Page 32 35.5.1 Reset ..........................856 35.5.2 IEEE 1149.1-2001 defined test modes .................856 35.5.2.1 Bypass mode ....................857 35.5.2.2 TAP sharing mode ..................857 35.6 External signal description ......................857 35.7 Memory map and registers description ..................857 35.7.1 Instruction register ......................858 35.7.2 Bypass register ......................858 35.7.3 Device identification register ..................858 35.7.4 Boundary scan register ....................859...
Page 33 36.6 External signal description ......................871 36.7 Memory map and registers description ..................872 36.8 Interrupts and Exceptions ......................872 36.9 Debug support overview .......................873 36.9.1 Software Debug Facilities ....................873 36.9.1.1 Power Architecture technology compatibility ..........873 36.9.2 Additional Debug Facilities ..................874 36.9.3 Hardware Debug Facilities ...................874 36.9.4 Sharing Debug Resources by Software/Hardware ............874 36.9.4.1...
Page 34 36.12.4.4 e200z0h CPU Clock On Input (jd_mclk_on) ..........909 36.12.4.5 Watchpoint Events (jd_watchpt[0:5]) ............909 36.12.5 e200z0h OnCE Controller and Serial Interface ............909 36.12.5.1 e200z0h OnCE Status Register ..............910 36.12.5.2 e200z0h OnCE Command Register (OCMD) ..........911 36.12.5.3 e200z0h OnCE Control Register (OCR) ............915 36.12.6 Access to Debug Resources ..................917 36.12.7...
Page 35 Chapter 1 Introduction Chapter 1 Introduction The MPC5602P microcontroller family ® The Qorivva MPC5602P microcontroller, a SafeAssure solution, is built on the Power Architecture platform. The Power Architecture based 32-bit microcontrollers represent the latest achievement in integrated automotive application controllers. This device family integrates the most advanced and up-to-date motor control design features.
Page 36 Chapter 1 Introduction Target applications The MPC5602P belongs to an expanding range of automotive-focused products designed to address and target the following chassis and safety market segments: • Electric hydraulic power steering (EHPS) • Lower end of electric power steering (EPS) •...
Page 37 Chapter 1 Introduction PMSM 3-phase Low Voltage Power Stage Position Sensor Gearbox U DC Bus Load Position Sensor Physical Layer Torque Driver Signal Reverse Bat System Signal Conditioning Driver Protection Conditioning Circuitry Basis Circuitry Chip Vanalog Vref Relay Fast ADC Timer <1 µs, 10-bit Relay Driver...
Page 38 Chapter 1 Introduction DSPI X/Y - accel. Physical Satellite I/F Body network (dashboard) CAN Physical Interface FlexCAN Layer Physical Satellite I/F Interface Occupant detection LIN Physical LINFlex Layer Physical Satellite I/F Interface MPC5602P BOOST Physical Satellite I/F Interface Squib 1 DSPI DSPI Squib 2...
Page 39 Chapter 1 Introduction Table 1-1. MPC5602P device comparison (continued) Feature MPC5601P MPC5602P Safety port Yes (via FlexCAN module) Yes (via second FlexCAN module) FCU (fault collection unit) CTU (cross triggering unit) eTimer 1 (16-bit, 6 channels) FlexPWM (pulse-width modulation) channels (capture capability not supported) Analog-to-digital converter (ADC)
Page 40 Chapter 1 Introduction External ballast e200z0 Core 32-bit 1.2 V regulator control general purpose registers XOSC Integer Special Exception Interrupt execution purpose handler controller 16 MHz unit registers RC oscillator Variable Instruction length FMPLL_0 unit encoded (System) instructions Branch Load/store JTAG prediction unit...
Page 41 Chapter 1 Introduction Critical performance parameters • Fully static operation, 0–64 MHz • –40 °C to 150 °C junction temperature • Low power design — Less than 450 mW power dissipation — Halt and STOP mode available for power reduction —...
Page 42 Chapter 1 Introduction — 16-channel eDMA controller — 16 priority level controller — Up to 25 external interrupts — PIT implements four 32-bit timers — 120 interrupts are routed via INTC • General purpose I/Os — Individually programmable as input, output or special function —...
Page 43 Chapter 1 Introduction — 3.3 V or 5 V supply for I/Os and ADC — On-chip single supply voltage regulator with external ballast transistor • Operating temperature ranges: –40 to 125 °C or –40 to 105 °C Module features 1.6.1 High performance e200z0 core processor The e200z0 Power Architecture core provides the following features: •...
Page 44 Chapter 1 Introduction The crossbar provides the following features: • 3 master ports: — e200z0 core complex instruction port — e200z0 core complex Load/Store Data port — eDMA • 3 slave ports: — Flash memory (Code and Data) — SRAM —...
Page 45 Chapter 1 Introduction buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states. The flash memory module provides the following features: • As much as 320 KB flash memory —...
Page 46 Chapter 1 Introduction • Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back-to-back with a read to same memory block 1.6.6 Interrupt controller (INTC) The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems.
Page 47 Chapter 1 Introduction 1.6.8 System clocks and clock generation The following list summarizes the system clock and clock generation on the MPC5602P: • Lock detect circuitry continuously monitors lock status • Loss of clock (LOC) detection for PLL outputs Programmable output clock divider (1, 2, 4, 8) •...
Page 48 Chapter 1 Introduction • Nominal frequency 16 MHz • ±5% variation over voltage and temperature after process trim • Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the PLL •...
Page 49 Chapter 1 Introduction • Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device and/or other circuitry (for example, a safety relay) • Faults are latched into a register 1.6.16 System integration unit –...
Page 50 Chapter 1 Introduction • Ability to accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory 1.6.18 Error correction status module (ECSM) The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes, and information on platform memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.
Page 51 Chapter 1 Introduction — Programmable bit rate up to 1 Mbit/s • 32 message buffers of up to 8-bytes data length • Each message buffer configurable as Rx or Tx, all supporting standard and extended messages • Programmable loop-back mode supporting self-test operation •...
Page 52 Chapter 1 Introduction • LIN state machine compliant to LIN1.3, 2.0 and 2.1 specifications • Handles LIN frame transmission and reception without CPU intervention • LIN features — Autonomous LIN frame handling — Message buffer to store Identifier and up to 8 data bytes —...
Page 53 Chapter 1 Introduction • End-of-transmission interrupt flag • Programmable transfer baud rate • Programmable data frames from 4 to 16 bits • Up to 8 chip select lines available: — 8 on DSPI_0 — 4 each on DSPI_1 and DSPI_2 •...
Page 54 Chapter 1 Introduction • PWMX pin can optionally output a third PWM signal from each submodule • Channels not used for PWM generation can be used for buffered output compare functions • Channels not used for PWM generation can be used for input capture functions •...
Page 55 Chapter 1 Introduction — 1 sample and hold unit — Conversion time, including sampling time, less than 1 µs (at full precision) — Typical sampling time is 150 ns minimum (at full precision) — DNL/INL ±1 LSB — TUE < 1.5 LSB —...
Page 56 Chapter 1 Introduction • Trigger generation unit configurable in sequential mode or in triggered mode • Each trigger can be appropriately delayed to compensate the delay of external low pass filter • Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation •...
Page 57 Chapter 1 Introduction • IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO) • Selectable modes of operation include JTAGC/debug or normal system operation. • 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: — BYPASS —...
Page 58 Chapter 1 Introduction • 64-pin LQFP, 0.5 mm pitch, 10 mm × 10 mm outline • 100-pin LQFP, 0.5 mm pitch, 14 mm × 14 mm outline MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 59 Chapter 2 MPC5602P Memory Map Chapter 2 MPC5602P Memory Map Table 2-1 shows the memory map for the MPC5602P. All addresses on the MPC5602P, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block.
Page 60 Chapter 2 MPC5602P Memory Map Table 2-1. Memory map (continued) Size Start address End address Region name (KB) 0xC3FE_4000 0xC3FE_7FFF Reset Generation Module (RGM) 0xC3FE_8000 0xC3FE_BFF Power Control Unit (PCU) 0xC3FE_C00 0xC3FE_FFF Reserved 0xC3FF_0000 0xC3FF_3FFF Periodic Interrupt Timer (PIT) 0xC3FF_4000 0xC3FF_FFFF Reserved 0xFFE0_0000 0xFFE0_3FFF Analog to Digital Converter 0 (ADC_0)
Page 61 Chapter 2 MPC5602P Memory Map Table 2-1. Memory map (continued) Size Start address End address Region name (KB) 0xFFFC_0000 0xFFFC_3FFF FlexCAN_0 (CAN0) 0xFFFC_4000 0xFFFD_BFF Reserved 0xFFFD_C00 0xFFFD_FFF DMA Multiplexer (DMA_MUX) 0xFFFE_0000 0xFFFE_7FFF Reserved 0xFFFE_8000 0xFFFE_BFF Safety Port (FlexCAN) 0xFFFE_C00 0xFFFF_BFFF Reserved 0xFFFF_C000 0xFFFF_FFFF Boot Assist Module (BAM)
Page 62 Chapter 2 MPC5602P Memory Map MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 63 Chapter 3 Signal Description Chapter 3 Signal Description This chapter describes the signals of the MPC5602P. It includes a table of signal properties and detailed descriptions of signals. 100-pin LQFP pinout Figure 3-1 shows the pinout of the 100-pin LQFP. A[4] VPP_TEST A[6]...
Page 64 Chapter 3 Signal Description 64-pin LQFP pinout A[4] VPP_TEST A[6] D[14]] A[7] A[8] D[12] D[13 A[5] VSS_LV_COR1 VDD_HV_IO1 VSS_HV_IO1 VDD_LV_COR1 A[3] D[9] 64 LQFP VDD_HV_OSC VDD_HV_IO2 VSS_HV_IO2 VSS_HV_OSC XTAL EXTAL RESET D[8] VSS_LV_COR0 C[12] C[11] VDD_LV_COR0 Figure 3-2. 64-pin LQFP pinout(top view) Pin description The following sections provide signal descriptions and related information about the functionality and configuration of the MPC5602P devices.
Page 65 Chapter 3 Signal Description Table 3-1. Supply pins Supply Symbol Description 64-pin 100-pin VREG control and power supply pins. Pins available on 64-pin and 100-pin packages BCTRL Voltage regulator external NPN ballast base control pin Voltage regulator supply voltage DD_HV_REG (3.3 V or 5.0 V) ADC_0 reference and supply voltage.
Page 66 Chapter 3 Signal Description 3.3.2 System pins Table 3-2 Table 3-3 contain information on pin functions for the MPC5602P devices. The pins listed Table 3-2 are single-function pins. The pins shown in Table 3-3 are multi-function pins, programmable via their respective pad configuration register (PCR) values. Table 3-2.
Page 67 Chapter 3 Signal Description Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. For more information, see “Pad AC Specifications” in the device data sheet. Table 3-3. Pin muxing Pad speed Port Alternate Functions...
Page 68 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin A[7] PCR[7] ALT0 GPIO[7] SIUL Slow Medium ALT1 SOUT DSPI_1 ALT2 — — — ALT3 —...
Page 69 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin A[15] PCR[15] ALT0 GPIO[15] SIUL Slow Medium ALT1 — — — ALT2 — — —...
Page 70 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin B[9] PCR[25] ALT0 GPIO[25] SIUL Input only — — ALT1 — — ALT2 — —...
Page 71 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin Port C (16-bit) C[0] PCR[32] ALT0 GPIO[32] SIUL Input only — — — ALT1 —...
Page 72 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin C[8] PCR[40] ALT0 GPIO[40] SIUL Slow Medium ALT1 DSPI_1 ALT2 — — — ALT3 DSPI_0 C[9] PCR[41]...
Page 73 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin D[1] PCR[49] ALT0 GPIO[49] SIUL Slow Medium — ALT1 — — — ALT2 — —...
Page 74 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin D[12 PCR[60] ALT0 GPIO[60] SIUL Slow Medium ALT1 X[1] FlexPWM_0 ALT2 — — — ALT3 —...
Page 75 Chapter 3 Signal Description Table 3-3. Pin muxing (continued) Pad speed Port Alternate Functions Peripheral register function direction SRC = 0 SRC = 1 64-pin 100-pin E[6] PCR[70] ALT0 GPIO[70] SIUL Input only — — — ALT1 — — ALT2 —...
Page 76 Chapter 3 Signal Description External pins FlexPWM External pins PWMA0 Master reload PWM_REL TRIGGER_0 ADC0 PWMB0 OUT_TRIG0_0 PWM_ODD_0 ADC_CMD_0 PWMA1 OUT_TRIG0_1 PWM_ODD_1 NEXT_CMD_0 PWMB1 OUT_TRIG0_2 PWM_ODD_2 FIFO_0 CTU/ADC OUT_TRIG0_3 TRIGGER_1 PWMA2 PWM_ODD_3 IP Interface (ipp_ind_injection_trg) PWMB2 OUT_TRIG1_0 PWM_EVEN_0 ADC_CMD_1 OUT_TRIG1_1 NEXT_CMD_1 PWMA3 PWM_EVEN_1...
Page 77 Chapter 3 Signal Description Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued) Source module Target module Comment (Signal) (Signal) PWM (PWMA0) SIU lite — PWM (PWMB0) SIU lite — PWM (PWMX1) SIU lite — PWM (PWMA1) SIU lite —...
Page 78 Chapter 3 Signal Description Table 3-4. CTU / ADC / FlexPWM / eTimer connections (continued) Source module Target module Comment (Signal) (Signal) SIU lite PWM (EXT_SYNC) The same GPIO pin as used for CTU (EXT_IN) and the PWM (EXT_SYNC) SIU lite PWM (FAULT0) —...
Page 79 Chapter 4 Clock Description Chapter 4 Clock Description This chapter describes the clock architectural implementation for MPC5602P. The following clock related modules are implemented on the MPC5602P: • Clock, Reset, and Mode Handling — Clock Generation Module (CGM) (see Chapter 5, “Clock Generation Module (MC_CGM)) —...
Page 80 Chapter 4 Clock Description IRC_CLK IRC_CLK RC Oscillator (IRC) 16 MHz 16 MHz SYS_CLK FMPLL_0_PCS_CLK PHI_PCS FMPLL_0 Oscillator FMPLL_0_CLK 64 MHz—50% 64 MHz (XOSC40) XOSC_CLK XOSC_CLK 8 MHz—50% 8 MHz—50% Clockout  1,  2,  4,  8 30/32 MHz Clock Out Divider IRC_CLK XOSC_CLK...
Page 81 Chapter 4 Clock Description SafetyPort SP_CLK Module Clock XOSC_CLK Protocol Clock SP_CLK IPS @ SP_CLK IPS @ SYS_CLK eTimer_0 MC_CLK Module Clock IPS @ MC_CLK FlexPWM MC_CLK Module Clock IPS @ MC_CLK ADC_0 MC_CLK Module Clock IPS @ MC_CLK DSPI_0 Module Clock SYS_CLK DSPI_1...
Page 82 Chapter 4 Clock Description SYS_CLK SYS_CLK LINFlex_0 SYS_CLK SYS_CLK Module clock Module clock LINFlex_1 ECSM SYS_CLK SYS_CLK Module clock Module clock Platform Flash Controller SYS_CLK SYS_CLK Module clock Code Flash 0 Module clock IRCOSC_CLK Protocol clock Data Flash 0 DMA Mux SIUL SYS_CLK SYS_CLK...
Page 83 Chapter 4 Clock Description • Internal RC oscillator clock (IRC) • Progressive output clock of FMPLL_0 • Directly from the oscillator clock (XOSC) Its behavior is configured via software through ME_x_MC register of the ME module. When the standard boot from internal flash is selected via the boot configuration pins, the clock source for the system clock (SYS_CLK) after reset (DRUN mode) is the internal RC oscillator (IRC).
Page 84 Chapter 4 Clock Description Alternate module clock domains This section lists the different clock domains for each module. If not otherwise noted, all modules on the MPC5602P device are clocked on the SYS_CLK. 4.3.1 FlexCAN clock domains The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is always derived from the system clock.
Page 85 Chapter 4 Clock Description 4.3.4.3 ADC_0 clock domain The ADC_0 module has only one clock domain. The ADC_0 module is clocked from the MC_PLL_CLK. Therefore, it is placed behind the IPS bus clock sync bridge. 4.3.4.4 Safety Port clock domains The Safety Port module has two distinct software-controlled clock domains.
Page 86 Chapter 4 Clock Description • The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and the XOSC signal against the IRC and provides clock out of range information about the monitored clock signals. • FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent to the CGM module.
Page 87 Chapter 4 Clock Description XOSC external crystal oscillator The external crystal oscillator (XOSC) operates in the range of 4 MHz to 40 MHz. The XOSC digital interface contains the control and status registers accessible for the external crystal oscillator. Main features are: •...
Page 88 Chapter 4 Clock Description 4.7.2 Register description Table 4-3. OSC_CTL memory map Offset from OSC_CTL_BASE Register Access Reset value Location (0xC3FE_0000) 0x0000 OSC_CTL—Oscillator control register 0x0080_0000 on page 88 0x0004–0x000F Reserved Address: 0xC3FE_0000 Access: Supervisor read/write; User read-only (Base + 0x0000) R OSC EOCV[7:0] Reset...
Page 89 Chapter 4 Clock Description Frequency Modulated Phase Locked Loop (FMPLL) 4.8.1 Introduction This section describes the features and functions of the FMPLL module implemented in MPC5602P. 4.8.2 Overview The FMPLL enables the generation of high speed system clocks from a common 4–40 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock.
Page 90 Chapter 4 Clock Description — Normal Mode with SSCG — Powerdown mode 4.8.4 Memory map Table 4-5 shows the memory map locations. Addresses are given as offsets of the module base address. Table 4-5. FMPLL memory map Offset from ME_CGM_BASE Register Access Reset value...
Page 91 Chapter 4 Clock Description Table 4-6. CR field descriptions Field Description IDF[3:0] Input Division Factor The value of this field sets the PLL input division factor. 0000: Divide by 1 0001: Divide by 2 0010: Divide by 3 0011: Divide by 4 0100: Divide by 5 0101: Divide by 6 0110: Divide by 7...
Page 92 Chapter 4 Clock Description Table 4-6. CR field descriptions (continued) Field Description pll_fail_mask This bit masks the pll_fail output. 0: pll_fail not masked 1: pll_fail masked pll_fail_flag This bit is asynchronously set by hardware whenever a loss of lock event occurs while PLL is switched on.
Page 93 Chapter 4 Clock Description Table 4-7. MR field descriptions (continued) Field Description FM_EN Frequency modulation enable The FM_EN bit enables the frequency modulation. 0: Frequency Modulation disabled 1: Frequency Modulation enabled INC_STEP Increment step The INC_STEP field is the binary equivalent of the value incstep derived from following formula: ...
Page 94 Chapter 4 Clock Description Table 4-8. Progressive clock switching on pll_select rising edge (continued) Number of PLL output clock cycles ck_pll_div frequency (PLL output frequency) onward (ck_pll_out frequency) Division factors ck_pll_out ck_pll_div of 8, 4, 2, or 1 Figure 4-9. Progressive clock switching scheme 4.8.6.3 Normal Mode with frequency modulation The FMPLL default mode is without frequency modulation enabled.
Page 95 Chapter 4 Clock Description • PLL output frequency = 256 MHz/ODF • Spread: Center spread (SPREAD_CONTROL = 0) • Modulation frequency = 24 kHz • Modulation depth = ±2.0% (4% pk-pk) Using the formulae for MODPERIOD and INCSTEP: MODPERIOD = Round [(4e06) / (4 × 24e03)] = Round [41.66] = 42 Eqn.
Page 96 Chapter 4 Clock Description 4.8.6.4 Powerdown mode To reduce consumption, the FMPLL can be switched off when not required by programming the registers ME_x_MC on the ME module. 4.8.7 Recommendations To avoid any unpredictable behavior of the PLL clock, it is recommended to follow these guidelines: •...
Page 97 Chapter 4 Clock Description XOSC valid (on AND stable) / off CMU_0 Clock FMPLL_0 valid (on AND locked) / off Control Logic IRC_CLK CK 0 (reference) 16 MHz XOSC_CLK Loss of crystal CK XOSC 4 to 40 MHz FMPLL_0 FMPLL_0 freq. CK PLL 64 MHz out of range...
Page 98 Chapter 4 Clock Description 4.9.3.2 PLL clock monitor The PLL clock CK_PLL frequency can be monitored by programming bit CME_0 of the CMU_0_CSR to ‘1’. The CK_PLL monitor starts as soon as bit CME_0 is set. This monitor can be disabled at any time by writing bit CME_0 to ‘0’.
Page 99 Chapter 4 Clock Description If F is less than a reference value determined by the CMU_1_LFREFR_A[LFREF_A] bits and SYS_CLK the system clock is enabled, then: • CMU_1_ISR[FLLI] is set • A failure event is signaled to the MC_RGM and FCU, which in turn can generate a ‘functional’ reset, a SAFE mode request, or an interrupt NOTE The system clock monitor may produce a false event when F...
Page 100 Chapter 4 Clock Description Table 4-10. CMU memory map (continued) Offset from CMU_BASE Register Access Reset value Location (0xC3FE_0100) 0x0018 Measurement Duration Register (CMU_0_MDR) 0x0000_0000 on page 103 0x001C–0x3FFF Reserved 4.9.4.1 Control Status Register (CMU_0_CSR) Address: Base + 0x0000 Access: User read/write Reset RCDIV[1:0] Reset...
Page 101 Chapter 4 Clock Description 4.9.4.2 Frequency Display Register (CMU_0_FDR) Address: Base + 0x0004 Access: User read-only FD[19:16] Reset FD[15:0] Reset Figure 4-13. Frequency Display Register (CMU_0_FDR) Table 4-12. CMU_0_FDR field descriptions Field Description FD[19:0] Measured frequency bits This register displays the measured frequency f with respect to f .
Page 102 Chapter 4 Clock Description 4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) Address: Base + 0x000C Access: User read/write Reset LFREF[11:0] Reset Figure 4-15. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) Table 4-14. CMU_0_LFREFR_A fields descriptions Field Description LFREF_A Low Frequency reference value These bits determine the low reference value for the FMPLL_0.
Page 103 Chapter 4 Clock Description Table 4-15. CMU_0_ISR field descriptions (continued) Field Description FHHI_0 FMPLL_0 Clock frequency higher than high reference interrupt This bit is set by hardware when CK_FMPLL_ 0 frequency becomes higher than HFREF_A value and CK_FMPLL_0 is ‘ON’ and the PLL locked as signaled by the ME. It can be cleared by software by writing 1.
Page 104 Chapter 4 Clock Description MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 105 Chapter 5 Clock Generation Module (MC_CGM) Chapter 5 Clock Generation Module (MC_CGM) Overview The clock generation module (MC_CGM) generates reference clocks for all the SoC blocks. The MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the system clock selection (see the MC_ME chapter for more details).
Page 106 Chapter 5 Clock Generation Module (MC_CGM) MC_CGM 16 MHz_IRC MC_ME XOSC0 Registers Platform Interface MC_RGM PLL0 System Clock peripherals Multiplexer/Divider Auxiliary Clock PAD[22] Selector/Divider core Output Clock Selector/Divider mapped peripherals Figure 5-1. MC_CGMBlock Diagram Features The MC_CGM includes the following features: •...
Page 107 Chapter 5 Clock Generation Module (MC_CGM) • contains a set of registers to control peripheral clock selection • supports multiple clock sources and maps their address spaces to its memory map • generates an output clock • guarantees glitch-less clock transitions when changing the system clock selection •...
Page 108 Chapter 5 Clock Generation Module (MC_CGM) Table 5-2. MC_CGM Memory Map 0xC3FE _0000 … XOSC registers 0xC3FE _001C 0xC3FE _0020 … reserved 0xC3FE _003C 0xC3FE _0040 … reserved 0xC3FE _005C 0xC3FE _0060 … IRCOSC registers 0xC3FE _007C 0xC3FE _0080 … reserved 0xC3FE _009C...
Page 109 Chapter 5 Clock Generation Module (MC_CGM) Table 5-2. MC_CGM Memory Map (continued) 0xC3FE _0120 … reserved 0xC3FE _013C 0xC3FE _0140 … reserved 0xC3FE _015C 0xC3FE _0160 … reserved 0xC3FE _017C 0xC3FE _0180 … reserved 0xC3FE _019C 0xC3FE _01A0 … reserved 0xC3FE _01BC 0xC3FE...
Page 110 Chapter 5 Clock Generation Module (MC_CGM) Table 5-2. MC_CGM Memory Map (continued) 0xC3FE _0240 … reserved 0xC3FE _025C 0xC3FE _0260 … reserved 0xC3FD _C27C 0xC3FE _0280 … reserved 0xC3FE _029C 0xC3FE _02A0 … reserved 0xC3FE _02BC 0xC3FE _02C0 … reserved 0xC3FE _02DC 0xC3FE...
Page 111 Chapter 5 Clock Generation Module (MC_CGM) Table 5-2. MC_CGM Memory Map (continued) 0xC3FE _0360 … reserved 0xC3FE _036C 0xC3FE CGM_OC_EN R _0370 0xC3FE CGM_OCDS_ SELDIV SELCTL _0374 0xC3FE CGM_SC_SS SELSTAT _0378 0xC3FE CGM_SC_DC DIV0 _037C 0xC3FE CGM_AC0_S SELCTL _0380 0xC3FE CGM_AC0_D DIV0 _0384...
Page 112 Chapter 5 Clock Generation Module (MC_CGM) Table 5-2. MC_CGM Memory Map (continued) 0xC3FE CGM_AC1_D DIV0 _038C 0xC3FE CGM_AC2_S SELCTL _0390 0xC3FE CGM_AC2_D DIV0 _0394 0xC3FE _0398 … reserved 0xC3FE _3FFC Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian.
Page 113 Chapter 5 Clock Generation Module (MC_CGM) Table 5-3. Output Clock Enable Register (CGM_OC_EN) Field Descriptions Field Description Output Clock Enable control 0 Output Clock is disabled 1 Output Clock is enabled 5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) Address 0xC3FE_0374 Access: User read, Supervisor read/write, Test read/write SELDIV SELCTL...
Page 114 Chapter 5 Clock Generation Module (MC_CGM) 5.5.3 System Clock Select Status Register (CGM_SC_SS) Address 0xC3FE_0378 Access: User read, Supervisor read, Test read SELSTAT Reset Reset Figure 5-4. System Clock Select Status Register (CGM_SC_SS) This register provides the current system clock source selection. Table 5-5.
Page 115 Chapter 5 Clock Generation Module (MC_CGM) Table 5-6. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions Field Description Divider 0 Enable 0 Disable system clock divider 0 1 Enable system clock divider 0 DIV0 Divider 0 Division Value — The resultant divided system clock 0 will have a period DIV0 + 1 times that of the system clock.
Page 116 Chapter 5 Clock Generation Module (MC_CGM) 5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Address 0xC3FE_0384 Access: User read, Supervisor read/write, Test read/write DIV0 Reset Reset Figure 5-7. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) This register controls the auxiliary clock 0 divider. Table 5-8.
Page 117 Chapter 5 Clock Generation Module (MC_CGM) Table 5-9. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions Field Description SELCTL Auxiliary Clock 1 Source Selection Control — This value selects the current source for auxiliary clock 0000 (no clock) 0001 reserved 0010 reserved 0011 reserved 0100 reserved...
Page 118 Chapter 5 Clock Generation Module (MC_CGM) 5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Address 0xC3FE_0390 Access: User read, Supervisor read/write, Test read/write SELCTL Reset Reset Figure 5-10. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) This register is used to select the current clock source for the following clocks: •...
Page 119 Chapter 5 Clock Generation Module (MC_CGM) 5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Address 0xC3FE_0394 Access: User read, Supervisor read/write, Test read/write DIV0 Reset Reset Figure 5-11. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) This register controls the auxiliary clock 2 divider. Table 5-12.
Page 120 Chapter 5 Clock Generation Module (MC_CGM) system clock is disabled if 16 MHz int. RC osc. ME_<current mode>_MC.SYSCLK = “1111” 4 MHz crystal osc. system PLL ’0’ system clock CGM_SC_DC0 Register divided system clock 0 MC_RGM SAFE mode request clock divider “0000”...
Page 121 Chapter 5 Clock Generation Module (MC_CGM) (no clock) (no clock) (no clock) (no clock) (unused) (no clock) CGM_AC0_DC0 Register (unused) clock divider CGM_AC0_SC Register Figure 5-13. MC_CGM Auxiliary Clock 0 Generation Overview MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 122 Chapter 5 Clock Generation Module (MC_CGM) (no clock) (unused) CGM_AC1_DC0 Register (unused) clock divider CGM_AC1_SC Register Figure 5-14. MC_CGM Auxiliary Clock 1 Generation Overview MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 123 Chapter 5 Clock Generation Module (MC_CGM) (no clock) (no clock) (no clock) (no clock) (unused) (no clock) CGM_AC2_DC0 Register (unused) clock divider CGM_AC2_SC Register Figure 5-15. MC_CGM Auxiliary Clock 2 Generation Overview 5.8.1 Auxiliary Clock Source Selection During normal operation, the auxiliary clock selection is done via the CGM_AC0…2_SC registers. If software selects an ‘unavailable’...
Page 124 Chapter 5 Clock Generation Module (MC_CGM) The reset value of all counters is ‘1’. If a divider has its DE bit in the respective configuration register set to ‘0’ (the divider is disabled), any value in its DIVn field is ignored. 5.10 Output Clock Multiplexing The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as...
Page 125 Chapter 6 Power Control Unit (MC_PCU) Chapter 6 Power Control Unit (MC_PCU) Introduction 6.1.1 Overview The power control unit (MC_PCU) acts as a bridge for mapping the PMU peripheral to the MC_PCU address space. Figure 6-1 depicts the MC_PCU block diagram. MC_PCU Registers Platform Interface...
Page 126 Chapter 6 Power Control Unit (MC_PCU) 6.1.2 Features The MC_PCU includes the following features: • maps the PMU registers to the MC_PCU address space External Signal Description The MC_PCU has no connections to any external pins. Memory Map and Register Definition 6.3.1 Memory Map Table 6-1.
Page 127 Chapter 6 Power Control Unit (MC_PCU) Table 6-2. MC_PCU Memory Map (continued) 0xC3FE _8080 … PMU registers 0xC3FE _80FC 0xC3FE _8100 … reserved 0xC3FE _BFFC 6.3.2 Register Descriptions All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian.
Page 128 Chapter 6 Power Control Unit (MC_PCU) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 129 Chapter 7 Mode Entry Module (MC_ME) Chapter 7 Mode Entry Module (MC_ME) Introduction 7.1.1 Overview The MC_ME controls the SoC mode and mode transition sequences in all functional states. It also contains configuration, control and status registers accessible for the application. Figure 7-1 depicts the MC_ME Block Diagram.
Page 130 Chapter 7 Mode Entry Module (MC_ME) MC_ME VREG Flashes Registers Platform Interface MC_RGM 16 MHz_IRC MC_CGM XOSC0 PLL0 core Device Mode State Machine peripherals WKPU Figure 7-1. MC_ME Block Diagram MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 131 Chapter 7 Mode Entry Module (MC_ME) 7.1.2 Features The MC_ME includes the following features: • control of the available modes by the ME_ME register • definition of various device mode configurations by the ME_<mode>_MC registers • control of the actual device mode by the ME_MCTL register •...
Page 132 Chapter 7 Mode Entry Module (MC_ME) Table 7-1. MC_ME Mode Descriptions (continued) Name Description Entry Exit TEST This is a chip-wide service mode which is intended to software request system reset provide a control environment for device software teting. from DRUN assertion, DRUN via software RUN0…3...
Page 133 Chapter 7 Mode Entry Module (MC_ME) 7.3.1 Memory Map Table 7-2. MC_ME Register Description Access Address Name Description Size Location User Supervisor Test 0xC3FD ME_GS Global Status word read read read on page 140 _C000 0xC3FD ME_MCTL Mode Control word read read/write read/write...
Page 134 Chapter 7 Mode Entry Module (MC_ME) Table 7-2. MC_ME Register Description (continued) Access Address Name Description Size Location User Supervisor Test 0xC3FD ME_PS2 Peripheral Status 2 word read read read on page 156 _C068 0xC3FD ME_RUN_PC0 Run Peripheral word read read/write read/write on page 156...
Page 135 Chapter 7 Mode Entry Module (MC_ME) Table 7-2. MC_ME Register Description (continued) Access Address Name Description Size Location User Supervisor Test 0xC3FD ME_PCTL49 LIN_FLEX_1 Control byte read read/write read/write on page 158 _C0F1 0xC3FD ME_PCTL92 PIT Control byte read read/write read/write on page 158 _C11C...
Page 136 Chapter 7 Mode Entry Module (MC_ME) Table 7-3. MC_ME Memory Map (continued) 0xC3FD ME_IM _C010 0xC3FD ME_IMTS _C014 w1c w1c w1c w1c w1c 0xC3FD ME_DMTS _C018 PREVIOUS_MODE 0xC3FD reserved _C01C 0xC3FD ME_RESET_ _C020 DFLAON CFLAON SYSCLK MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 137 Chapter 7 Mode Entry Module (MC_ME) Table 7-3. MC_ME Memory Map (continued) 0xC3FD ME_TEST_M _C024 DFLAON CFLAON SYSCLK 0xC3FD ME_SAFE_M _C028 DFLAON CFLAON SYSCLK 0xC3FD ME_DRUN_M _C02C DFLAON CFLAON SYSCLK 0xC3FD ME_RUN0…3 _C030 DFLAON CFLAON … 0xC3FD _C03C SYSCLK MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 138 Chapter 7 Mode Entry Module (MC_ME) Table 7-3. MC_ME Memory Map (continued) 0xC3FD ME_HALT0_ _C040 DFLAON CFLAON SYSCLK 0xC3FD reserved _C044 0xC3FD ME_STOP0_ _C048 DFLAON CFLAON SYSCLK 0xC3FD _C04C … reserved 0xC3FD _C05C 0xC3FD ME_PS0 _C060 MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 139 Chapter 7 Mode Entry Module (MC_ME) Table 7-3. MC_ME Memory Map (continued) 0xC3FD ME_PS1 _C064 0xC3FD ME_PS2 _C068 0xC3FD reserved _C06C 0xC3FD reserved _C070 0xC3FD _C074 … reserved 0xC3FD _C07C 0xC3FD ME_RUN_PC _C080 0…7 … 0xC3FD _C09C 0xC3FD ME_LP_PC0 _C0A0 …7 …...
Page 140 Chapter 7 Mode Entry Module (MC_ME) Table 7-3. MC_ME Memory Map (continued) 0xC3FD ME_PCTL0… LP_CFG RUN_CFG LP_CFG RUN_CFG _C0C0 … 0xC3FD _C14C LP_CFG RUN_CFG LP_CFG RUN_CFG 0xC3FD _C150 … reserved 0xC3FD _FFFC 7.3.2 Register Description Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian.
Page 141 Chapter 7 Mode Entry Module (MC_ME) Table 7-4. Global Status Register (ME_GS) Field Descriptions Field Description S_CURREN Current device mode status T_MODE 0000 RESET 0001 TEST 0010 SAFE 0011 DRUN 0100 RUN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT0 1001 reserved 1010 STOP0 1011 reserved...
Page 142 Chapter 7 Mode Entry Module (MC_ME) Table 7-4. Global Status Register (ME_GS) Field Descriptions (continued) Field Description S_16 16 MHz internal RC oscillator status MHz_IRC 0 16 MHz internal RC oscillator is not stable 1 16 MHz internal RC oscillator is providing a stable clock S_SYSCLK System clock switch status —...
Page 143 Chapter 7 Mode Entry Module (MC_ME) Table 7-5. Mode Control Register (ME_MCTL) Field Descriptions Field Description TARGET_M Target device mode — These bits provide the target device mode to be entered by software programming. The mechanism to enter into any mode by software requires the write operation twice: first time with key, and second time with inverted key.
Page 144 Chapter 7 Mode Entry Module (MC_ME) Table 7-6. Mode Enable Register (ME_ME) Field Descriptions Field Description STOP0 STOP0 mode enable 0 STOP0 mode is disabled 1 STOP0 mode is enabled HALT0 HALT0 mode enable 0 HALT0 mode is disabled 1 HALT0 mode is enabled RUN3 RUN3 mode enable 0 RUN3 mode is disabled...
Page 145 Chapter 7 Mode Entry Module (MC_ME) This register provides the current interrupt status. Table 7-7. Interrupt Status Register (ME_IS) Field Descriptions Field Description I_ICONF Invalid mode configuration interrupt — This bit is set whenever a write operation to ME_<mode>_MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’ to this bit.
Page 146 Chapter 7 Mode Entry Module (MC_ME) Table 7-8. Interrupt Mask Register (ME_IM) Field Descriptions (continued) Field Description M_SAFE SAFE mode interrupt mask 0 SAFE mode interrupt is masked 1 SAFE mode interrupt is enabled M_MTC Mode transition complete interrupt mask 0 Mode transition complete interrupt is masked 1 Mode transition complete interrupt is enabled 7.3.2.6...
Page 147 Chapter 7 Mode Entry Module (MC_ME) Table 7-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions (continued) Field Description S_NMA Non-existing Mode Access status — This bit is set whenever the target mode requested is one of those non existing modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit. 0 Target mode requested is an existing mode 1 Target mode requested is a non-existing mode S_SEA...
Page 148 Chapter 7 Mode Entry Module (MC_ME) Table 7-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions Field Description PREVIOUS_ Previous device mode — These bits show the mode in which the device was prior to the latest MODE change to the current mode. 0000 RESET 0001 TEST 0010 SAFE...
Page 149 Chapter 7 Mode Entry Module (MC_ME) Table 7-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued) Field Description SYSCLK_S System Clock Switching pending status — 0 No system clock source switching is pending 1 A system clock source switching is pending DFLASH_SC DFLASH State Change during mode transition indicator —...
Page 150 Chapter 7 Mode Entry Module (MC_ME) 7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) Address 0xC3FD_C020 Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset Figure 7-9. RESET Mode Configuration Register (ME_RESET_MC) This register configures system behavior during RESET mode. Please refer to Table 7-11 for details.
Page 151 Chapter 7 Mode Entry Module (MC_ME) 7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) Address 0xC3FD_C028 Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset Figure 7-11. SAFE Mode Configuration Register (ME_SAFE_MC) This register configures system behavior during SAFE mode. Please refer to Table 7-11 for details.
Page 152 Chapter 7 Mode Entry Module (MC_ME) … 7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0 3_MC) Address 0xC3FD_C030 - 0xC3FD_C03C Access: User read, Supervisor read/write, Test read/write DFLAON CFLAON Reset SYSCLK Reset Figure 7-13. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) This register configures system behavior during RUN0…3 modes. Please refer to Table 7-11 for details.
Page 153 Chapter 7 Mode Entry Module (MC_ME) NOTE The reset value of the DFLAON field in the ME_HALT0_MC register is “10”. This reset value is illegal for the data flash. Thus, the reset value for the HALT0 mode configuration cannot be used as is and must be set to a legal value before requesting the entry of the HALT0 mode.
Page 154 Chapter 7 Mode Entry Module (MC_ME) Table 7-11. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions (continued) Field Description CFLAON Code flash power-down control — This bit specifies the operating mode of the code flash after entering this mode. 00 reserved 01 Code flash is in power-down mode 10 Code flash is in low-power mode 11 Code flash is in normal mode PLL0ON...
Page 155 Chapter 7 Mode Entry Module (MC_ME) 7.3.2.15 Peripheral Status Register 0 (ME_PS0) Address 0xC3FD_C060 Access: User read, Supervisor read, Test read Reset Reset Figure 7-16. Peripheral Status Register 0 (ME_PS0) This register provides the status of the peripherals. Please refer to Table 7-12 for details.
Page 156 Chapter 7 Mode Entry Module (MC_ME) 7.3.2.17 Peripheral Status Register 2 (ME_PS2) Address 0xC3FD_C068 Access: User read, Supervisor read, Test read Reset Reset Figure 7-18. Peripheral Status Register 2 (ME_PS2) This register provides the status of the peripherals. Please refer to Table 7-12 for details.
Page 157 Chapter 7 Mode Entry Module (MC_ME) Table 7-13. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions Field Description RUN3 Peripheral control during RUN3 0 Peripheral is frozen with clock gated 1 Peripheral is active RUN2 Peripheral control during RUN2 0 Peripheral is frozen with clock gated 1 Peripheral is active RUN1 Peripheral control during RUN1...
Page 158 Chapter 7 Mode Entry Module (MC_ME) Table 7-14. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions Field Description STOP0 Peripheral control during STOP0 0 Peripheral is frozen with clock gated 1 Peripheral is active HALT0 Peripheral control during HALT0 0 Peripheral is frozen with clock gated 1 Peripheral is active …...
Page 159 Chapter 7 Mode Entry Module (MC_ME) Table 7-15. Peripheral Control Registers (ME_PCTL0…143) Field Descriptions (continued) Field Description LP_CFG Peripheral configuration select for non-run modes — These bits associate a configuration as defined in the ME_LP_PC0…7 registers to the peripheral. 000 Selects ME_LP_PC0 configuration 001 Selects ME_LP_PC1 configuration 010 Selects ME_LP_PC2 configuration 011 Selects ME_LP_PC3 configuration...
Page 160 Chapter 7 Mode Entry Module (MC_ME) the status in the ME_GS register matches the configuration programmed in the respective ME_<mode>_MC register. NOTE It is recommended that software poll the S_MTRANS bit in the ME_GS register after requesting a transition to HALT0 or STOP0 modes. recoverable SYSTEM MODES USER MODES...
Page 161 Chapter 7 Mode Entry Module (MC_ME) 7.4.2.2 DRUN Mode The device enters this mode on the following events: • automatically from RESET mode after completion of the reset sequence • from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL register is written with “0011”...
Page 162 Chapter 7 Mode Entry Module (MC_ME) • to assess the severity of the cause of failure and then to either — re-initialize the device via the DRUN mode, or — completely reset the device via the RESET mode. If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the PDO bit of the ME_SAFE_MC register should be set.
Page 163 Chapter 7 Mode Entry Module (MC_ME) 7.4.2.6 HALT0 Mode The device enters this mode on the following events: • from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with “1000”. As soon as any of the above events has occurred, a HALT0 mode transition request is generated. The mode configuration information for this mode is provided by ME_HALT0_MC register.
Page 164 Chapter 7 Mode Entry Module (MC_ME) • to wait until it is required to do something with no need to react quickly (e.g., allow for system clock source to be re-started) This mode can be used to stop all clock sources and thus preserve the device status. When exiting the STOP0 mode, the 16 MHz internal RC oscillator clock is selected as the system clock until the target clock is available.
Page 165 Chapter 7 Mode Entry Module (MC_ME) Table 7-16. MC_ME Resource Control Overview Mode Resource RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0    MHz_IRC      XOSC0     PLL0     ...
Page 166 Chapter 7 Mode Entry Module (MC_ME) Please refer to Section 7.4.6, “Peripheral Clock Gating“ for more details. Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive state when the device enters the SAFE mode. 7.4.3.4 Processor Low-Power Mode Entry If, on completion of the...
Page 167 Chapter 7 Mode Entry Module (MC_ME) 7.4.3.7 Flash Modules Switch-On On completion of the step, if one or more of the flashes needs to be switched to normal mode from its low-power or power-down mode based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME requests the flash to exit from its low-power/power-down mode.
Page 168 Chapter 7 Mode Entry Module (MC_ME) • The target clock configuration for the 4 MHz crystal osc. takes effect only after the S_XOSC0 bit of the ME_GS register is set by hardware (i.e the 4 MHz crystal oscillator has stabilized). •...
Page 169 Chapter 7 Mode Entry Module (MC_ME) 7.4.3.14 Clock Sources (with no Dependencies) Switch-Off Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given clock source is to be switched off and no other clock source needs it to be on, the MC_ME requests the clock source to power down and updates its availability status bit S_<clock source>...
Page 170 Chapter 7 Mode Entry Module (MC_ME) Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. If a mode transition is taking longer to complete than is expected, the ME_DMTS register can indicate which process is still in progress.
Page 171 Chapter 7 Mode Entry Module (MC_ME) Start Write ME_MCTL register Target Mode Request SAFE mode request interrupt/wakeup event Clock Sources Switch-On FLASH Outputs On Switch-On Peripheral Clocks Disable Processor & Memory Clock Enable Processor Low-Power Peripheral Clocks Entry Enable Processor System Clock Low-Power Switching...
Page 172 Chapter 7 Mode Entry Module (MC_ME) 7.4.4 Protection of Mode Configuration Registers While programming the mode configuration registers ME_<mode>_MC, the following rules must be respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be generated. •...
Page 173 Chapter 7 Mode Entry Module (MC_ME) • If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if the target mode requested is other than RESET or SAFE, then this new mode request is considered to be invalid, and the S_SEA bit of the ME_IMTS register is set.
Page 174 Chapter 7 Mode Entry Module (MC_ME) Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’. 7.4.5.3 SAFE Mode Transition Interrupt Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due...
Page 175 Chapter 7 Mode Entry Module (MC_ME) 7.4.7 Application Example Figure 7-24 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed. MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 176 Chapter 7 Mode Entry Module (MC_ME) START of mode change config for target mode okay? write ME_<target mode>_MC, ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTL0…143 registers write ME_MCTL with target mode and key write ME_MCTL with target mode and inverted key start timer S_MTRANS cleared? timer...
Page 177 Chapter 8 Reset Generation Module (MC_RGM) Chapter 8 Reset Generation Module (MC_RGM) Introduction 8.1.1 Overview The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset sequence of the device. It provides a register interface and the reset sequencer. Various registers are available to monitor and control the device reset sequence.
Page 178 Chapter 8 Reset Generation Module (MC_RGM) MC_RGM power-on MC_ME 1.2V low-voltage detected software watchdog timer 2.7V low-voltage detected Registers (VREG) 2.7V low-voltage detected Platform Interface MC_CGM (flash) 2.7V low-voltage detected (I/O) peripherals Reset RESET_B State Machine JTAG initiated reset core core reset software reset checkstop reset...
Page 179 Chapter 8 Reset Generation Module (MC_RGM) • bidirectional reset behavior configuration • boot mode capture on RESET_B deassertion 8.1.3 Reset Sources The different reset sources are organized into two families: ‘destructive’ and ‘functional’. • A ‘destructive’ reset source is associated with an event related to a critical - usually hardware - error or dysfunction.
Page 180 Chapter 8 Reset Generation Module (MC_RGM) Alternatively, it is possible for software to configure some reset source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see Section 8.3.1.3, “Functional Event Reset Disable Register (RGM_FERD) Section 8.3.1.5, “Functional Event Alternate Request Register (RGM_FEAR)
Page 181 Chapter 8 Reset Generation Module (MC_RGM) Table 8-2. MC_RGM Memory Map 0xC3FE RGM_ _4000 FES / RGM_ W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c W w1c w1c w1c w1c 0xC3FE RGM_ _4004 FERD / RGM_ DERD 0xC3FE _4008...
Page 182 Chapter 8 Reset Generation Module (MC_RGM) Table 8-2. MC_RGM Memory Map (continued) 0xC3FE RGM_ _4018 FESS 0xC3FE RGM_ _401C FBRE 0xC3FE _4020 … reserved 0xC3FE _7FFC 8.3.1 Register Descriptions Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian.
Page 183 Chapter 8 Reset Generation Module (MC_RGM) This register contains the status of the last asserted functional reset sources. It can be accessed in read/write on either supervisor mode or test mode. Register bits are cleared on write ‘1’. Table 8-3. Functional Event Status Register (RGM_FES) Field Descriptions Field Description F_EXR...
Page 184 Chapter 8 Reset Generation Module (MC_RGM) 8.3.1.2 Destructive Event Status Register (RGM_DES) Address 0xC3FE_4002 Access: User read, Supervisor read/write, Test read/write W w1c Figure 8-3. Destructive Event Status Register (RGM_DES) This register contains the status of the last asserted destructive reset sources. It can be accessed in read/write on either supervisor mode or test mode.
Page 185 Chapter 8 Reset Generation Module (MC_RGM) NOTE The F_POR flag is automatically cleared on a 1.2 V low-voltage detected or a 2.7 V low-voltage detected. This means that if the power-up sequence is not monotonic (i.e., the voltage rises and then drops enough to trigger a low-voltage detection), the F_POR flag may not be set but instead the F_LVD12 or F_LVD27_VREG flag is set on exiting the reset sequence.
Page 186 Chapter 8 Reset Generation Module (MC_RGM) Table 8-5. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions (continued) Field Description D_CMU0_OLR Disable oscillator frequency lower than reference 0 A oscillator frequency lower than reference event triggers a reset sequence 1 A oscillator frequency lower than reference event generates either a SAFE mode or an interrupt request depending on the value of RGM_FEAR.AR_CMU0_OLR D_PLL0 Disable PLL0 fail...
Page 187 Chapter 8 Reset Generation Module (MC_RGM) Table 8-6. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions Field Description D_LVD27_IO Disable 2.7V low-voltage detected (I/O) 0 A 2.7V low-voltage detected (I/O) event triggers a reset sequence D_LVD27_FLASH Disable 2.7V low-voltage detected (flash) 0 A 2.7V low-voltage detected (flash) event triggers a reset sequence D_LVD27_VREG Disable 2.7V low-voltage detected (VREG) 0 A 2.7V low-voltage detected (VREG) event triggers a reset sequence...
Page 188 Chapter 8 Reset Generation Module (MC_RGM) Table 8-7. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions (continued) Field Description AR_CMU0_OLR Alternate Request for oscillator frequency lower than reference 0 Generate a SAFE mode request on a oscillator frequency lower than reference event if the reset is disabled 1 Generate an interrupt request on a oscillator frequency lower than reference event if the reset is disabled...
Page 189 Chapter 8 Reset Generation Module (MC_RGM) Table 8-8. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions Field Description SS_EXR Short Sequence for External Reset 0 The reset sequence triggered by an external reset event will start from PHASE1 SS_PLL1 Short Sequence for PLL1 fail 0 The reset sequence triggered by a PLL1 fail event will start from PHASE1 1 The reset sequence triggered by a PLL1 fail event will start from PHASE3, skipping PHASE1 and PHASE2...
Page 190 Chapter 8 Reset Generation Module (MC_RGM) 8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE) Address 0xC3FE_401C Access: User read, Supervisor read/write, Test read/write Figure 8-8. Functional Bidirectional Reset Enable Register (RGM_FBRE) This register enables the generation of an external reset on functional reset. It can be accessed in read/write in either supervisor mode or test mode.
Page 191 Chapter 8 Reset Generation Module (MC_RGM) Table 8-9. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions (continued) Field Description BE_CORE Bidirectional Reset Enable for core reset 0 RESET_B is asserted on a core reset event if the reset is enabled 1 RESET_B is not asserted on a core reset event BE_JTAG Bidirectional Reset Enable for JTAG initiated reset...
Page 192 Chapter 8 Reset Generation Module (MC_RGM) power-on or enabled ‘destructive’ reset PHASE0 duration  3 16 MHz internal RC oscillator clock cycles 16 MHz IRC stable, VREG voltage okay done enabled non-shortened external or ‘functional’ PHASE1 reset duration  350 16 MHz internal RC oscillator clock cycles PHASE2 duration 16 MHz internal RC oscillator clock cycles code and data flash initialization done...
Page 193 Chapter 8 Reset Generation Module (MC_RGM) — 16 MHz IRC stable, VREG voltage okay • a minimum of 3 16 MHz internal RC oscillator clock cycles have elapsed since power-up completion and the last enabled ‘destructive’ reset event 8.4.1.2 PHASE1 Phase This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on a non-masked external or ‘functional’...
Page 194 Chapter 8 Reset Generation Module (MC_RGM) 8.4.2 Destructive Resets A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content can no longer be guaranteed. The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_<destructive reset> bit) is set when the ‘destructive’...
Page 195 Chapter 8 Reset Generation Module (MC_RGM) 8.4.4 Functional Resets A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical register and memory content is still intact. The status flag associated with a given ‘functional’ reset event (RGM_FES.F_<functional reset> bit) is set when the ‘functional’...
Page 196 Chapter 8 Reset Generation Module (MC_RGM) NOTE If a masked ‘functional’ reset event which is configured to generate a SAFE mode/interrupt request occurs during PHASE1, it is ignored, and the MC_RGM will not send any safe mode/interrupt request to the MC_ME. 8.4.6 Boot Mode Capturing The MC_RGM provides sampling of the boot mode PAD[4:2] for use by the system.
Page 197 Chapter 9 Interrupt Controller (INTC) Chapter 9 Interrupt Controller (INTC) Introduction The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 128 interrupt requests. It is targeted to work with Power Architecture technology and automotive applications where the ISRs nest to multiple levels, but it also can be used with other processors and applications.For high-priority interrupt requests in these target applications, the time from the assertion of the peripheral’s interrupt request to when the processor is performing useful work to service the interrupt request needs to...
Page 198 Chapter 9 Interrupt Controller (INTC) Table 9-1. Interrupt sources available Interrupt sources (128) Number available Software ECSM eDMA2x SIUL MC_ME MC_RGM XOSC FlexCAN eTimer FlexPWM Safety Port DSPI LINFlex MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 199 Chapter 9 Interrupt Controller (INTC) Block diagram Figure 9-1 shows a block diagram of the interrupt controller (INTC). Software Module Priority Set/Clear Hardware Select Configuration Interrupt Vector Enable Register Registers Registers End of Interrupt Vector Table Highest Lowest Register Entry Size 4-bits Priority Vector...
Page 200 Chapter 9 Interrupt Controller (INTC) mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated. The vector is read from INC_IACKR.
Page 201: Table Of Contents
Chapter 9 Interrupt Controller (INTC) The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to the processor. Memory map and registers description 9.5.1 Module memory map Table 9-2 shows the INTC memory map. Table 9-2.
Page 202: Intc Module Configuration Register (Intc_Mcr)
Chapter 9 Interrupt Controller (INTC) INTC registers are accessible only when the core is in supervisor mode (see Section 15.4.3, “ECSM_reg_protection). 9.5.2.1 INTC Module Configuration Register (INTC_MCR) The module configuration register configures options of the INTC. Address: Base + 0x0000 Access: User read/write Reset VTES...
Page 203 Chapter 9 Interrupt Controller (INTC) 9.5.2.2 INTC Current Priority Register (INTC_CPR) Address: Base + 0x0008 Access: User read/write Reset Reset Figure 9-3. INTC Current Priority Register (INTC_CPR) Table 9-4. INTC_CPR field descriptions Field Description 28–31 Priority PRI[0:3] PRI is the priority of the currently executing ISR according to the following: 1111 Priority 15—highest priority 1110 Priority 14 1101 Priority 13...
Page 204: Intc Interrupt Acknowledge Register(Intc_Iackr)
Chapter 9 Interrupt Controller (INTC) NOTE A store to modify the PRI field that closely precedes or follows an access to a shared resource can result in a non-coherent access to the resource. Refer Section 9.7.5.2, “Ensuring coherency, for example code to ensure coherency.
Page 205: Intc End-Of-Interrupt Register (Intc_Eoir)
Chapter 9 Interrupt Controller (INTC) 9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) Address Base + 0x0018 Access: Write-only Reset Reset Figure 9-5. INTC End-of-Interrupt Register (INTC_EOIR) Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR.
Page 206: Intc Priority Select Registers (Intc_Psr0_3-Intc_Psr220_221)
Chapter 9 Interrupt Controller (INTC) Address Base + 0x0024 Access: User read/write SET4 SET5 Reset SET6 SET7 Reset Figure 9-7. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7]) Table 9-6. INTC_SSCIR[0:7] field descriptions Field Description 6, 14, 22, 30 Set Flag Bits SET[0:7] Writing a ‘1’...
Page 207 Chapter 9 Interrupt Controller (INTC) Address Base + 0x011C Access: User read/write PRI220 PRI221 Reset Reset Figure 9-9. INTC Priority Select Register 220–221 (INTC_PSR[220:221]) Table 9-7. INTC_PSR0_3–INTC_PSR220–221 field descriptions Field Description 4–7, 12–15, Priority Select 20–23, 28–31 PRIx selects the priority for interrupt requests. Refer to Section 9.6, “Functional description.
Page 208 Chapter 9 Interrupt Controller (INTC) Table 9-8. INTC Priority Select Register address offsets (continued) INTC_PSRx_x Offset Address INTC_PSRx_x Offset Address INTC_PSR68_71 0x0084 INTC_PSR180_183 0x00F4 INTC_PSR72_75 0x0088 INTC_PSR184_187 0x00F8 INTC_PSR76_79 0x008C INTC_PSR188_191 0x00FC INTC_PSR80_83 0x0090 INTC_PSR192_195 0x0100 INTC_PSR84_87 0x0094 INTC_PSR196_199 0x0104 INTC_PSR88_91 0x0098 INTC_PSR200_203...
Page 209 Chapter 9 Interrupt Controller (INTC) Functional description The functional description involves the areas of interrupt request sources, priority management, and handshaking with the processor. NOTE The INTC has no spurious vector support. Therefore, if an asserted peripheral or software settable interrupt request, whose PRIn value in INTC_PSR0–INTC_PSR221 is higher than the PRI value in INTC_CPR, negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged, the interrupt request to...
Page 210 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0824 Platform Flash Bank 0 Abort | ECSM Platform Flash Bank 0 Stall | Platform Flash Bank 1 Abort | Platform Flash Bank 1 Stall | Platform Flash Bank 2 Abort | Platform Flash Bank 2 Stall | Platform Flash Bank 3 Abort |...
Page 211 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0888 Reserved ECSM 0x088C ECC_DBD_PlatformFlash | ECSM ECC_DBD_PlatformRAM 0x0890 ECC_SBC_PlatformFlash | ECSM ECC_SBC_PlatformRAM 0x0894 Reserved 0x0898 Reserved 0x089C Reserved 0x08A0 Reserved SIUL 0x08A4 SIU External IRQ_0 SIUL 0x08A8 SIU External IRQ_1...
Page 212 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x08E8 Reserved 0x08EC PITimer Channel 0 0x08F0 PITimer Channel 1 0x08F4 PITimer Channel 2 ADC0 0x08F8 ADC_EOC ADC_0 0x08FC ADC_ER ADC_0 0x0900 ADC_WD ADC_0 FlexCAN0 0x0904 FLEXCAN_ESR[ERR_INT]...
Page 213 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0950 Reserved FlexCAN1 0x0954 FLEXCAN_ESR[ERR_INT] FlexCAN_1 0x0958 FLEXCAN_ESR_BOFF | FlexCAN_1 FLEXCAN_Transmit_Warning | FLEXCAN_Receive_Warning 0x095C FLEXCAN_ESR_WAK FlexCAN_1 0x0960 FLEXCAN_BUF_00_03 FlexCAN_1 0x0964 FLEXCAN_BUF_04_07 FlexCAN_1 0x0968 FLEXCAN_BUF_08_11 FlexCAN_1 0x096C FLEXCAN_BUF_12_15...
Page 214 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x09BC Reserved 0x09C0 Reserved 0x09C4 Reserved DSPI2 0x09C8 DSPI_SR[TFUF] DSPI_2 DSPI_SR[RFOF] 0x09CC DSPI_SR[EOQF] DSPI_2 0x09D0 DSPI_SR[TFFF] DSPI_2 0x09D4 DSPI_SR[TCF] DSPI_2 0x09D8 DSPI_SR[RFDF] DSPI_2 0x09DC Reserved 0x09E0 Reserved...
Page 215 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0A34 Reserved 0x0A38 Reserved 0x0A3C Reserved 0x0A40 Reserved 0x0A44 Reserved 0x0A48 Reserved 0x0A4C Reserved 0x0A50 Reserved 0x0A54 Reserved 0x0A58 Reserved 0x0A5C Reserved 0x0A60 Reserved 0x0A64 Reserved 0x0A68...
Page 216 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0AB0 Reserved 0x0AB4 Reserved 0x0AB8 Reserved 0x0ABC Reserved 0x0AC0 Reserved 0x0AC4 Reserved 0x0AC8 Reserved FlexPWM 0x0ACC FlexPWM_0 0x0AD0 COF0 FlexPWM_0 0x0AD4 Reserved 0x0AD8 FlexPWM_0 0x0ADC COF1 FlexPWM_0...
Page 217 Chapter 9 Interrupt Controller (INTC) Table 9-9. Interrupt vector table (continued) IRQ # Offset Interrupt Module 0x0B28 FIFO1_I CTU_0 0x0B2C FIFO2_I CTU_0 0x0B30 FIFO3_I CTU_0 0x0B34 FIFO4_I CTU_0 0x0B38 ADC_I CTU_0 0x0B3C ERR_I CTU_0 SafetyPort 0x0B40 FLEXCAN_ESR[ERR_INT] SafetyPort (FlexCAN) 0x0B44 FLEXCAN_ESR_BOFF | SafetyPort (FlexCAN) FLEXCAN_Transmit_Warning |...
Page 218 Chapter 9 Interrupt Controller (INTC) 9.6.1.2 Software configurable interrupt requests An interrupt request is triggered by software by writing a ‘1’ to a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the interrupt request. The interrupt request is cleared by writing a ‘1’ to the CLRx bit. The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the processor is four clocks.
Page 219 Chapter 9 Interrupt Controller (INTC) 9.6.2.1.3 Vector encoder subblock The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the request selector subblock for the associated processor. 9.6.2.1.4 Priority comparator subblock The priority comparator submodule compares the highest priority output from the priority arbitrator submodule with PRI in INTC_CPR.
Page 220 Chapter 9 Interrupt Controller (INTC) updated with the preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC field retains that value until the next time the interrupt request to the processor is asserted. The rest of handshaking process is described in Section 9.4.1.1, “Software vector mode.
Page 221 Chapter 9 Interrupt Controller (INTC) 9.6.3.2 Hardware vector mode handshaking A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in Figure 9-11.
Page 222 Chapter 9 Interrupt Controller (INTC) are negated. An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is: interrupt_request_initialization: interrupt_request_initialization: configure VTES and HVEN in INTC_MCR configure VTBA in INTC_IACKR raise the PRIn fields in INTC_PSRn set the enable bits or clear the mask bits for the peripheral interrupt requests lower PRI in INTC_CPR to zero...
Page 223 Chapter 9 Interrupt Controller (INTC) ISRx: code to service the interrupt event code to clear flag bit that drives interrupt request to INTC blr # return to epilog 9.7.2.2 Hardware vector mode This interrupt exception handler is useful with processor and system bus implementations that support a hardware vector.
Page 224 Chapter 9 Interrupt Controller (INTC) the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0. If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.
Page 225 Chapter 9 Interrupt Controller (INTC) Table 9-10. Order of ISR execution example (continued) Code Executing at End of Step PRI in Step INTC_CPR Step Description Interrupt ISR108 ISR20 ISR30 ISR40 at End of RTOS Exception Step Handler ISR208 completes. Interrupt exception handler writes to INTC_EOIR.
Page 226 Chapter 9 Interrupt Controller (INTC) and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt request to the processor because the peripheral interrupt request for ISR2 has asserted.
Page 227 Chapter 9 Interrupt Controller (INTC) acknowledge. The ISR, however, can have a portion that does not need to be executed at this higher priority. Therefore, executing the later portion that does not need to be executed at this higher priority can prevent the execution of ISRs that do not have a higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion of the ISR needs.
Page 228 Chapter 9 Interrupt Controller (INTC) 9.7.9 Negating an interrupt request outside of its ISR 9.7.9.1 Negating an interrupt request as a side effect of an ISR Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request.
Page 229 Chapter 10 System Status and Configuration Module (SSCM) Chapter 10 System Status and Configuration Module (SSCM) 10.1 Introduction 10.1.1 Overview The System Status and Configuration Module (SSCM), pictured in Figure 10-1, provides central device functionality. System Status and Configuration Module RevID Hardmacro Core...
Page 230 Chapter 10 System Status and Configuration Module (SSCM) • Bus and peripheral abort enable/disable 10.1.3 Modes of operation The SSCM operates identically in all system modes. 10.2 Memory map and register description This section provides a detailed description of all memory-mapped registers in the SSCM. 10.2.1 Memory map Table 10-1...
Page 231 Chapter 10 System Status and Configuration Module (SSCM) Always Always Read- Write- Write 1 Self- reads 1 reads 0 only bit only bit to clear clear Figure 10-2. Key to register fields 10.2.2.1 System Status register (STATUS) The system status register is a read-only register that reflects the current state of the system. Address: Base + 0x0000 Access: Read-only PUB SEC...
Page 232 Chapter 10 System Status and Configuration Module (SSCM) Table 10-3. STATUS field descriptions (continued) Field Description Autobaud Indicates that autobaud detection is active when in SCI or CAN serial boot loader mode. No meaning in other modes. 10.2.2.2 System Memory Configuration register (MEMCONFIG) The system memory configuration register is a read-only register that reflects the memory configuration of the system.
Page 233 Chapter 10 System Status and Configuration Module (SSCM) 10.2.2.3 Error Configuration (ERROR) register The Error Configuration register is a read-write register that controls the error handling of the system. Address: Base + 0x0006 Access: User read/write PAE RAE Reset Figure 10-5. Error Configuration (ERROR) register Table 10-6.
Page 234 Chapter 10 System Status and Configuration Module (SSCM) Address: Base + 0x0008 Access: User read/write DEBUG_MODE [2:0] Reset Figure 10-6. Debug Status Port (DEBUGPORT) register Table 10-8. DEBUGPORT field descriptions Field Description 13-15 Debug Status Port Mode DEBUG_MODE[2:0] This field selects the alternate debug functionality for the Debug Status Port. 000: No alternate functionality selected 001: Mode 1 selected 010: Mode 2 selected...
Page 235 Chapter 10 System Status and Configuration Module (SSCM) Table 10-10. DEBUGPORT allowed register accesses Access width Access type 8-bit 16-bit 32-bit Read Allowed Allowed Not allowed Write Allowed Allowed Not allowed All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). MPC5602P Microcontroller Reference Manual, Rev.
Page 236 Chapter 10 System Status and Configuration Module (SSCM) 10.2.2.5 Password comparison registers These registers allow to unsecure the device, if the correct password is known. Address: Base + 0x000C Access: User read/write PWD_HI[31:16] Reset PWD_HI[15:0] Reset Figure 10-7. Password Comparison Register High Word (PWCMPH) register Address: Base + 0x0010 Access: User read/write PWD_LO[31:16]...
Page 237 Chapter 10 System Status and Configuration Module (SSCM) 10.3 Functional description The primary purpose of the SSCM is to provide information about the current state and configuration of the system that may be useful for configuring application software and for debug of the system. 10.4 Initialization/application information 10.4.1...
Page 238 Chapter 10 System Status and Configuration Module (SSCM) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 239 Chapter 11 System Integration Unit Lite (SIUL) Chapter 11 System Integration Unit Lite (SIUL) 11.1 Introduction This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the pads and their configuration. It controls the multiplexing of the alternate functions used on all pads and is responsible for managing the external interrupts to the device.
Page 240 Chapter 11 System Integration Unit Lite (SIUL) SIUL Module Pad Configuration (IOMUXC) Pad Config (PCRs) GPIO Functionality Data Pads Pad Input Master Interrupt Functionality Interrupt Controller Interrupt – Configuration – Glitch Filter Figure 11-1. System Integration Unit Lite block diagram 11.3 Features The System Integration Unit Lite provides these features:...
Page 241 Chapter 11 System Integration Unit Lite (SIUL) • System configuration — Pad configuration control 11.3.1 Register protection Most of the configuration registers of the System Integration Unit Lite are protected from accidental writes, see Appendix A, “Registers Under Protection. 11.4 External signal description The pad configuration allows flexible, centralized control of the pin electrical characteristics of the MCU with the GPIO control providing centralized general purpose I/O for an MCU that multiplexes GPIO with...
Page 242 Chapter 11 System Integration Unit Lite (SIUL) Rising-Edge Event Enable Register (IREER) Section 11.5.2.6, “Interrupt Falling-Edge Event Enable Register (IFEER). 11.5 Memory map and register description This section provides a detailed description of all registers accessible in the SIUL module. 11.5.1 SIUL memory map Table 11-2...
Page 243 Chapter 11 System Integration Unit Lite (SIUL) Table 11-2. SIUL memory map (continued) Offset from SIUL_BASE Register Location (0xC3F9_0000) 0x0C9C–0x0FFF Reserved 0x1000–0x1060 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24]) on page 257 0x1064–0x107C Reserved 0x1080 Interrupt Filter Clock Prescaler Register (IFCPR) on page 257 0x1084–0x3FFF Reserved NOTE...
Page 244 Chapter 11 System Integration Unit Lite (SIUL) Table 11-3. MIDR1 field descriptions Field Description PARTNUM[15:0] MCU Part Number Device part number of the MCU. 0101_0110_0000_0001: 192 KB 0101_0110_0000_0010: 256 KB 0101_0110_0000_0011:384 KB For the full part number this field needs to be combined with MIDR2.PARTNUM[23:16] Always reads back 0 PKG[4:0] Package Settings...
Page 245 Chapter 11 System Integration Unit Lite (SIUL) 11.5.2.2 MCU ID Register #2 (MIDR2) This register contains additional configuration information about the device. Address: Base + 0x0008 Access: User read-only FLASH_SIZE_1[3:0] FLASH_SIZE_2[3:0] Reset PARTNUM[23:16] Reset Figure 11-4. MCU ID Register #2 (MIDR2) The reset value of this bit depends on the device sales type.
Page 246 Chapter 11 System Integration Unit Lite (SIUL) 11.5.2.3 Interrupt Status Flag Register (ISR) This register holds the interrupt flags. Address: Base + 0x0014 Access: User read/write EIF[24:16] Reset EIF[15:0] Reset Figure 11-5. Interrupt Status Flag Register (ISR) Table 11-5. ISR field descriptions Field Description EIFn...
Page 247 Chapter 11 System Integration Unit Lite (SIUL) 11.5.2.5 Interrupt Rising-Edge Event Enable Register (IREER) This register allows rising-edge triggered events to be enabled on the corresponding interrupt pads. Address: Base + 0x0028 Access: User read/write IREE[24:16] Reset IREE[15:0] Reset Figure 11-7. Interrupt Rising-Edge Event Enable Register (IREER) Table 11-7.
Page 248 Chapter 11 System Integration Unit Lite (SIUL) NOTE If both the IREER.IREE and IFEER.IFEE bits are cleared for the same interrupt source, the interrupt status flag for the corresponding external interrupt will never be set. 11.5.2.7 Interrupt Filter Enable Register (IFER) This register enables a digital filter counter on the corresponding interrupt pads to filter out glitches on the inputs.
Page 249 Chapter 11 System Integration Unit Lite (SIUL) Table 11-10. PCR[0:71] field descriptions Field Description Safe Mode Control This bit supports the overriding of the automatic deactivation of the output buffer of the associated pad upon entering Safe mode of the device. 0: In Safe mode, output buffer of the pad disabled 1: In Safe mode, output buffer remains functional Analog Pad Control...
Page 250 Chapter 11 System Integration Unit Lite (SIUL) Table 11-11. PCR[n] reset value exceptions Field Description PCR[2] These registers correspond to the ABS[0], ABS[1], and FAB boot pins, respectively. Their default PCR[3] state is input, pull enabled. Their reset value is 0x0102. PCR[4] PCR[20] This register corresponds to the TDO pin.
Page 251 Chapter 11 System Integration Unit Lite (SIUL) Address: Base + 0x0500 (PSMI0_3) Base + 0x0514 (PSMI20_23) Access: User read/write Base + 0x0504 (PSMI4_7) Base + 0x0518 (PSMI024_27) Base + 0x0508 (PSMI8_11) Base + 0x051C (PSMI28_31) Base + 0x050C (PSMI12_15) Base + 0x0520 (PSMI32_35) Base + 0x0510 (PSMI16_19) PADSEL0[3:0] PADSEL1[3:0]...
Page 252 Chapter 11 System Integration Unit Lite (SIUL) Table 11-14. Pad selection (continued) LQFP pin PADSEL[3:0] Register PADSEL Module Port Port name value 64-pin 100-pin PSMI8_11 PADSEL0 eTimer0 ETC[5] 0000 C[12] 0001 B[8] PADSEL1 — — — — — — PADSEL2 —...
Page 253 Chapter 11 System Integration Unit Lite (SIUL) Values not listed are reserved. Writing to PADSELx[3:1] has no effect—a write to these three bits will return ‘0’. Writing to PADSELx[3:2] has no effect—a write to these two bits will return ‘0’. MPC5602P Microcontroller Reference Manual, Rev.
Page 254 Chapter 11 System Integration Unit Lite (SIUL) 11.5.2.10 GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71]) These registers can be used to set or clear a single GPIO pad with a byte access. Address: Base + 0x0600 (GPDO0_3) Access: User read/write Base + 0x0644 (GPDO68_71) 18 registers Reset Reset...
Page 255 Chapter 11 System Integration Unit Lite (SIUL) Table 11-16. GPDI[0_3:68_71] field descriptions Field Description PDI[x] Pad Data In This bit stores the value of the external GPIO pad associated with this register. 0: The value of the data in signal for the corresponding GPIO pad is logic low. 1: The value of the data in signal for the corresponding GPIO pad is logic high.
Page 256 Chapter 11 System Integration Unit Lite (SIUL) Address: Base + 0x0C40 (PGPDI0) Base + 0x0C45 (PGPDI2) Access: User read-only Base + 0x0C44 (PGPDI1) Base + 0x0C4C (PGPDI3) PPDI[x][15:0] Reset PPDI[x + 1][15:0] Reset Figure 11-15. Parallel GPIO Pad Data In register 0–3 (PGPDI[0:3]) Table 11-18.
Page 257 Chapter 11 System Integration Unit Lite (SIUL) Table 11-19. MPGPDO[0:6] field descriptions Field Description MASK[x] Mask Field [15:0] Each bit corresponds to one data bit in the MPPDO[x] field at the same bit location. 0: The associated bit value in the MPPDO[x] field is ignored. 1: The associated bit value in the MPPDO[x] field is written.
Page 258 Chapter 11 System Integration Unit Lite (SIUL) Address: Base + 0x1080 Access: User read/write Reset IFCP[3:0] Reset Figure 11-18. Interrupt Filter Clock Prescaler Register (IFCPR) Table 11-21. IFCPR field descriptions Field Description IFCP Interrupt Filter Clock Prescaler setting [3:0] Prescaled Filter Clock Period = T ×...
Page 259 Chapter 11 System Integration Unit Lite (SIUL) 11.6 Functional description 11.6.1 General This section provides a functional description of the System Integration Unit Lite. 11.6.2 Pad control The SIUL controls the configuration and electrical characteristic of the device pads. It provides a consistent interface for all pads, both on a by-port and a by-bit basis.
Page 260 Chapter 11 System Integration Unit Lite (SIUL) The SIUL has separate data input (GPDIn_n, see Section 11.5.2.11, “GPIO Pad Data Input registers 0_3–68_71 (GPDI[0_3:68_71])) and data output (GPDOn_n, see Section 11.5.2.10, “GPIO Pad Data Output registers 0_3–68_71 (GPDO[0_3:68_71])) registers for all pads, allowing the possibility of reading back an input or output value of a pad directly.
Page 261 Chapter 11 System Integration Unit Lite (SIUL) 11.6.4.1 External interrupt management Each interrupt can be enabled or disabled independently. This can be performed using the IRER (see Section 11.5.2.4, “Interrupt Request Enable Register (IRER)). A pad defined as an external interrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges being active.
Page 262 Chapter 11 System Integration Unit Lite (SIUL) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 263 Chapter 12 e200z0 and e200z0h Core Chapter 12 e200z0 and e200z0h Core 12.1 Overview The MPC5602P microcontroller implements the e200z0h core. The e200 processor family is a set of CPU cores built on the Power Architecture technology. e200 processors are designed for deeply embedded control applications that require low cost solutions rather than maximum performance.
Page 264 Chapter 12 e200z0 and e200z0h Core — Low power design — Dynamic power management of execution units • Testability — Synthesizeable, full MuxD scan design — ABIST/MBIST for optional memory arrays 12.2.1 Microarchitecture summary The e200z0 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
Page 265 Chapter 12 e200z0 and e200z0h Core OnCE/NEXUS CONTROL LOGIC CONTROL LOGIC INTEGER EXECUTION UNIT MULTIPLY INSTRUCTION UNIT UNIT INSTRUCTION BUFFER CONTROL EXTERNAL DATA INTERFACE (MTSPR/MFSPR) BRANCH UNIT UNIT LOAD/STORE UNIT Figure 12-1. e200z0 block diagram MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 266 Chapter 12 e200z0 and e200z0h Core OnCE/NEXUS CONTROL LOGIC CONTROL LOGIC NEXUS DEBUG INTEGER EXECUTION UNIT UNIT MULTIPLY INSTRUCTION UNIT UNIT INSTRUCTION BUFFER CONTROL EXTERNAL DATA INTERFACE (MTSPR/MFSPR) BRANCH UNIT UNIT LOAD/STORE UNIT DATA BUS INTERFACE UNIT ADDRESS DATA CONTROL Figure 12-2.
Page 267 Chapter 12 e200z0 and e200z0h Core • Instruction buffer with 2 entries in e200z0, each holding a single 32-bit instruction, or a pair of 16-bit instructions • Dedicated PC incrementer supporting instruction prefetches • Branch unit with dedicated branch address adder supporting single cycle of execution of certain branches, two cycles for all others 12.2.1.3 Integer unit features...
Page 268 Chapter 12 e200z0 and e200z0h Core • Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced. •...
Page 269 Chapter 12 e200z0 and e200z0h Core Exception Handling/Control Registers General Registers SPR General Save and Restore Interrupt Vector Prefix Condition Register General-Purpose IVPR SPR 63 SPRG0 SPR 272 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 GPR0 Count Register CSRR0 SPR 58 GPR1...
Page 270 Chapter 12 e200z0 and e200z0h Core Exception Handling/Control Registers General Registers SPR General Save and Restore Interrupt Vector Prefix Condition Register General-Purpose IVPR SPR 63 SPRG0 SPR 272 SRR0 SPR 26 Registers SPRG1 SPR 273 SRR1 SPR 27 GPR0 Count Register CSRR0 SPR 58 GPR1...
Page 271 Chapter 12 e200z0 and e200z0h Core USER Mode Programmer Model General Registers General-Purpose Condition Register Registers Cache Registers GPR0 Count Register Cache Configuration GPR1 (Read-only) SPR 9 Link Register L1CFG0 SPR 515 SPR 8 GPR31 SPR 1 Figure 12-5. e200 User mode program model 12.3.1 Unimplemented SPRs and read-only SPRs e200 fully decodes the SPR field of the...
Page 272 Chapter 12 e200z0 and e200z0h Core MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 273 Chapter 13 Peripheral Bridge (PBRIDGE) Chapter 13 Peripheral Bridge (PBRIDGE) 13.1 Introduction The Peripheral Bridge (PBRIDGE) is the interface between the system bus and on-chip peripherals. The Peripheral Bridge of MPC5602P is the same as the one of all other PPC55xx and PPC56xx products except that it cannot be configured by software and that it has a hard-wired configuration.
Page 274 Chapter 13 Peripheral Bridge (PBRIDGE) 13.1.3 Modes of operation The PBRIDGE has only one operating mode. 13.2 Functional description The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module selects for peripheral devices on the slave bus interface.
Page 275 Chapter 14 Crossbar Switch (XBAR) Chapter 14 Crossbar Switch (XBAR) 14.1 Introduction This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections between three master ports and three slave ports. XBAR supports a 32-bit address bus width and a 32-bit data bus width at all master and slave ports.
Page 276 Chapter 14 Crossbar Switch (XBAR) Table 14-1. Device XBAR switch ports (continued) Port Module Physical master ID Logical Type number Internal SRAM Controller Slave — Peripheral bridge Slave — 14.3 Overview The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests.
Page 277 Chapter 14 Crossbar Switch (XBAR) 14.6 Functional description This section describes the functionality of the XBAR in more detail. 14.6.1 Overview The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum.
Page 278 Chapter 14 Crossbar Switch (XBAR) 14.6.3 Master ports A master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. In this case, the XBAR is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred.
Page 279 Chapter 14 Crossbar Switch (XBAR) 14.6.6.1 Fixed priority operation When operating in fixed-priority arbitration mode, each master is assigned a unique priority level in the XBAR_MPR. If two masters both request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port.
Page 280 Chapter 14 Crossbar Switch (XBAR) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 281 Chapter 15 Error Correction Status Module (ECSM) Chapter 15 Error Correction Status Module (ECSM) 15.1 Introduction The Error Correction Status Module (ECSM) provides control functions for the device Standard Product Platform (SPP) including program-visible information about the platform configuration and revision levels, a reset status register, a software watchdog timer, and wakeup control for exiting sleep modes, and optional features such as an address map for the device’s crossbar switch, information on memory errors reported by error-correcting codes and/or generic access error information for certain processor cores.
Page 282 Chapter 15 Error Correction Status Module (ECSM) ECSM registers are accessible only when the core is in supervisor mode (see Section 15.4.3, “ECSM_reg_protection). 15.4.1 Memory map Table 15-1 lists the registers in the ECSM. Table 15-1. ECSM registers Offset from ECSM_BASE Register Location...
Page 283 Chapter 15 Error Correction Status Module (ECSM) Table 15-1. ECSM registers (continued) Offset from ECSM_BASE Register Location Size (bits) 0xFFF4_0000 0x0066 REMR—RAM ECC Master register on page 298 0x0067 REAT—RAM ECC Attributes register on page 298 0x0068–0x006B Reserved 0x006C REDR—RAM ECC Data register on page 299 0x0070–0x3FFF Reserved...
Page 284 Chapter 15 Error Correction Status Module (ECSM) Address: Base + 0x0002 Access: User read-only REV[15:0] Reset Figure 15-2. Revision (REV) register Table 15-3. REV field descriptions Name Description 0-15 Revision REV[15:0] The REV[15:0] field is specified by an input signal to define a software-visible revision number. 15.4.2.3 Platform XBAR Master Configuration (PLAMC) The PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to...
Page 285 Chapter 15 Error Correction Status Module (ECSM) Table 15-5. ASC field descriptions Field Description DP64 64-bit Datapath 0 Datapath width is 32 bits. 1 Datapath width is 64 bits. ASC[7:0] XBAR Slave Configuration 0 Bus slave connection to XBAR output port n is not present. 1 Bus slave connection to XBAR output port n is present.
Page 286 Chapter 15 Error Correction Status Module (ECSM) Table 15-7. MRSR field descriptions Field Description Power-On Reset 0 Last recorded event was not caused by a power-on reset (based on a device input signal). 1 Last recorded event was caused by a power-on reset (based on a device input signal). Device Input Reset 0 Last recorded event was not caused by a device input reset.
Page 287 Chapter 15 Error Correction Status Module (ECSM) 15.4.2.8 Miscellaneous User-Defined Control Register (MUDCR) The MUDCR provides a program-visible register for user-defined control functions. It provides configuration control for assorted modules on the device. The contents of this register is output from the ECSM to other modules where these user-defined control functions are implemented.
Page 288 Chapter 15 Error Correction Status Module (ECSM) The details on the ECC registers are provided in the subsequent sections. If the design does not include ECC on the memories, these addresses are reserved locations within the ECSM’s programming model. 15.4.2.10 ECC Configuration Register (ECR) The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors are reported.
Page 289 Chapter 15 Error Correction Status Module (ECSM) Table 15-10. ECR field descriptions (continued) Field Description Enable Flash Non-Correctable Reporting EFNCR The occurrence of a non-correctable multi-bit flash error generates a ECSM ECC interrupt request as signaled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers.
Page 290 Chapter 15 Error Correction Status Module (ECSM) Address: Base + 0x0047 Access: User read/write R1BC F1BC RNCE FNCE Reset Figure 15-10. ECC Status register (ESR) Table 15-11. ESR field descriptions Field Description RAM 1-bit Correction R1BC This bit can only be set if ECR[ER1BR] is asserted. The occurrence of a properly enabled single-bit RAM correction generates a ECSM ECC interrupt request.
Page 291 Chapter 15 Error Correction Status Module (ECSM) It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported for the same two reasons previously identified.
Page 292 Chapter 15 Error Correction Status Module (ECSM) Table 15-12. EEGR field descriptions (continued) Field Description Force RAM Continuous Non-Correctable Data Inversions FRCNCI 0 No RAM continuous 2-bit data inversions generated 1 2-bit data inversions in the RAM continuously generated The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.
Page 293 Chapter 15 Error Correction Status Module (ECSM) This register can only be read from the IPS programming model; any attempted write is ignored. Address Base + 0x0050 Access: User read-only FEAR[31:16] Reset — — — — — — — — —...
Page 294 Chapter 15 Error Correction Status Module (ECSM) in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
Page 295 Chapter 15 Error Correction Status Module (ECSM) Address: Base + 0x005C Access: User read-only FEDR[31:16] Reset: — — — — — — — — — — — — — — — — FEDR[15:0] Reset: — — — — — — —...
Page 296 Chapter 15 Error Correction Status Module (ECSM) 15.4.2.18 RAM ECC Syndrome Register (RESR) The RESR is an 8-bit register for capturing the error syndrome of the last properly enabled ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.
Page 297 Chapter 15 Error Correction Status Module (ECSM) Table 15-19. RAM syndrome mapping for single-bit correctable errors (continued) RESR[7:0] Data Bit in Error 0x12 DATA ODD BANK[27] 0x14 DATA ODD BANK[26] 0x16 DATA ODD BANK[25] 0x18 DATA ODD BANK[24] 0x1A DATA ODD BANK[23] 0x1C DATA ODD BANK[22] 0x50...
Page 298 Chapter 15 Error Correction Status Module (ECSM) 15.4.2.19 RAM ECC Master Number Register (REMR) The REMR is an 8-bit register in which the 4-bit field REMR[0:3] is used for capturing the XBAR bus master number of the last properly enabled ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register to be asserted.
Page 299 Chapter 15 Error Correction Status Module (ECSM) Table 15-21. REAT field descriptions Name Description AMBA-AHB HSIZE[2:0] SIZE[2:0] 8-bit AMBA-AHB access 16-bit AMBA-AHB access 32-bit AMBA-AHB access Reserved AMBA-AHB HPROT[3] PROTECTION[3] Protection[0]: Type 0 I-Fetch 1 Data AMBA-AHB HPROT[2] PROTECTION[2] Protection[1]: Mode 0 User mode 1 Supervisor mode AMBA-AHB HPROT[1]...
Page 300 Chapter 15 Error Correction Status Module (ECSM) Table 15-22. REDR field descriptions Name Description 0-31 RAM ECC Data Register REDR[31:0] This 32-bit register contains the data associated with the faulting access of the last properly enabled RAM ECC event. The register contains the data value taken directly from the data bus. ECSM_reg_protection 15.4.3 The ECSM_reg_protection logic provides hardware enforcement of supervisor mode access protection for...
Page 301 Chapter 15 Error Correction Status Module (ECSM) writes, etc. Attempted writes of a different size than the register width produce an error termination of the bus cycle and no change to the targeted register. MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 302 Chapter 15 Error Correction Status Module (ECSM) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 303 Chapter 16 Internal Static RAM (SRAM) Chapter 16 Internal Static RAM (SRAM) 16.1 Introduction The general-purpose SRAM has a size of 20 KB. The SRAM provides the following features: • SRAM can be read/written from any bus master • Byte, halfword, word and doubleword addressable •...
Page 304 Chapter 16 Internal Static RAM (SRAM) Internal SRAM write operations are performed on the following byte boundaries: • 1 byte (0:7 bits) • 2 bytes (0:15 bits) • 4 bytes or 1 word (0:31 bits) If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated across the 32-bit data bus.
Page 305 Chapter 16 Internal Static RAM (SRAM) Table 16-3. Number of wait states required for SRAM operations (continued) Operation type Current operation Previous operation Number of wait states required Write 8 or 16-bit write Idle Read Pipelined 8- or 16-bit write 32-bit write 8 or 16-bit write (write to the same address)
Page 306 Chapter 16 Internal Static RAM (SRAM) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 307 Chapter 17 Flash Memory Chapter 17 Flash Memory 17.1 Introduction The Flash memory comprises a platform Flash controller interface and two Flash memory arrays: one array of 256 KB for code (code Flash) and one array of 64 KB for data (data Flash). The Flash architecture of the MPC5602P device is illustrated in Figure 17-1.
Page 308 Chapter 17 Flash Memory required and always attached to bank0. Additionally, there is a data Flash attached to bank1. The platform Flash controller interface supports two separate connections, one to each memory bank. On the MPC5602P device, bank0 and bank1 are internal to the device. •...
Page 309 Chapter 17 Flash Memory • Programmable response for read-while-write sequences including support for stall-while-write, optional stall notification interrupt, optional Flash operation termination, and optional termination notification interrupt • Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies •...
Page 310 Chapter 17 Flash Memory 17.2.4.1 Memory map First, consider the Flash memory space accessed via transactions from the platform Flash controller’s AHB port. To support the two separate Flash memory banks, the platform Flash controller uses address bit 23 (haddr[23]) to steer the access to the appropriate memory bank. In addition to the actual Flash memory regions, there are shadow and test sectors included in the system memory map.
Page 311 Chapter 17 Flash Memory Next, consider the memory map associated with the control and configuration registers. There are multiple registers that control operation of the platform Flash controller. Note the first two Flash array registers (PFCR0, PFCR1) are reset to a device-defined value, while the remaining register (PFAPR) is loaded at reset from specific locations in the array’s shadow region.
Page 312 Chapter 17 Flash Memory Throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and bk1_. Also, the nomenclature Bx_Py_RegName is used to reference a program-visible register field associated with bank “x” and port “y”. 17.2.6 Basic interface protocol The platform Flash controller interfaces to the Flash array by driving addresses (bkn_fl_addr[23:0]) and...
Page 313 Chapter 17 Flash Memory buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1, the data is captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus. Timing diagrams of basic read accesses from the Flash array are shown in Figure 17-2 through...
Page 314 Chapter 17 Flash Memory A fourth case involves an attempted read access while the Flash array is busy doing a write (program) or erase operation if the appropriate read-while-write control field is programmed for this response. The 3-bit read-while-write control allows for immediate termination of an attempted read, or various stall-while-write/erase operations are occurring.
Page 315 Chapter 17 Flash Memory For the general case, a page buffer is written at the completion of an error-free Flash access and the valid bit asserted. Subsequent Flash accesses that “hit” the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 AHB wait states as the stored read data is routed from the given page buffer back to the requesting bus master.
Page 316 Chapter 17 Flash Memory In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Refer to Section 17.3.6, “Registers description for a description of these control fields.
Page 317 Chapter 17 Flash Memory Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on haddr[28:24] to support wait state emulation. 17.2.15 Bank1 temporary holding register Recall the bank1 logic within the Flash includes a single 128-bit data register, used for capturing read data. Since this bank does not support prefetching, the read data for the referenced address is bypassed directly back to the AHB data bus.
Page 318 Chapter 17 Flash Memory Specifically, there are two 3-bit read-while-write (BKn_RWWC) control register fields that define the platform Flash controller’s response to these types of access sequences. There are five unique responses that are defined by the BKn_RWWC setting: one immediately reports an error on an attempted read, and four settings that support various stall-while-write capabilities.
Page 319 Chapter 17 Flash Memory Table 17-3. Platform Flash controller stall-while-write interrupts MIR[n] Interrupt description ECSM.MIR[7] Platform Flash bank0 termination notification, MIR[FB0AI] ECSM.MIR[6] Platform Flash bank0 stall notification, MIR[FB0SI] ECSM.MIR[5] Platform Flash bank1 termination notification, MIR[FB1AI] ECSM.MIR[4] Platform Flash bank1 stall notification, MIR[FB1S1] For example timing diagrams of the stall-while-write and terminate-while-write operations, see Figure 17-6 Figure 17-7...
Page 320 Chapter 17 Flash Memory Table 17-5 shows the relationship of haddr[25:24] to the number of additional wait states. These are applied in addition to those specified by haddr[28:26] and thus extend the total wait state specification capability. Table 17-5. Extended additional wait state encoding Additional wait states Memory address (added to those specified by...
Page 321 Chapter 17 Flash Memory Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0 hclk nonseq htrans addr y addr y+4 addr y+8 addr y+12 haddr, hprot hwrite C(y) C(y+4) C(y+8) C(y+12) hrdata hwdata hready_out okay okay okay okay...
Page 322 Chapter 17 Flash Memory Burst Read, buffer miss, no prefetch, APC=2, RWSC=2, PFLM=0 hclk nonseq htrans addr y addr y addr y+8 addr y+4 addr y+12 haddr,hprot hwrite C(y) C(y+4) hrdata hwdata hready_out okay okay okay okay okay okay okay okay hresp bkn_fl_addr...
Page 323 Chapter 17 Flash Memory Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0 hclk htrans nonseq addr y haddr,hprot addr y+4 addr y+8 addr y+12 hwrite C(y) C(y+4) C(y+8) C(y+12) hrdata hwdata hready_out okay okay okay okay...
Page 324 Chapter 17 Flash Memory Burst Read, buffer miss, prefetch, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y+20 addr y addr y+8 addr y+16 addr y+4 addr y+12 haddr, hprot hwrite C(y+12) C(y+16) C(y) C(y+4) C(y+8) hrdata hwdata...
Page 325 Chapter 17 Flash Memory Burst Read, Stall-and-Retry, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y+4 addr y+8 addr y haddr, hprot hwrite C(y) C(y+4) hrdata hwdata hready_out okay okay hresp okay okay okay okay okay okay okay...
Page 326 Chapter 17 Flash Memory Burst Read, Abort-and-Retry, APC = 2, RWSC = 2, PFLM = 2 hclk nonseq htrans addr y addr y+8 addr y+4 haddr, hprot hwrite C(y+4) C(y) hrdata hwdata hready_out hresp okay okay okay okay okay okay okay okay okay...
Page 327 Chapter 17 Flash Memory 17.3 Flash memory 17.3.1 Introduction The Flash module provides electrically programmable and erasable non-volatile memory (NVM), which may be used for instruction and/or data storage. The Flash module is arranged as two functional units: the Flash core and the memory interface. The Flash core is composed of arrayed non-volatile storage elements, sense amplifiers, row decoders, column decoders and charge pumps.
Page 328 Chapter 17 Flash Memory The high voltages needed for Program/Erase operations are internally generated. Figure 17-8 shows the data Flash module structure. HV generator Flash Program/Erase Flash Bank 1 Controller 64 KB + 8 KB TestFlash Data Flash Registers Registers Matrix Interface Interface...
Page 329 Chapter 17 Flash Memory HV generator Flash Program/Erase Flash Bank 0 Controller 256 KB + 16 KB TestFlash Code Flash + 16 KB Shadow Registers Matrix Registers Interface Interface Figure 17-9. Code Flash module structure 17.3.4 Functional description 17.3.4.1 Macrocell structure The Flash macrocell provides high density non-volatile memories with high-speed read access.
Page 330 Chapter 17 Flash Memory The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed and erased with sufficient margin to guarantee data integrity and reliability. A programmed bit in the Flash module reads as logic level 0 (or low). An erased bit in the Flash module reads as logic level 1 (or high).
Page 331 Chapter 17 Flash Memory Table 17-7. 64 KB data Flash module sectorization Bank Sector Addresses Size (KB) Address space B1F0 0x0080_0000 to 0x0080_3FFF Low Address Space B1F1 0x0080_4000 to 0x0080_7FFF Low Address Space B1F2 0x0080_8000 to 0x0080_BFFF Low Address Space B1F3 0x0080_C000 to 0x0080_FFFF Low Address Space...
Page 332 Chapter 17 Flash Memory TestFlash block programming restrictions, in terms of how ECC is calculated, are similar to array programming restrictions. Only one program is allowed per 64-bit ECC segment. Locations of the Code TestFlash block marked as reserved cannot be programmed by the user application. Locations of the Data TestFlash block marked as reserved cannot be programmed by the user application.
Page 333 Chapter 17 Flash Memory Table 17-9. Shadow sector structure Size Name Description Addresses (bytes — User Area 0x0020_0000–0x0020_3DCF 15824 — Reserved 0x0020_3DD0–0x0020_3DD7 NVPWD0–1 Non-volatile private censorship password 0–1 registers 0x0020_3DD8–0x0020_3DDF NVSCI0–1 Non-volatile system censorship information 0–1 registers 0x0020_3DE0–0x0020_3DE7 — Reserved 0x0020_3DE8–0x0020_3DFF NVBIU2–3 Non-volatile bus interface unit 2–3 registers...
Page 334 Chapter 17 Flash Memory The default state of the Flash module is the read state. The main, shadow, and test address space can be read only in the read state. The Flash registers are always available for reads. When the module is in power-down mode, most (but not all) registers are available for reads.
Page 335 Chapter 17 Flash Memory If the Flash module is put into Low-power mode during an erase operation, the MCR[ESUS] bit is set to 1. The user may resume the erase operation when the Flash module exits from Low-power mode by clearing MCR[ESUS].
Page 336 Chapter 17 Flash Memory 17.3.6 Registers description The Flash user registers mapping is shown in Table 17-10. Except as noted, registers and offsets are identical for the code Flash and data Flash blocks. Table 17-10. Flash registers Offset from xxxx_BASE Register Location (0xFFFE_C000)
Page 337 Chapter 17 Flash Memory 17.3.7 Register map Table 17-11. Flash 256 KB bank0 register map Address Register offset name 0x00 SIZE2 SIZE1 SIZE0 LAS2 LAS1 LAS0 PEAS DONE PSUS ESUS 0x04 TSLK LLK15 LLK14 LLK13 LLK12 LLK11 LLK10 LLK9 LLK8 LLK7 LLK6 LLK5...
Page 338 Chapter 17 Flash Memory Table 17-11. Flash 256 KB bank0 register map (continued) Address Register offset name 0x54 UMISR3 MS127 MS126 MS125 MS124 MS123 MS122 MS121 MS120 MS119 MS118 MS117 MS116 MS115 MS114 MS113 MS112 MS111 MS110 MS109 MS108 MS107 MS106 MS105 MS104 MS103 MS102 MS101 MS100 MS099 MS098 MS097 MS096 0x58 UMISR4 MS159 MS158 MS157 MS156 MS155 MS154 MS153 MS152 MS151 MS150 MS149 MS148 MS147 MS146 MS145 MS144 MS143 MS142 MS141 MS140 MS139 MS138 MS137 MS136 MS135 MS134 MS133 MS132 MS131 MS130 MS129 MS128...
Page 339 Chapter 17 Flash Memory Table 17-12. Flash 64 KB bank1 register map (continued) Address Register offset name 0x50– Reserved 0x5B In the following sections, some non-volatile registers are described. Please notice that such entities are not Flip-Flops, but locations of TestFlash or Shadow sectors with a special meaning. During the Flash initialization phase, the FPEC reads these non-volatile registers and updates their related volatile registers.
Page 340 Chapter 17 Flash Memory Table 17-13. MCR field descriptions Field Description ECC Data Correction EDC provides information on previous reads. If a ECC Single Error detection and correction occurs, the EDC bit is set to 1. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state.
Page 341 Chapter 17 Flash Memory Table 17-13. MCR field descriptions (continued) Field Description ECC Event Error EER provides information on previous reads. When an ECC Double Error detection occurs, the EER bit is set to 1. This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may not be set to 1 by the user.
Page 342 Chapter 17 Flash Memory Table 17-13. MCR field descriptions (continued) Field Description DONE Modify Operation Done DONE indicates if the Flash module is performing a high voltage operation. DONE is set to 1 on termination of the Flash module reset. DONE is cleared to 0 just after a 0-to-1 transition of EHV, which initiates a high voltage operation, or after resuming a suspended operation.
Page 343 Chapter 17 Flash Memory Table 17-13. MCR field descriptions (continued) Field Description Erase ERS sets up the Flash module for an Erase operation. A 0-to-1 transition of ERS initiates an Erase sequence. A 1-to-0 transition of ERS ends the Erase sequence. ERS can be set only under User mode Read (PGM is low and UT0[AIE] is low).
Page 344 Chapter 17 Flash Memory Table 17-14. MCR bits set/clear priority levels Priority level MCR bits ESUS If the user attempts to write two or more MCR bits simultaneously, only the bit with the lowest priority level is written. 17.3.7.2 Low/Mid Address Space Block Locking register (LML) The Low/Mid Address Space Block Locking register provides a means to protect blocks from being modified.
Page 345 Chapter 17 Flash Memory 17.3.7.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) Address: Base + 0x40_3DE8 Access: User read/write TSLK Reset R LLK Reset Figure 17-12. Non-Volatile Low/Mid Address Space Block Locking register (NVLML) The NVLML register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that are eventually used to manage ECC codes.
Page 346 Chapter 17 Flash Memory Table 17-15. LML and NVLML field descriptions (continued) Field Description LLK[15:0] Low Address Space Block Lock 15-0 16:31 These bits lock the blocks of Low Address Space from program and Erase. For code Flash, LLK[5:0] are related to sectors B0F[5:0], respectively. See Table 17-6 for more information.
Page 347 Chapter 17 Flash Memory Address: Base + 0x000C Access: User read/write R SLE Reset R SLK Reset Figure 17-13. Secondary Low/mid address space block Locking reg (SLL) 17.3.7.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL) The NVSLL register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that are eventually used to manage ECC codes.
Page 348 Chapter 17 Flash Memory Table 17-16. SLL and NVSLL field descriptions (continued) Field Description STSLK Secondary Test/Shadow address space block LocK This bit is used as an alternate means to lock the block of Test and Shadow Address Space from program and Erase (Erase is any case forbidden for Test block).
Page 349 Chapter 17 Flash Memory 17.3.7.6 Low/Mid Address Space Block Select register (LMS) The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on during erase. Identical LMS registers are provided in the code Flash and the data Flash blocks. Address: Base + 0x0010 Access: User read/write Reset...
Page 350 Chapter 17 Flash Memory Address: Base + 0x0018 Access: User read/write Reset R AD Reset Figure 17-16. Address Register (ADR) Table 17-18. ADR field descriptions Field Description Reserved (Read Only) A write to these bits has no effect. A read of these bits always outputs 0. AD[22:3] Address 22–3 9:28...
Page 351 Chapter 17 Flash Memory 17.3.7.7.1 Platform Flash Configuration Register 0 (PFCR0) The Platform Flash Configuration Register 0 (PFCR0) defines the configuration associated with Flash memory bank0, which corresponds to the code Flash. The register is described in Figure 17-17 Table 17-20.
Page 352 Chapter 17 Flash Memory Table 17-20. PFCR0 field descriptions (continued) Field Description Bank0 Write Wait State Control BK0_WWSC This field controls the number of wait states to be added to the Flash array access time for writes. This field must be set to a value appropriate to the operating frequency of the PFlash. Higher operating frequencies require non-zero settings for this field for proper Flash operation.
Page 353 Chapter 17 Flash Memory Table 17-20. PFCR0 field descriptions (continued) Field Description 25-26 Bank0, Port 0 Page Buffer Configuration B0_P0_BCFG This field controls the configuration of the four page buffers in the PFlash controller. The buffers can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers.
Page 354 Chapter 17 Flash Memory 17.3.7.7.2 Platform Flash Configuration Register 1 (PFCR1) The Platform Flash Configuration Register 1 (PFCR1) defines the configuration associated with Flash memory bank1. This corresponds to the data Flash. The register is described in Figure 17-18 Table 17-21.
Page 355 Chapter 17 Flash Memory Table 17-21. PFCR1 field descriptions (continued) Field Description Bank1 Write Wait State Control BK1_WWSC This field controls the number of wait states to be added to the Flash array access time for writes. This field must be set to a value appropriate to the operating frequency of the PFlash. Higher operating frequencies require non-zero settings for this field for proper Flash operation.
Page 356 Chapter 17 Flash Memory Table 17-21. PFCR1 field descriptions (continued) Field Description Bank1, Port 1 Buffer Enable B1_P1_BFE This bit enables or disables read hits from the 128-bit holding register. It is also used to invalidate the contents of the holding register. This bit is set by hardware reset, enabling the use of the holding register.
Page 357 Chapter 17 Flash Memory Table 17-22. PFAPR field descriptions Field Description Reserved, should be cleared. Arbitration Mode ARBM This 2-bit field controls the arbitration for PFlash controllers supporting 2 AHB ports. 00 Fixed priority arbitration with AHB p0 > p1. 01 Fixed priority arbitration with AHB p1 >...
Page 358 Chapter 17 Flash Memory Table 17-23. UT0 field descriptions Field Description User Test Enable This status bit indicates when User Test is enabled. All bits in UT0–2 and UMISR0–4 are locked when this bit is 0. This bit is not writeable to a 1, but may be cleared. The reset value is 0. The method to set this bit is to provide a password, and if the password matches, the UTE bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write.
Page 359 Chapter 17 Flash Memory Table 17-23. UT0 field descriptions (continued) Field Description Array Integrity Sequence AIS determines the address sequence to be used during array integrity checks or Margin Mode. The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths.
Page 360 Chapter 17 Flash Memory Table 17-24. UT1 field descriptions Field Description DAI[31:0] Data Array Input 31–0 0:31 These bits represent the input of the even word of ECC logic used in the ECC Logic Check. The DAI[31:0] bits correspond to the 32 array bits representing Word 0 within the double word. 0 The array bit is forced at 0.
Page 361 Chapter 17 Flash Memory Address: Base + 0x0048 Access: User read/write R MS Reset R MS Reset Figure 17-23. User Multiple Input Signature Register 0 (UMISR0) Table 17-26. UMSIR0 field descriptions Field Description MS[031:000] Multiple input Signature 031–000 0:31 These bits represent the MISR value obtained by accumulating the bits 31:0 of all the pages read from the Flash memory.
Page 362 Chapter 17 Flash Memory 17.3.7.13 User Multiple Input Signature Register 2 (UMISR2) The Multiple Input Signature Register (UMISR2) provides a mean to evaluate the array integrity. UMISR2 represents the bits 95-64 of the whole 144-bit word (2 double words including ECC). UMISR2 is not accessible whenever MCR[DONE] or UT0[AID] are low.
Page 363 Chapter 17 Flash Memory Address: Base + 0x0054 Access: User read/write R MS Reset R MS Reset Figure 17-26. User Multiple Input Signature Register 3 (UMISR3) Table 17-29. UMISR3 field descriptions Field Description MS[127:096] Multiple Input Signature 127–096 0:31 These bits represent the MISR value obtained accumulating bits 127:96 of all the pages read from the Flash memory.
Page 364 Chapter 17 Flash Memory Table 17-30. UMISR4 field descriptions Field Description MS[159:128] Multiple Input Signature 159:128 0:31 These bits represent the MISR value obtained accumulating: • MS[135:128]—8 ECC bits for the even double word • MS138—Single ECC error detection for even double word •...
Page 365 Chapter 17 Flash Memory Address: 0x20_3DDC Access: User read/write R PWD Reset R PWD Reset Figure 17-29. Non-Volatile Private Censorship Password 1 register (NVPWD1) Table 17-32. NVPWD1 field descriptions Field Description 0:31 PWD63–32: PassWorD 63–32 The PWD63–32 registers represent the 32 MSB of the Private Censorship Password. 17.3.7.18 Non-Volatile System Censoring Information 0 register (NVSCI0) The Non-Volatile System Censoring Information 0 register (NVSCI0) stores the 32 LSB of the Censorship Control Word of the device.
Page 366 Chapter 17 Flash Memory Table 17-33. NVSCI0 field descriptions Field Description SC[15:0] Serial Censorship control word 15–0 0:15 These bits represent the 16 LSB of the Serial Censorship Control Word (SCCW). If SC[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Public Access is disabled. If SC[15:0] ...
Page 367 Chapter 17 Flash Memory 17.3.7.20 Non-Volatile User Options register (NVUSRO) The Non-Volatile User Options Register (NVUSRO) contains configuration information for the user application. NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that are eventually used to manage ECC codes.
Page 368 Chapter 17 Flash Memory 17.3.8 Code Flash programming considerations 17.3.8.1 Modify operation All the modify operations of the Flash module are managed through the Flash user registers interface. All the sectors of the Flash module belong to the same partition (Bank), therefore when a Modify operation is active on some sectors, no read access is possible on any other sector (Read-While-Modify is not supported).
Page 369 Chapter 17 Flash Memory 4. Deselect current operation by clearing MCR[PGM] and MCR[ERS] (or UT0[MRE] and UT0[EIE]). If a modify operation is on-going in one of the Flash blocks, it is forbidden to start any other modify operation on the other Flash block. In the following sections, all the possible modify operations are described and some examples of the sequences needed to activate them are presented.
Page 370 Chapter 17 Flash Memory 8. If more addresses are to be programmed, return to step 2. 9. Write a logic 0 to the MCR[PGM] bit to terminate the program operation. A program operation may be initiated with the 0-to-1 transition of the MCR[PGM] bit or by clearing the MCR[EHV] bit at the end of a previous program.
Page 371 Chapter 17 Flash Memory The Erase operation consists of the following sequence of events: 1. Change the value in the MCR[ERS] bit from 0 to 1. 2. Select the block(s) to be erased by writing 1s to the LMS register. If the shadow block is to be erased, this step may be skipped, and LMS is ignored.
Page 372 Chapter 17 Flash Memory During erase suspend, all reads to blocks targeted for erase return indeterminate data. An erase suspend can be initiated by changing the value of the MCR[ESUS] bit from 0 to 1. MCR[ESUS] can be set to 1 at any time when MCR[ERS] and MCR[EHV] are high and MCR[PGM] is low. A 0-to-1 transition of MCR[ESUS] causes the module to start the sequence that places it in erase suspend.
Page 373 Chapter 17 Flash Memory The internal MISR calculator is a 32-bit register. The 128-bit data, the 16-bit ECC data, and the single and double ECC errors of the two double words are therefore captured by the MISR through five different read accesses at the same location. The whole check is done through five complete scans of the memory address space: 1.
Page 374 Chapter 17 Flash Memory = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */ = 0x80000002; /* Set AIE in UT0: Operation Start */ /* Loop to wait for AID=1 */ { tmp = UT0; /* Read UT0 */ } while ( !(tmp & 0x00000001) ); data0 = UMISR0;...
Page 375 Chapter 17 Flash Memory During the execution of the Margin Mode operation it is forbidden to modify the content of Block Select (LMS) and Lock (LML, SLL) registers, otherwise the MISR value can vary in an unpredictable way. The read accesses will be done with the addition of a proper number of wait states to guarantee the correctness of the result.
Page 376 Chapter 17 Flash Memory Example 17-7. ECC logic check = 0xF9F99999; /* Set UTE in UT0: Enable User Test */ = 0x55555555; /* Set DAI31-0 in UT1: Even Word Input Data */ = 0xAAAAAAAA; /* Set DAI63-32 in UT2: Odd Word Input Data */ = 0x80FF0000;...
Page 377 Chapter 17 Flash Memory Table 17-37. Bits manipulation: double words with the same ECC value Double word ECC value – All 1s No Error 0xFFFF_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_FFFF_0000 0xFF 0xFFFF_FFFF_0000_FFFF 0xFF 0xFFFF_0000_FFFF_FFFF 0xFF 0x0000_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_0000_0000 0xFF 0xFFFF_0000_FFFF_0000 0xFF 0x0000_FFFF_FFFF_0000 0xFF 0xFFFF_0000_0000_FFFF 0xFF 0x0000_FFFF_0000_FFFF...
Page 378 Chapter 17 Flash Memory A software mechanism is provided to independently lock/unlock each Low or Mid Address Space block against program and erase. Software locking is done through the LML (Low/Mid Address Space Block Lock Register) register. An alternate means to enable software locking for blocks of Low Address Space only is through the SLL (Secondary Low/Mid Address Space Block Lock Register).
Page 379 Chapter 17 Flash Memory Table 17-38. Bits manipulation: censorship management Censored mode Public access NVSCI0 NVSCI1 Enabled Enabled 0xFFFF_FFFF 0xFFFF_FFFF Disabled Enabled 0xFFFF_55AA 0xFFFF_55AA Enabled Disabled 0x55AA_FFFF 0x55AA_FFFF Disabled Disabled 0x55AA_55AA 0x55AA_55AA Enabled Disabled 0x55AA_0000 0x55AA_0000 Disabled Enabled 0x0000_55AA 0x0000_55AA Enabled Enabled 0x0000_0000...
Page 380 Chapter 17 Flash Memory MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 381 Chapter 18 Enhanced Direct Memory Access (eDMA) Chapter 18 Enhanced Direct Memory Access (eDMA) 18.1 Introduction This chapter describes the enhanced Direct Memory Access (eDMA) Controller, a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. 18.2 Overview The enhanced direct memory access (eDMA) controller hardware microarchitecture includes a DMA...
Page 382 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.3 Features The eDMA is a highly programmable data transfer engine, which has been optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known, and is not defined within the data packet itself.
Page 383 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.4 Modes of operation 18.4.1 Normal mode In normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. 18.4.2 Debug mode If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant a service...
Page 384 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5 Memory map and register definition 18.5.1 Memory map The eDMA programming model is partitioned into two regions: Region 1 defines control registers; Region 2 defines the local transfer control for the descriptor memory. Table 18-1 is a 32-bit view of the eDMA memory map.
Page 385 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-1. eDMA memory map (continued) Offset from EDMA_BASE Register Location (0xFFF4_4000) 0x002C EDMA_ERL—eDMA Error on page 397 Register 0x0030 Reserved 0x0034 EDMA_HRSL—eDMA on page 398 Hardware Request Status Register 0x0038–0x00FF Reserved 0x0100 EDMA_CPR0—eDMA Channel on page 399 0 Priority Register...
Page 386 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-1. eDMA memory map (continued) Offset from EDMA_BASE Register Location (0xFFF4_4000) 0x0110–0x0FFF Reserved 0x1000 TCD00—Transfer Control on page 400 Descriptor 0 0x1020 TCD01—Transfer Control on page 400 Descriptor 1 0x1040 TCD02—Transfer Control on page 400 Descriptor 2 0x1060...
Page 387 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2 Register descriptions Read operations on reserved bits in a register return undefined data. Do not write operations to reserved bits. Writing to reserved bits in a register can generate errors. The maximum register bit-width for this device is 16 bits wide.
Page 388 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.2 eDMA Error Status Register (EDMA_ESR) The EDMA_ESR provides information concerning the last recorded channel error. Channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
Page 389 Chapter 18 Enhanced Direct Memory Access (eDMA) Address: Base + 0x0004 Access: User read-only R VLD Reset R GPE CPE ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE Reset Figure 18-3. eDMA Error Status Register (EDMA_ESR) Table 18-3. EDMA_ESR field descriptions Field Description Logical OR of all EDMA_ERH and EDMA_ERL status bits.
Page 390 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-3. EDMA_ESR field descriptions (continued) Field Description NBYTES/CITER configuration error. 0 No NBYTES/CITER configuration error. 1 The last recorded error was a configuration error detected in the TCD.NBYTES or TCD.CITER fields, indicating the following conditions exist: •...
Page 391 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-4. EDMA_ERQRL field descriptions Field Description 16–31 Enable DMA hardware service request n. ERQn 0 The DMA request signal for channel n is disabled. 1 The DMA request signal for channel n is enabled. As a given channel completes the processing of its major iteration count, there is a flag in the transfer control descriptor that can affect the ending state of the EDMA_ERQR bit for that channel.
Page 392 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.5 eDMA Set Enable Request Register (EDMA_SERQR) The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the EDMA_ERQRL to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the EDMA_ERQRL to be set.
Page 393 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-7. EDMA_CERQR field descriptions Field Description Reserved. 1–7 Clear enable request. CERQ[0:6] 0–15 Clear corresponding bit in EDMA_ERQRL 16–63Reserved 64–127Clear all bits in EDMA_ERQRL Note: Bit 2 (CERQ1) is not used. 18.5.2.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the EDMA_EEIRL to enable the error interrupt for a given channel.
Page 394 Chapter 18 Enhanced Direct Memory Access (eDMA) Address: Base + 0x001B Access: User write-only CEEI[0:6] Reset Figure 18-9. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR) Table 18-9. EDMA_CEEIR field descriptions Field Description Reserved. 1–7 Clear enable error interrupt. CEEI[0:6] 0–15 Clear corresponding bit in EDMA_EEIRL 16–63 Reserved 64–127 Clear all bits in EDMA_EEIRL Note: Bit 2 (CEEI1) is not used.
Page 395 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.10 eDMA Clear Error Register (EDMA_CERR) The EDMA_CERR provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the EDMA_ERL to be cleared.
Page 396 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) The EDMA_CDSBR provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared.
Page 397 Chapter 18 Enhanced Direct Memory Access (eDMA) Address: Base + 0x0024 Access: User read/write Reset R INT Reset Figure 18-14. eDMA Interrupt Request Low Register (EDMA_IRQRL) Table 18-14. EDMA_IRQRL field descriptions Field Description 16–31 eDMA interrupt request n. INTn 0 The interrupt request for channel n is cleared. 1 The interrupt request for channel n is active.
Page 398 Chapter 18 Enhanced Direct Memory Access (eDMA) Address: Base + 0x002C Access: User read/write Reset R ERR Reset Figure 18-15. eDMA Error Low Register (EDMA_ERL) Table 18-15. EDMA_ERL field descriptions Field Description 16–31 eDMA Error n. ERRn 0 An error in channel n has not occurred. 1 An error in channel n has occurred.
Page 399 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.16 eDMA Channel n Priority Registers (EDMA_CPRn) When the fixed-priority channel arbitration mode is enabled (EDMA_CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel within a group. The channel priorities are evaluated by numeric value;...
Page 400 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.5.2.17 Transfer Control Descriptor (TCD) Each channel requires a 256-bit transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,...
Page 401 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-18. TCDn 32-bit memory structure (continued) TCDn eDMA Bit Offset TCDn Field Name Word # Length Abbreviation 0x1000 + (32 × n) + Channel-to-channel Linking on Minor Loop BITER.E_LINK Word 7 Complete 0x1000 + (32 ×...
Page 402 Chapter 18 Enhanced Direct Memory Access (eDMA) Word 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Offset SADDR SMOD SSIZE DMOD DSIZE SOFF NBYTES SLAST 0x10 DADDR 0x14...
Page 403 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-19. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] 32–36 SMOD Source address modulo. 0x4 [0:4] [0:4] Source address modulo feature is disabled. not 0 This value defines a specific address range that is specified to be either the value after SADDR + SOFF calculation is performed or the original register value.
Page 404 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-19. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] CITER.E_LINK Enable channel-to-channel linking on minor loop completion. As the channel 0x14 [0] completes the inner minor loop, this flag enables the linking to another channel, defined by CITER.LINKCH[0:5].
Page 405 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-19. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] BITER.E_LINK Enables channel-to-channel linking on minor loop complete. As the channel 0x1C [0] completes the inner minor loop, this flag enables the linking to another channel, defined by BITER.LINKCH[0:5].
Page 406 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-19. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] 242–247 MAJOR.LINKC Link channel number. If channel-to-channel linking on major loop complete is 0x1C [18:23] disabled (TCD.MAJOR.E_LINK = 0) then: [0:5] •...
Page 407 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-19. TCDn field descriptions (continued) Bits Word Offset Field Name Description [n:n] INT_HALF Enable an interrupt when major counter is half complete. 0x1C [29] If this flag is set, the channel generates an interrupt request by setting the bit in the EDMA_ERQL when the current major iteration count reaches the halfway point.
Page 408 Chapter 18 Enhanced Direct Memory Access (eDMA) the TCDn.{SADDR, DADDR, CITER} back into the local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
Page 409 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.6.2 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 18-19, the first segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request service for channel n.
Page 410 Chapter 18 Enhanced Direct Memory Access (eDMA) This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA Done Handshake signal is asserted at the end of the minor byte count transfer. eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address...
Page 411 Chapter 18 Enhanced Direct Memory Access (eDMA) eDMA SRAM Transfer Control Descriptor (TCD) Slave Write Address Slave Write Data SRAM TCD0 TCDn – 1* eDMA Engine Bus Read Data Program Model/ Channel Arbitration Address Control Data Path Slave Read Data Path Bus Write Data Bus Address...
Page 412 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-20. eDMA peak transfer rates (MB/Sec) Internal SRAM-to- Internal SRAM-to- System Speed, Internal SRAM-to- 32-bit Slave-to- 32-bit Slave 32-bit Slave Transfer Size Internal SRAM Internal SRAM (buffering disabled) (buffering enabled) 66.7 MHz, 32-bit 66.7 66.7 53.3...
Page 413 Chapter 18 Enhanced Direct Memory Access (eDMA) • Cycle 7: The first system bus read cycle is initiated, as the third part of the channel’s TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus can insert an additional cycle of delay here.
Page 414 Chapter 18 Enhanced Direct Memory Access (eDMA) read_ws — wait states seen during the system bus read data phase write_ws — wait states seen during the system bus write data phase exit — channel shutdown (three cycles) For example: consider a system with the following characteristics: •...
Page 415 Chapter 18 Enhanced Direct Memory Access (eDMA) 4. Write the 32-byte TCD for each channel that can request service. 5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers. 6. Request channel service by either software (setting the TCD.START bit) or by hardware (slave device asserting its eDMA peripheral request signal).
Page 416 Chapter 18 Enhanced Direct Memory Access (eDMA) Current Major Loop Example Memory Array Iteration Count (CITER) DMA Request • Minor Loop • • DMA Request • Minor Loop Major Loop • • DMA Request • Minor Loop • • Figure 18-22. Example of multiple loop iterations Figure 18-23 lists the memory array terms and how the TCD settings interrelate.
Page 417 Chapter 18 Enhanced Direct Memory Access (eDMA) If priority levels are not unique, the highest (channel/group) priority that has an active request is selected, but the lowest numbered (channel/group) with that priority is selected by arbitration and executed by the eDMA engine.
Page 418 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.7.5 DMA transfer 18.7.5.1 Single request To perform a simple transfer of ‘n’ bytes of data with one activation, set the major loop to 1 (TCD.CITER = TCD.BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute.
Page 419 Chapter 18 Enhanced Direct Memory Access (eDMA) g) read_byte (0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f) h) write_word (0x200c)  last iteration of the minor loop  major loop complete 6. eDMA engine writes: TCD.SADDR = 0x1000, TCD.DADDR = 0x2000, TCD.CITER = 1 (TCD.BITER). 7.
Page 420 Chapter 18 Enhanced Direct Memory Access (eDMA) e) read_byte (0x1008), read_byte (0x1009), read_byte (0x100a), read_byte (0x100b) f) write_word (0x2008)  third iteration of the minor loop g) read_byte (0x100c), read_byte (0x100d), read_byte (0x100e), read_byte (0x100f) h) write_word (0x200c)  last iteration of the minor loop 6.
Page 421 Chapter 18 Enhanced Direct Memory Access (eDMA) Table 18-24. Modulo feature example Transfer Number Address 0x12345670 0x12345674 0x12345678 0x1234567C 0x12345670 0x12345674 18.7.6 TCD status 18.7.6.1 Minor loop complete There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.CITER field and test for a change.
Page 422 Chapter 18 Enhanced Direct Memory Access (eDMA) 18.7.6.2 Active channel TCD reads the eDMA reads the true TCD.SADDR, TCD.DADDR, and TCD.NBYTES values if read while a channel is executing. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine is currently using in its internal register file and not the values in the TCD local memory for that channel.
Page 423 Chapter 18 Enhanced Direct Memory Access (eDMA) When minor loop linking is enabled (TCD.CITER.E_LINK = 1), the TCD.CITER field uses a nine bit vector to form the current iteration count. When minor loop linking is disabled (TCD.CITER.E_LINK = 0), the TCD.CITER field uses a 15-bit vector to form the current iteration count.
Page 424 Chapter 18 Enhanced Direct Memory Access (eDMA) 2. Read the TCD.MAJOR.E_LINK bit 3. Test the TCD.MAJOR.E_LINK request status: a) If the bit is set, the dynamic link attempt was successful.D b) If the bit is cleared, the channel had already retired before the dynamic link completed. This same coherency model is true for dynamic scatter/gather operations.
Page 425 Chapter 19 DMA Channel Mux (DMA_MUX) Chapter 19 DMA Channel Mux (DMA_MUX) 19.1 Introduction 19.1.1 Overview The DMA Mux allows to route a configurable amount of DMA sources (slots) to a configurable amount of DMA channels. This is illustrated in Figure 19-1.
Page 426 Chapter 19 DMA Channel Mux (DMA_MUX) • Each channel router can be assigned to 1 of 21 possible peripheral DMA sources 19.1.3 Modes of operation The following operation modes are available: • Disabled Mode In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA Channel Mux.
Page 427 Chapter 19 DMA Channel Mux (DMA_MUX) Table 19-1. DMA_MUX memory map (continued) Offset from DMA_MUX_BASE Register Location (0xFFFD_C000) 0x0002 Channel #2 Configuration (CHCONFIG2) on page 428 0x0003 Channel #3 Configuration (CHCONFIG3) on page 428 0x0004 Channel #4 Configuration (CHCONFIG4) on page 428 0x0005 Channel #5 Configuration (CHCONFIG5) on page 428...
Page 428 Chapter 19 DMA Channel Mux (DMA_MUX) All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit READ/WRITE to address ‘Base + 0x0000’, but performing a 32-bit access to address ‘Base + 0x0001’...
Page 429 Chapter 19 DMA Channel Mux (DMA_MUX) NOTE Setting multiple CHCONFIG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCONFIG[#n].ENBL bit. 19.4 DMA request mapping Table 19-4.
Page 430 Chapter 19 DMA Channel Mux (DMA_MUX) Table 19-4. DMA channel mapping (continued) DMA_CH_MUX DMA requesting Module DMA Mux input # channel module — ALWAYS requestors DMA MUX Source #25 — ALWAYS requestors DMA MUX Source #26 — ALWAYS requestors DMA MUX Source #27 —...
Page 431 Chapter 19 DMA Channel Mux (DMA_MUX) Source #1 Source #2 Source #3 DMA Channel #0 Trigger #1 Trigger #2 Source #21 DMA Channel #3 Trigger #4 Always #1 Always #9 Figure 19-3. DMA mux triggered channels diagram The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 432 Chapter 19 DMA Channel Mux (DMA_MUX) Peripheral Request Trigger DMA Request Figure 19-5. DMA mux channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •...
Page 433 Chapter 19 DMA Channel Mux (DMA_MUX) 19.5.2 DMA channels with no triggering capability Channels 4–15 of the DMA Mux provide the normal routing functionality as described in Section 19.1.3, “Modes of operation. Source #1 Source #2 Source #3 DMA Channel #4 Source #21 DMA Channel #15 Always #1...
Page 434 Chapter 19 DMA Channel Mux (DMA_MUX) 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. In the PIT, configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG register, ensuring that the ENBL and TRIG bits are set.
Page 435 Chapter 19 DMA Channel Mux (DMA_MUX) Example 19-2. Configure source #5 Transmit for use with DMA Channel 2, with no periodic triggering capability. 1. Write 0x00 to CHCONFIG2 (Base Address + 0x02). 2. Configure Channel 2 in the DMA, including enabling the channel. 3.
Page 436 Chapter 19 DMA Channel Mux (DMA_MUX) 3. Write 0x87 to CHCONFIG8 (Base Address + 0x08). In this case, setting the TRIG bit would have no effect, because channels 8 and above do not support the periodic triggering functionality. The following code example illustrates steps 2 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */...
Page 437 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.1 Introduction This chapter describes the deserial serial peripheral interface (DSPI), which provides a synchronous serial bus for communication between the MCU and an external peripheral device. The MPC5602P implements the modules DSPI0, 1 and 2.
Page 438 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.3 Overview The register content is transmitted using an SPI protocol. There are three DSPI modules (DSPI_0, DSPI_1, and DSPI_2) on the device. The modules are identical except that DSPI_0 has four additional chip select (CS) lines.
Page 439 Chapter 20 Deserial Serial Peripheral Interface (DSPI) — Continuously held chip select capability • 8 peripheral chip selects, expandable to 64 with external demultiplexer • Deglitching support for as many as 32 peripheral chip selects with external demultiplexer • 2 DMA conditions for SPI queues residing in RAM or flash —...
Page 440 Chapter 20 Deserial Serial Peripheral Interface (DSPI) must be configured as input and pulled high. If the internal pullup is being used then the appropriate bits in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1], [WPS = 1]). For more information, refer to Section 20.8.1.2, “Slave mode.
Page 441 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.6.2 Signal names and descriptions 20.6.2.1 Peripheral Chip Select / Slave Select (CS_0) In master mode, the CS_0 signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. In slave mode, the CS_0 signal is a slave select input signal that allows an SPI master to select the DSPI as the target for transmission.
Page 442 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.6.2.7 Serial Clock (SCK_x) SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCK_x is an input from an external bus master. 20.7 Memory map and registers description 20.7.1 Memory map Table 20-2...
Page 443 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-2. DSPI memory map (continued) Offset from DSPI_BASE 0xFFF9_0000 (DSPI_0) Register Location 0xFFF9_4000 (DSPI_1) 0xFFF9_8000 (DSPI_2) 0x0044 DSPI_TXFR2—DSPI transmit FIFO register 2 on page 459 0x0048 DSPI_TXFR3—DSPI transmit FIFO register 3 on page 459 0x004C DSPI_TXFR4—DSPI transmit FIFO register 4 on page 459...
Page 444 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-3. DSPIx_MCR field descriptions Field Description Master/slave mode select MSTR Configures the DSPI for master mode or slave mode. 0 DSPI is in slave mode. 1 DSPI is in master mode. Continuous SCK enable CONT_SCKE Enables the serial communication clock (SCK) to run continuously.
Page 445 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-3. DSPIx_MCR field descriptions (continued) Field Description 10–15 Peripheral chip select inactive state PCSISn Determines the inactive state of the CS0_x signal. CS0_x must be configured as inactive high for slave mode operation. 0 The inactive state of CS0_x is low.
Page 446 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-3. DSPIx_MCR field descriptions (continued) Field Description 22–23 Sample point SMPL_PT Allows the host software to select when the DSPI master samples SIN in modified transfer format. [0:1] Figure 20-18 shows where the master can sample the SIN pin. The following table lists the delayed sample points.
Page 447 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-4. DSPIx_TCR field descriptions Field Description 0–15 SPI transfer counter SPI_TCNT Counts the number of SPI transfers the DSPI makes. The SPI_TCNT field is incremented every time [0:15] the last bit of an SPI frame is transmitted. A value written to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at the beginning of the frame when the CTCNT field is set in the executing SPI command.
Page 448 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Address: Base + 0x000C (DSPIx_CTAR0) Base + 0x001C (DSPIx_CTAR4) Access: User read/write Base + 0x0010 (DSPIx_CTAR1) Base + 0x0020 (DSPIx_CTAR5) Base + 0x0014 (DSPIx_CTAR2) Base + 0x0024 (DSPIx_CTAR6) Base + 0x0018 (DSPIx_CTAR3) Base + 0x0028 (DSPIx_CTAR7) FMSZ PCSSCK PASC...
Page 449 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-5. DSPIx_CTARn field descriptions (continued) Field Descriptions LSB First LSBFE The LSBFE bit selects if the LSB or MSB of the frame is transferred first. This bit is only used in Master Mode. 0 Data is transferred MSB first.
Page 450 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-5. DSPIx_CTARn field descriptions (continued) Field Descriptions 14–15 Baud Rate Prescale PBR[0:1] The PBR field selects the prescaler value for the baud rate. This field is only used in Master Mode. The baud rate is the frequency of the Serial Communications Clock (SCK). The system clock is divided by the prescaler value before the baud rate selection takes place.
Page 451 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-5. DSPIx_CTARn field descriptions (continued) Field Descriptions 28–31 Baud Rate Scaler BR[0:3] The BR field selects the scaler value for the baud rate. This field is only used in Master Mode. The pre-scaled system clock is divided by the baud rate scaler to generate the frequency of the SCK.
Page 452 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-8. DSPI PCS to SCK delay scaler CSSCK PCS to SCK delay scaler value CSSCK PCS to sck delay scaler value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192...
Page 453 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-11. DSPI baud rate scaler Baud rate scaler value Baud rate scaler value 0000 1000 0001 1001 0010 1010 1024 0011 1011 2048 0100 1100 4096 0101 1101 8192 0110 1110 16384 0111 1111 32768...
Page 454 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-12. DSPIx_SR field descriptions (continued) Field Description End of queue flag EOQF Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and after the last incoming databit is sampled, but before the tASC delay starts.
Page 455 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-12. DSPIx_SR field descriptions (continued) Field Description 20–23 Transmit next pointer TXNXTPTR Indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR field is [0:3] updated every time SPI data is transferred from the TX FIFO to the shift register. Refer to Section 20.8.3.4, “Transmit First In First Out (TX FIFO) buffering mechanism for more details.
Page 456 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-13. DSPIx_RSER field descriptions (continued) Field Description Transmit FIFO underflow request enable TFUF_RE The TFUF_RE bit enables the TFUF flag in the DSPIx_SR to generate an interrupt request. 0 TFUF interrupt requests are disabled. 1 TFUF interrupt requests are enabled.
Page 457 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Address Base + 0x0034 Access: User read/write CONT CTAS Reset TXDATA Reset Figure 20-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) Table 20-14. DSPIx_PUSHR field descriptions Field Description Continuous peripheral chip select enable CONT Selects a continuous selection format.
Page 458 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-14. DSPIx_PUSHR field descriptions (continued) Field Description Clear SPI_TCNT CTCNT Provides a means for host software to clear the SPI transfer counter. The CTCNT bit clears the SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the current SPI frame begins.
Page 459 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-15. DSPIx_POPR field descriptions Field Description 0–15 Reserved, must be cleared. 16–31 Received data RXDATA The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next [0:15] data pointer (POPNXTPTR).
Page 460 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Address: Base + 0x007C (DSPIx_RXFR0) Base + 0x0088 (DSPIx_RXFR3) Access: User read-only Base + 0x0080 (DSPIx_RXFR1) Base + 0x008C (DSPIx_RXFR4) Base + 0x0084 (DSPIx_RXFR2) Reset RXDATA Reset Figure 20-11. DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) Table 20-17.
Page 461 Chapter 20 Deserial Serial Peripheral Interface (DSPI) DSPI Master DSPI Slave SIN_x SOUT_x Shift register Shift register SOUT_x SIN_x SCK_x SCK_x CS_x CS0_x Baud rate generator Figure 20-12. SPI serial protocol overview Each DSPI has four peripheral chip select (CSx) signals that select the slaves with which to communicate (DSPI_0 has eight CSx signals.) Transfer protocols and timing properties are shared by the three DSPI configurations;...
Page 462 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.1.2 Slave mode In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected by a bus master by having the slave’s CS0_x asserted.
Page 463 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-18. State transitions for start and stop of DSPI transfers Transition # Current State Next State Description RESET STOPPED Generic power-on-reset transition STOPPED RUNNING The DSPI starts (transitions from STOPPED to RUNNING) when all of the following conditions are true: •...
Page 464 Chapter 20 Deserial Serial Peripheral Interface (DSPI) pin. In SPI master mode, each SPI frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. Refer to Section 20.7.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR) for details on the SPI command fields.
Page 465 Chapter 20 Deserial Serial Peripheral Interface (DSPI) transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the shift register. 20.8.3.4.1 Filling the TX FIFO Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the DSPIx_PUSHR.
Page 466 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.3.5.1 Filling the RX FIFO The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full, SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred to the RX FIFO the RX FIFO counter is incremented by one.
Page 467 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-19 shows an example of a computed baud rate. Table 20-19. Baud rate computation example Prescaler value Scaler value DBR value Baud rate 100 MHz 0b00 0b0000 25 Mbit/s 20 MHz 0b00 0b0000 10 Mbit/s 20.8.4.2...
Page 468 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.4.4 Delay after transfer (t The delay after transfer is the length of time between negation of the CSx signal for a frame and the assertion of the CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers select the delay after transfer.
Page 469 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Eqn. 20-10  PASC PASC Table 20-23 shows an example of the computed t delay. PCSSCK Table 20-23. Peripheral Chip Select strobe assert computation example PCSSCK Prescaler Delay before transfer 0b11 100 MHz 70.0 ns Table 20-24 shows an example of the computed the t...
Page 470 Chapter 20 Deserial Serial Peripheral Interface (DSPI) In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames. Refer to Section 20.8.5.5, “Continuous selection format for details. 20.8.5.1 Classic SPI transfer format (CPHA = 0) The transfer format shown in Figure 20-16 is used to communicate with peripheral SPI slave devices...
Page 471 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.5.2 Classic SPI transfer format (CPHA = 1) The transfer format shown in Figure 20-17 is used to communicate with peripheral SPI slave devices that require the first SCK_x edge before the first data bit becomes available on the slave SOUT_x pin. In this format the master and slave devices change the data on their SOUT_x pins on the odd-numbered SCK_x edges and sample the data on their SIN_x pins on the even-numbered SCK_x edges.
Page 472 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) In this modified transfer format both the master and the slave sample later in the SCK period than in classic SPI mode to allow for delays in device pads and board traces. These delays become a more significant fraction of the SCK period as the SCK period decreases with increasing baud rates.
Page 473 Chapter 20 Deserial Serial Peripheral Interface (DSPI) System clock Slave sample Master sample Slave SOUT Master SOUT System clock System clock = CS to SCK delay. = After SCK delay. Figure 20-18. DSPI modified transfer format (MTFE = 1, CPHA = 0, f / 4) 20.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1)
Page 474 Chapter 20 Deserial Serial Peripheral Interface (DSPI) System clock Slave sample Master sample Master SOUT Slave SOUT = CS to SCK delay. = After SCK delay. Figure 20-19. DSPI modified transfer format (MTFE = 1, CPHA = 1, f / 4) 20.8.5.5 Continuous selection format Some peripherals must be deselected between every transfer.
Page 475 Chapter 20 Deserial Serial Peripheral Interface (DSPI) When the CONT = 1 and the CS signal for the next transfer is the same as for the current transfer, the CS signal remains asserted for the duration of the two transfers. The delay between transfers (t ) is not inserted between the transfers.
Page 476 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Figure 20-22, time ‘A’ shows the one clock interval. Time ‘B’ is user programmable from a minimum of two system clocks. System clock Frame 0 Frame 1 CPOL = 0 CPOL = 1 Figure 20-22.
Page 477 Chapter 20 Deserial Serial Peripheral Interface (DSPI) (CPOL = 0) (CPOL = 1) Master SOUT Master SIN = 1 SCK. Figure 20-23. Continuous SCK timing diagram (CONT = 0) If the CONT bit in the TX FIFO entry is set, CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer.
Page 478 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.7 Interrupts/DMA requests The DSPI has conditions that can generate interrupt requests only, and conditions that can generate interrupts or DMA requests. Table 20-26 lists these conditions. Table 20-26. Interrupt and DMA request conditions Condition Flag Interrupt...
Page 479 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.8.7.4 Transmit FIFO underflow interrupt request (TFUF) The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI configuration.
Page 480 Chapter 20 Deserial Serial Peripheral Interface (DSPI) in the DSPI return the correct values when read, but writing to them has no affect. Writing to the DSPIx_TCR during module disable mode does not have an effect. Interrupt and DMA request signals cannot be cleared while in the module disable mode.
Page 481 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Table 20-27. Baud rate values Baud Rate divider prescaler values (DSPI_CTAR[PBR]) 25.0 MHz 16.7 MHz 10.0 MHz 7.14 MHz 12.5 MHz 8.33 MHz 5.00 MHz 3.57 MHz 8.33 MHz 5.56 MHz 3.33 MHz 2.38 MHz 6.25 MHz 4.17 MHz...
Page 482 Chapter 20 Deserial Serial Peripheral Interface (DSPI) 20.9.3 Delay settings Table 20-28 shows the values for the delay after transfer (t ) and CS to SCK delay (t ) that can be generated based on the prescaler values and the scaler values set in the DSPIx_CTARs. The values calculated assume a 100 MHz system frequency.
Page 483 Chapter 20 Deserial Serial Peripheral Interface (DSPI) The following delay variables generate the same delay, or as close as possible, from the DSPI_100 MHz system clock that a QSPI generates from a 40 MHz system clock. For other system clock frequencies, you can recompute the values using the information presented in Section 20.9.3, “Delay settings.”...
Page 484 Chapter 20 Deserial Serial Peripheral Interface (DSPI) Transmit next TX FIFO base data pointer – (TXNXTPTR) – Push TX FIFO register Entry A (first in) Entry B Entry C Entry D (last in) Shift register SOUT – – TX FIFO counter –...
Page 485 Chapter 20 Deserial Serial Peripheral Interface (DSPI) The memory address of the last-in entry in the RX FIFO is computed by the following equation: Eqn. 20-14 Last-in entry address = RXFIFO base + 4 × [(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter...
Page 486 Chapter 20 Deserial Serial Peripheral Interface (DSPI) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 487 Chapter 21 LIN Controller (LINFlex) Chapter 21 LIN Controller (LINFlex) 21.1 Introduction The LINFlex (Local Interconnect Network Flexible) controller interfaces the LIN network and supports the LIN protocol versions 1.3; 2.0 2.1; and J2602 in both Master and Slave modes. LINFlex includes a LIN mode that provides additional features (compared to standard UART) to ease LIN implementation, improve system robustness, minimize CPU load and allow slave node resynchronization.
Page 488 Chapter 21 LIN Controller (LINFlex) — Initialization — Normal — Sleep • 2 test modes: — Loop Back — Self Test • Maskable interrupts 21.3 General description The increasing number of communication peripherals embedded on microcontrollers, for example CAN, LIN and SPI, requires more and more CPU resources for communication management. Even a 32-bit microcontroller is overloaded if its peripherals do not provide high-level features to autonomously handle the communication.
Page 489 Chapter 21 LIN Controller (LINFlex) Application LINFlex Controller Transceiver LIN Bus Figure 21-1. LIN topology network REGISTER MODEL / APPLICATION INTERFACE Message Buffer Interface CONFIGURATION CONTROL STATUS LIN control LIN status Baud rate SLAVE MESSAGE HANDLER Filter configuration MASTER MESSAGE HANDLER Identifier Filters LIN PROTOCOL HANDLER 1.
Page 490 Chapter 21 LIN Controller (LINFlex) Eqn. 21-1 periph_set_1_clk Tx/ Rx baud = (16 × LFDIV) LFDIV is an unsigned fixed point number. The 12-bit mantissa is coded in the LINIBRR and the fraction is coded in the LINFBRR. The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values: Example 21-1.
Page 491 Chapter 21 LIN Controller (LINFlex) Table 21-1. Error calculation for programmed baud rates (continued) 64 MHz 16 MHz periph_set_1_clk periph_set_1_clk Value programmed % Error = % Error = Baud (Calculated – Value programmed in (Calculated – rate the baud rate Desired) the baud rate register Desired)
Page 492 Chapter 21 LIN Controller (LINFlex) 21.5.1 Initialization mode The software can be initialized while the hardware is in Initialization mode. To enter this mode the software sets the INIT bit in the LINCR1. To exit Initialization mode, the software clears the INIT bit. While in Initialization mode, all message transfers to and from the LIN bus are stopped and the status of the LIN bus output LINTX is recessive (high).
Page 493 Chapter 21 LIN Controller (LINFlex) LINFlex LINTX LINRX Figure 21-4. LINFlex in loop back mode This mode is provided for self test functions. To be independent of external events, the LIN core ignores the LINRX signal. In this mode, the LINFlex performs an internal feedback from its Tx output to its Rx input.
Page 494 Chapter 21 LIN Controller (LINFlex) Table 21-2. LINFlex memory map Address offset Register Location 0x0000 LIN control register 1 (LINCR1) on page 495 0x0004 LIN interrupt enable register (LINIER) on page 498 0x0008 LIN status register (LINSR) on page 499 0x000C LIN error status register (LINESR) on page 502...
Page 495 Chapter 21 LIN Controller (LINFlex) Table 21-2. LINFlex memory map (continued) Address offset Register Location 0x0084 Identifier filter control register 14 (IFCR14) on page 517 0x0088 Identifier filter control register 15 (IFCR15) on page 517 0x008C–0x000F Reserved LSB: Least significant byte MSB: Most significant byte 21.7.1.1 LIN control register 1 (LINCR1)
Page 496 Chapter 21 LIN Controller (LINFlex) Table 21-3. LINCR1 field descriptions (continued) Field Description AWUM Automatic Wake-Up Mode This bit controls the behavior of the LINFlex hardware during Sleep mode. 0 The Sleep mode is exited on software request by clearing the SLEEP bit of the LINCR. 1 The Sleep mode is exited automatically by hardware on LINRX dominant state detection.
Page 497 Chapter 21 LIN Controller (LINFlex) Table 21-4. Checksum bits configuration LINCFR Checksum sent Read/Write None Read-only None Read/Write Programmed in LINCFR by bits CF[0:7] Read-only Hardware calculated Table 21-5. LIN master break length selection Length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit...
Page 498 Chapter 21 LIN Controller (LINFlex) 21.7.1.2 LIN interrupt enable register (LINIER) Offset: 0x0004 Access: User read/write Reset SZIE OCIE BEIE CEIE HEIE FEIE BOIE LSIE WUIE DBFIE DBEIE DRIE DTIE HRIE Reset Figure 21-7. LIN interrupt enable register (LINIER) Table 21-7. LINIER field descriptions Field Description SZIE...
Page 499 Chapter 21 LIN Controller (LINFlex) Table 21-7. LINIER field descriptions (continued) Field Description WUIE Wake-up Interrupt Enable 0 No interrupt when WUF bit in LINSR or UARTSR is set. 1 Interrupt generated when WUF bit in LINSR or UARTSR is set. DBFIE Data Buffer Full Interrupt Enable 0 No interrupt when buffer data register is full.
Page 500 Chapter 21 LIN Controller (LINFlex) Table 21-8. LINSR field descriptions Field Description LINS LIN modes / normal mode states 0000: Sleep mode LINFlex is in Sleep mode to save power consumption. 0001: Initialization mode LINFlex is in Initialization mode. Normal mode states 0010: Idle This state is entered on several events: •...
Page 501 Chapter 21 LIN Controller (LINFlex) Table 21-8. LINSR field descriptions (continued) Field Description LIN receive pin state This bit reflects the current status of LINRX pin for diagnostic purposes. Wake-up Flag This bit is set by hardware and indicates to the software that LINFlex has detected a falling edge on the LINRX pin when: •...
Page 502 Chapter 21 LIN Controller (LINFlex) 21.7.1.4 LIN error status register (LINESR) Offset: 0x000C Access: User read/write Reset R SZF OCF BEF CEF SFEF BDEF IDPEF FEF BOF W w1c Reset Figure 21-9. LIN error status register (LINESR) Table 21-9. LINESR field descriptions Field Description Stuck at Zero Flag...
Page 503 Chapter 21 LIN Controller (LINFlex) Table 21-9. LINESR field descriptions (continued) Field Description Framing Error Flag This bit is set by hardware and indicates to the software that LINFlex has detected a framing error (invalid stop bit). This error can occur during reception of any data in the response field (Master or Slave mode) or during reception of Synch Field or Identifier Field in Slave mode.
Page 504 Chapter 21 LIN Controller (LINFlex) Table 21-10. UARTCR field descriptions (continued) Field Description RXEN Receiver Enable 0 Receiver disable. 1 Receiver enable. This bit can be programmed only when the UART bit is set. TXEN Transmitter Enable 0 Transmitter disable. 1 Transmitter enable.
Page 505 Chapter 21 LIN Controller (LINFlex) Table 21-11. UARTSR field descriptions Field Description Stuck at Zero Flag This bit is set by hardware when the bus is dominant for more than a 100-bit time. It is cleared by software. OCF Output Compare Flag 0 No output compare event occurred.
Page 506 Chapter 21 LIN Controller (LINFlex) Table 21-11. UARTSR field descriptions (continued) Field Description Data Reception Completed Flag This bit is set by hardware and indicates the data reception is completed, that is, the number of bytes programmed in RDFL[0:1] in UARTCR have been received. This bit must be cleared by software.
Page 507 Chapter 21 LIN Controller (LINFlex) Table 21-12. LINTCSR field descriptions (continued) Field Description TOCE Timeout counter enable 0 Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare event. 1 Timeout counter enable. OCF bit is set if an output compare event occurs. TOCE bit is configurable by software in Initialization mode.
Page 508 Chapter 21 LIN Controller (LINFlex) 21.7.1.9 LIN timeout control register (LINTOCR) Offset: 0x0020 Access: User read/write Reset Reset Figure 21-14. LIN timeout control register (LINTOCR) Table 21-14. LINTOCR field descriptions Field Description Response timeout value This field contains the response timeout duration (in bit time) for 1 byte. The reset value is 0xE = 14, corresponding to T = 1.4 ×...
Page 509 Chapter 21 LIN Controller (LINFlex) Table 21-15. LINFBRR field descriptions Field Description DIV_F Fraction bits of LFDIV The 4 fraction bits define the value of the fraction of the LINFlex divider (LFDIV). Fraction (LFDIV) = Decimal value of DIV_F / 16. This field can be written in Initialization mode only.
Page 510 Chapter 21 LIN Controller (LINFlex) 21.7.1.12 LIN checksum field register (LINCFR) Offset: 0x002C Access: User read/write Reset Reset Figure 21-17. LIN checksum field register (LINCFR) Table 21-18. LINCFR field descriptions Field Description Checksum bits When LINCR1[CCD] = 0, this field is read-only. When LINCR1[CCD] = 1, this field is read/write. Table 21-4.
Page 511 Chapter 21 LIN Controller (LINFlex) Table 21-19. LINCR2 field descriptions (continued) Field Description IOPE Idle on Identifier Parity Error 0 Identifier Parity error does not reset LIN state machine. 1 Identifier Parity error reset LIN state machine. This bit can be set/cleared in Initialization mode only. WURQ Wake-up Generation Request Setting this bit generates a wake-up pulse.
Page 512 Chapter 21 LIN Controller (LINFlex) Table 21-20. BIDR field descriptions Field Description Data Field Length This field defines the number of data bytes in the response part of the frame. DFL = Number of data bytes – 1. Normally, LIN uses only DFL[2:0] to manage frames with a maximum of 8 bytes of data. Identifier filters are compatible with DFL[2:0] only.
Page 513 Chapter 21 LIN Controller (LINFlex) Table 21-21. BDRL field descriptions (continued) Field Description DATA1 Data Byte 1 Data byte 1 of the data field. DATA0 Data Byte 0 Data byte 0 of the data field. 21.7.1.16 Buffer data register MSB (BDRM) Offset: 0x003C Access: User read/write DATA7...
Page 514 Chapter 21 LIN Controller (LINFlex) 21.7.1.17 Identifier filter enable register (IFER) Offset: 0x0040 Access: User read/write Reset FACT Reset Figure 21-22. Identifier filter enable register (IFER) Table 21-23. IFER field descriptions Field Description FACT Filter activation The software sets the bit FACT[x] to activate the filters x in identifier list mode. In identifier mask mode bits FACT(2n + 1) have no effect on the corresponding filters as they act as masks for the Identifiers 2n.
Page 515 Chapter 21 LIN Controller (LINFlex) Table 21-24. IFMI field descriptions Field Description 0:26 Reserved IFMI[0:4] Filter match index 27:31 This register contains the index corresponding to the received identifier. It can be used to directly write or read the data in SRAM (see Section 21.8.2.2, Slave mode for more details).
Page 516 Chapter 21 LIN Controller (LINFlex) Table 21-26. IFMR[IFM] configuration (continued) Value Result IFM[4] Filters 8 and 9 are in identifier list mode. Filters 8 and 9 are in mask mode (filter 9 is the mask for the filter 8). IFM[5] Filters 10 and 11 are in identifier list mode.
Page 517 Chapter 21 LIN Controller (LINFlex) Table 21-27. IFCR2n field descriptions (continued) Field Description Classic Checksum This bit controls the type of checksum applied on the current message. 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher.
Page 518 Chapter 21 LIN Controller (LINFlex) Table 21-28. IFCR2n + 1 field descriptions (continued) Field Description Identifier Identifier part of the identifier field without the identifier parity MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 519 Chapter 21 LIN Controller (LINFlex) 21.8 Functional description 21.8.1 UART mode The main features in the UART mode are • Full duplex communication • 8- or 9-bit data with parity • 4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management 8-bit data frames: The 8th bit can be a data or a parity bit.
Page 520 Chapter 21 LIN Controller (LINFlex) Table 21-29. Message buffer Buffer data LIN mode UART mode register BDRL[0:31] Transmit/Receive DATA0[0:7] Transmit buffer buffer DATA1[0:7] DATA2[0:7] DATA3[0:7] BDRM[0:31] DATA4[0:7] Receive buffer DATA5[0:7] DATA6[0:7] DATA7[0:7] 21.8.1.2 UART transmitter In order to start transmission in UART mode, you must program the UART bit and the transmitter enable (TXEN) bit in the UARTCR to 1.
Page 521 Chapter 21 LIN Controller (LINFlex) An interrupt is generated if the LINIER[BOIE] bit is set. 21.8.1.4 Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In UART mode, the LINFlex controller acknowledges a clock gating request once the data transmission and data reception are completed, that is, once the Transmit buffer is empty and the Receive buffer is full.
Page 522 Chapter 21 LIN Controller (LINFlex) set after the first 8 bytes have been transmitted. The application has to update the buffer BDR before resetting the DBEF bit. The transmission of the next bytes starts when the DBEF bit is reset. After the last data byte (or the checksum byte) has been sent, the DTF flag is set.
Page 523 Chapter 21 LIN Controller (LINFlex) 21.8.2.1.7 Overrun Once the messages buffer is full (LINSR[RMB] = 1) the next valid message reception leads to an overrun and message is lost. The hardware signals the overrun condition by setting the BOF bit in the LINESR. Which message is lost depends on the buffer lock function control bit RBLM.
Page 524 Chapter 21 LIN Controller (LINFlex) When the checksum reception is completed, an RX interrupt is generated to allow the software to read the received data in the BDR registers. One or several identifier filters can be configured for reception by programming IFCRx[DIR] = 0 and activated by setting one or several bits in the IFER.
Page 525 Chapter 21 LIN Controller (LINFlex) During header reception, a Break Delimiter error, an Inconsistent Synch Field or a Timeout error leads LINFlex to discard the header. An interrupt is generated if LINIER[HEIE] = 1. LINFlex returns to idle state. 21.8.2.2.6 Valid header A received header is considered as valid when it has been received correctly according to the LIN protocol.
Page 526 Chapter 21 LIN Controller (LINFlex) In mask mode, the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. For the bit mapping and registers organization, please see Figure 21-29.
Page 527 Chapter 21 LIN Controller (LINFlex) Table 21-30. Filter to interrupt vector correlation Number of Number of active filters Number of active filters Interrupt vector active filters configured as TX configured as RX — TX interrupt on identifiers (a > 0) matching the filters, —...
Page 528 Chapter 21 LIN Controller (LINFlex) LIN Synch Field measurement, the LINFlex state machine is stopped and no data is transferred to the data register. = Clock period periph_set_1_clk = 16.LFDIV.T = baud rate period periph_set_1_clk SM = Synch Measurement Register (19 bits) LIN Synch Field LIN Break Next...
Page 529 Chapter 21 LIN Controller (LINFlex) Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered by the check for deviation error on the full synch byte. 21.8.2.5 Clock gating The LINFlex clock can be gated from the Mode Entry module (MC_ME). In LIN mode, the LINFlex controller acknowledges a clock gating request once the frame transmission or reception is completed.
Page 530 Chapter 21 LIN Controller (LINFlex) 21.8.3.1.2 LIN Slave mode The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout value is fixed to HTO. OC1 checks T and T and OC2 checks T (see Figure 21-32).
Page 531 Chapter 21 LIN Controller (LINFlex) 21.8.4 Interrupts Table 21-31. LINFlex interrupt control Interrupt event Event flag bit Enable control bit Interrupt vector Header Received interrupt HRIE Data Transmitted interrupt DTIE Data Received interrupt DRIE Data Buffer Empty interrupt DBEF DBEIE Data Buffer Full interrupt DBFF DBFIE...
Page 532 Chapter 21 LIN Controller (LINFlex) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 533 Chapter 22 FlexCAN Chapter 22 FlexCAN 22.1 Introduction The FlexCAN module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. A general block diagram is shown in Figure 22-1, which describes the main subblocks implemented in the FlexCAN module, including two embedded memories, one for storing Message Buffers (MB) and another one for storing Rx Individual Mask Registers.
Page 534 Chapter 22 FlexCAN a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module is a full implementation of the CAN protocol specification, Version 2.0 B, which supports both standard and extended message frames. 32 Message Buffers are supported. The Message Buffers are stored in an embedded RAM dedicated to the FlexCAN module.
Page 535 Chapter 22 FlexCAN • Independent of the transmission medium (an external transceiver is assumed) • Short latency time due to an arbitration scheme for high-priority messages • Low power modes, with programmable wake up 22.1.3 Modes of operation The FlexCAN module has four functional modes: Normal mode (User and Supervisor), Freeze mode, Listen-Only Mode, and Loop-Back mode.
Page 536 Chapter 22 FlexCAN down globally. Exit from this mode happens when the Stop mode request is removed. See Section 22.4.9.3, “Stop mode for more information. 22.2 External signal description 22.2.1 Overview The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are summarized in Table 22-1 and described in more detail in the next subsections.
Page 537 Chapter 22 FlexCAN The Rx Global Mask (RXGMASK), Rx Buffer 14 Mask (RX14MASK) and the Rx Buffer 15 Mask (RX15MASK) registers are provided for backwards compatibility, and are not used when the BCC bit in the MCR is asserted. The address ranges 0x0060–0x027F and 0x0880–0x08FF are occupied by two separate embedded memories of RAM, of 544 bytes and 128 bytes, respectively.
Page 538 Chapter 22 FlexCAN Table 22-2. FlexCAN module memory map (continued) Offset from FlexCAN_BASE Register Location 0xFFFC_0000 0x08C0–0x08FF Rx Individual Mask Registers RXIMR16–RXIMR31 on page 559 0x0900–0x3FFF Reserved Table 22-3. FlexCAN register reset status Register Affected by hard reset Affected by soft reset Module Configuration Register (MCR) Control Register (CTRL) Free Running Timer (TIMER)
Page 539 Chapter 22 FlexCAN 22.3.2 Message buffer structure The Message Buffer structure used by the FlexCAN module is represented in Table 22-2. Both Extended and Standard Frames (29-bit Identifier and 11-bit Identifier, respectively) used in the CAN specification (Version 2.0 Part B) are represented. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CODE LENGTH...
Page 540 Chapter 22 FlexCAN Table 22-5. Message Buffer structure field description (continued) Field Description TIME STAMP Free-Running Counter Time Stamp This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. PRIO Local priority This 3-bit field is only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers.
Page 541 Chapter 22 FlexCAN Table 22-6. Message buffer code for Rx buffers (continued) Rx Code Rx Code BEFORE Description AFTER Comment Rx New Frame Rx New Frame 0XY1 BUSY: Flexcan is updating 0010 An EMPTY buffer was written with a new frame the contents of the MB.
Page 542 Chapter 22 FlexCAN Table 22-8. MB0–MB31 addresses (continued) Address Register Address Register Base + 0x00D0 Base + 0x01D0 MB21 Base + 0x00E0 Base + 0x01E0 MB22 Base + 0x00F0 Base + 0x01F0 MB23 Base + 0x0100 Base + 0x0200 MB24 Base + 0x0110 Base + 0x0210 MB25...
Page 543 Chapter 22 FlexCAN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LENGTH TIME STAMP ID (Standard/Extended) ID (Extended) Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5...
Page 544 Chapter 22 FlexCAN Table 22-10. Rx FIFO Structure field description Field Description Remote Frame This bit specifies if Remote Frames are accepted into the FIFO if they match the target ID. 0 Remote Frames are rejected and data frames can be accepted. 1 Remote Frames can be accepted and data frames are rejected.
Page 545 Chapter 22 FlexCAN Table 22-11. MCR field descriptions Field Description Module Disable MDIS This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the clocks to the CAN Protocol Interface and Message Buffer Management submodules. This is the only bit in MCR not affected by soft reset.
Page 546 Chapter 22 FlexCAN Table 22-11. MCR field descriptions (continued) Field Description Soft Reset SOFT_RST When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers. The following registers are reset: MCR (except the MDIS bit), TIMER, ECR, ESR, IMASK1, IFLAG1.
Page 547 Chapter 22 FlexCAN Table 22-11. MCR field descriptions (continued) Field Description Low Power Mode Acknowledge LPM_ACK This read-only bit indicates that FlexCAN is either in Disable Mode or Stop Mode. Either of these low power modes can not be entered until all current transmission or reception processes have finished, so the CPU can poll the LPM_ACK bit to know when FlexCAN has actually entered low power mode.
Page 548 Chapter 22 FlexCAN Table 22-11. MCR field descriptions (continued) Field Description 22–23 ID Acceptance Mode IDAM This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown in Table 22-12. Note that all elements of the table are configured at the same time by this field (they are all the same format).
Page 549 Chapter 22 FlexCAN Table 22-13. CTRL field descriptions Field Description 0–7 Prescaler Division Factor PRESDIV This 8-bit field defines the ratio between the CPI clock frequency and the Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock frequency is equal to the CPI clock frequency.
Page 550 Chapter 22 FlexCAN Table 22-13. CTRL field descriptions (continued) Field Description Rx Warning Interrupt Mask RWRN_MSK This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register. This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is negated.
Page 551 Chapter 22 FlexCAN Table 22-13. CTRL field descriptions (continued) Field Description Listen-Only Mode This bit configures FlexCAN to operate in Listen Only Mode. In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN Error Passive mode [Ref. 1]. Only messages acknowledged by another CAN station will be received.
Page 552 Chapter 22 FlexCAN Table 22-14. TIMER field descriptions Field Description TIMER Holds the value for this timer. 22.3.4.4 Rx Global Mask register (RXGMASK) This register is provided for legacy support and for low cost MCUs that do not have the individual masking per Message Buffer feature.
Page 553 Chapter 22 FlexCAN register has the same structure as the Rx Global Mask Register. It must be programmed while the module is in Freeze Mode, and must not be modified when the module is transmitting or receiving frames. Address: Base + 0x0014 Access: User read/write MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 Reset...
Page 554 Chapter 22 FlexCAN Table 22-17. RX15MASK field description Field Description 0–31 Mask Bits MI31–MI0 For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits affect all bits programmed in the filter table (ID, IDE, RTR). 0 The corresponding bit in the filter is “don’t care.”...
Page 555 Chapter 22 FlexCAN in the Error and Status Register). After the transition to ‘Error Passive’ state, the Tx_Err_Counter does not increment anymore by acknowledge errors. Therefore the device never goes to the ‘Bus Off’ state. • If the Rx_Err_Counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver.
Page 556 Chapter 22 FlexCAN Table 22-18. Error and Status Register (ESR) field description Field Description Tx Warning Interrupt Flag TWRN_INT If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from 0 to 1, meaning that the Tx error counter reached 96. If the corresponding mask bit in the Control Register (TWRN_MSK) is set, an interrupt is generated to the CPU.
Page 557 Chapter 22 FlexCAN Table 22-18. Error and Status Register (ESR) field description (continued) Field Description TX Error Counter TX_WRN This bit indicates when repetitive errors are occurring during message transmission. 0 No such occurrence. 1 TX_Err_Counter  96. Rx Error Counter RX_WRN This bit indicates when repetitive errors are occurring during message reception.
Page 558 Chapter 22 FlexCAN Table 22-19. Fault confinement state Value Meaning Error Passive Bus Off 22.3.4.9 Interrupt Masks 1 Register (IMASK1) This register allows to enable or disable any number of a range of 32 Message Buffer Interrupts. It contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an interrupt after a successful transmission or reception (that is, when the corresponding IFLAG1 bit is set).
Page 559 Chapter 22 FlexCAN Address: Base + 0x0030 Access: User read/write R BUF Reset R BUF Reset Figure 22-13. Interrupt Flags 1 Register (IFLAG1) Table 22-21. IFLAG1 field descriptions Field Description 0–23 Buffer MB Interrupt BUF31I – BUF8I Each bit flags the respective FlexCAN Message Buffer (MB8 to MB31) interrupt. 0 No such occurrence.
Page 560 Chapter 22 FlexCAN The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the module is in Freeze Mode. Out of Freeze Mode, write accesses are blocked and read accesses will return “all zeros”.
Page 561 Chapter 22 FlexCAN Table 22-23. RXIMR0–RXIMR31 addresses (continued) Address Register Address Register Base + 0x08A0 RXIMR8 Base + 0x08E0 RXIMR24 Base + 0x08A4 RXIMR9 Base + 0x08E4 RXIMR25 Base + 0x08A8 RXIMR10 Base + 0x08E8 RXIMR26 Base + 0x08AC RXIMR11 Base + 0x08EC RXIMR27 Base + 0x08B0...
Page 562 Chapter 22 FlexCAN 22.4 Functional description 22.4.1 Overview The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and receiving CAN frames. The mailbox system is composed by a set of as many as 32 Message Buffers (MB) that store configuration and control data, time stamp, message ID and data (see Section 22.3.2, “Message buffer...
Page 563 Chapter 22 FlexCAN structure). When the Abort feature is enabled (AEN in MCR is asserted), after the Interrupt Flag is asserted for a MB configured as transmit buffer, the MB is blocked, therefore the CPU is not able to update it until the Interrupt Flag be negated by CPU.
Page 564 Chapter 22 FlexCAN 22.4.4 Receive process To be able to receive CAN frames into the mailbox MBs, the CPU must prepare one or more Message Buffers for reception by executing the following steps: 1. If the MB has a pending transmission, write an ABORT code (‘1001’) to the Code field of the Control and Status word to request an abortion of the transmission, then read back the Code field and the IFLAG register to check if the transmission was aborted (see Section 22.4.6.1,...
Page 565 Chapter 22 FlexCAN Note that the received ID field is always stored in the matching MB, thus the contents of the ID field in an MB may change if the match was due to masking. Note also that FlexCAN does receive frames transmitted by itself if there exists an Rx matching MB, provided the SRX_DIS bit in the MCR is not asserted.
Page 566 Chapter 22 FlexCAN of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching algorithm will find MB number 2 again, but it is not “free to receive”, so it will keep looking and find MB number 5 and store the message there.
Page 567 Chapter 22 FlexCAN In order to abort a transmission, the CPU must write a specific abort code (1001) to the Code field of the Control and Status word. When the abort mechanism is enabled, the active MBs configured as transmission must be aborted first and then they may be updated. If the abort code is written to an MB that is currently being transmitted, or to an MB that was already loaded into the SMB for transmission, the write operation is blocked and the MB is not deactivated, but the abort request is captured and kept pending until one of the following conditions are satisfied:...
Page 568 Chapter 22 FlexCAN • Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is deactivated during the matching process after it was scanned, then this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for another matching MB within the ones it has not scanned yet.
Page 569 Chapter 22 FlexCAN While the message is being moved-in from the SMB to the MB, the BUSY bit on the Code field is asserted. If the CPU reads the Control and Status word and finds out that the BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated.
Page 570 Chapter 22 FlexCAN mask registers as follows: element 6 is affected by RX14MASK, element 7 is affected by RX15MASK and the other elements (0 to 5) are affected by RXGMASK. 22.4.8 CAN protocol related features 22.4.8.1 Remote frames Remote frame is a special kind of frame. The user can program a MB to be a Request Remote Frame by writing the MB as Transmit with the RTR bit set to 1.
Page 571 Chapter 22 FlexCAN 22.4.8.4 Protocol timing Figure 22-15 shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface (CPI) sub-module. The clock source bit (CLK_SRC) in the CTRL Register defines whether the internal clock is connected to the output of a crystal oscillator (Oscillator Clock) or to the Peripheral Clock (generally from a PLL).
Page 572 Chapter 22 FlexCAN • Time Segment 1: This segment includes the Propagation Segment and the Phase Segment 1 of the CAN standard. It can be programmed by setting the PROPSEG and the PSEG1 fields of the CTRL Register so that their sum (plus 2) is in the range of 4 to 16 time quanta. •...
Page 573 Chapter 22 FlexCAN Table 22-25. CAN standard compliant bit time segment settings Resynchronization Time Segment 1 Time Segment 2 Jump Width 5 .. 12 1 .. 4 6 .. 13 1 .. 4 7 .. 14 1 .. 4 8 .. 15 1 ..
Page 574 Chapter 22 FlexCAN A direct consequence of the first requirement is that the minimum number of time quanta per CAN bit must be 8, so the oscillator clock frequency should be at least 8 times the CAN bit rate. The minimum frequency ratio specified in Table 22-26 can be achieved by choosing a high enough peripheral clock frequency when...
Page 575 Chapter 22 FlexCAN • Waits for all internal activities like arbitration, matching, move-in and move-out to finish • Ignores its Rx input pin and drives its Tx pin as recessive • Shuts down the clocks to the CPI and MBM sub-modules •...
Page 576 Chapter 22 FlexCAN flag, bit 5 becomes the Frames Available in FIFO flag and bits 4:0 are unused. See Section 22.3.4.10, “Interrupt Flags 1 Register (IFLAG1) for more information. A combined interrupt for all MBs is also generated by an OR of all the interrupt sources from MBs. This interrupt gets generated when any of the MBs generates an interrupt.
Page 577 Chapter 22 FlexCAN • MCU level soft reset, which resets some of the memory mapped registers synchronously (refer to Table 22-2 to see which registers are affected by soft reset) • SOFT_RST bit in MCR, which has the same effect as the MCU level soft reset Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains.
Page 578 Chapter 22 FlexCAN MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 579 Chapter 23 Analog-to-Digital Converter (ADC) Chapter 23 Analog-to-Digital Converter (ADC) 23.1 Overview 23.1.1 Device-specific features • 1 ADC unit • 10-bit resolution • 16 input channels — 15 channels on 100-pin LQFP; 11 channels on 64-pin LQFP — Channel 15 dedicated to the internal 1.2 V rail •...
Page 580 Chapter 23 Analog-to-Digital Converter (ADC) 23.1.2 Device-specific pin configuration features • Section 23.3.3, ADC sampling and conversion timing,” = (1/2) MC_PLL_CLK is true where the bit ADCLKSEL would be always 0 (default value), meaning that AD_clk is half of MC_PLL_CLK. A clock prescaler (1 or 2) can be configured. The AD_clk has the same frequency of MC_PLL_CLK or is half of MC_PLL_CLK, depending on the value of the bit ADCLKSEL.
Page 581 Chapter 23 Analog-to-Digital Converter (ADC) Analog watchdogs allow continuous hardware monitoring. 23.3 Functional description 23.3.1 Analog channel conversion Two conversion modes are available within the ADC: • Normal conversion • Injected conversion 23.3.1.1 Normal conversion This is the normal conversion that the user programs by configuring the normal conversion mask registers (NCMR).
Page 582 Chapter 23 Analog-to-Digital Converter (ADC) If the content of all the normal conversion mask registers is zero (that is, no channel is selected) the conversion operation is considered completed and the interrupt ECH (see interrupt controller chapter for further details) is immediately issued after the start of conversion. 23.3.1.3 Normal conversion operating modes Two operating modes are available for the normal conversion:...
Page 583 Chapter 23 Analog-to-Digital Converter (ADC) B starts followed by conversion of the channels D-E. This sequence repeats itself till the MCR[NSTART] bit is cleared by software. At the end of each conversion an End Of Conversion interrupt is issued (if enabled by the corresponding mask bit) and at the end of the conversion sequence an End Of Chain interrupt is issued (if enabled by the corresponding mask bit in the IMR register).
Page 584 Chapter 23 Analog-to-Digital Converter (ADC) If the content of all the injected conversion mask registers (JCMR) is zero (that is, no channel is selected) the JECH interrupt is immediately issued after the start of conversion. Once started, injected chain conversion cannot be interrupted by any other conversion type (it can, however, be aborted;...
Page 585 Chapter 23 Analog-to-Digital Converter (ADC) MC_PLL_CLK MC_PLL_CLK Clock ADCClk MC_PLL_CLK/2 Prescaler CTU trigger signal ADCLKSEL ACKO ADCLKSEL = ‘0’ ADCLKSEL = ‘0’ (clock stretched) MC_PLL_CLK MC_PLL_CLK ADCClk ADCClk CTU trigger signal CTU trigger signal Figure 23-4. Prescaler simplified block diagram The clock stretching is implemented if and only if ADCLKSEL = 0 (and clock is half of the MC_PLL_CLK).
Page 586 Chapter 23 Analog-to-Digital Converter (ADC) 0.5 cycles 2.5 cycles 10 cycles Sampling phase Successive approximation / evaluation phase Latching phase: The capacitors field input End of conversion switch is opened Note: Operating conditions — INPLATCH = 0, INPSAMP = 3, INPCMP = 1 and Fadc clk = 20 MHz Figure 23-5.
Page 587 Chapter 23 Analog-to-Digital Converter (ADC) Table 23-2. ADC sampling and conversion timing at 5 V / 3.3 V for ADC0 (continued) Clock eval conv conv INPSAMPLE Ndelay INPCMP INPLATCH sample sample (MHz) (s) (s) (s) 0.063 0.500 8.000 0.625 1.188 19.000 0.031 0.500 16.000...
Page 588 Chapter 23 Analog-to-Digital Converter (ADC) 23.3.5 Programmable analog watchdog 23.3.5.1 Introduction The analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in Figure 23-6) specified by an upper and a lower threshold value named THRH and THRL respectively.
Page 589 Chapter 23 Analog-to-Digital Converter (ADC) NOTE If the higher threshold for the analog watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the WDGxL interrupt for the low threshold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher threshold) then the interrupt WDGxH for high threshold violation is set.
Page 590 Chapter 23 Analog-to-Digital Converter (ADC) • EOC (end of conversion) interrupt request • ECH (end of chain) interrupt request • JEOC (end of injected conversion) interrupt request • JECH (end of injected chain) interrupt request • EOCTU (end of CTU conversion) interrupt request •...
Page 591 Chapter 23 Analog-to-Digital Converter (ADC) 23.3.9 Auto-clock-off mode To reduce power consumption during the IDLE mode of operation (without going into power-down mode), an “auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit. When enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversion is programmed by the user.
Page 592 Chapter 23 Analog-to-Digital Converter (ADC) Table 23-6. ADC digital registers Offset from base address Register name Location 0xFFE0_0000 0x0060 Threshold Register 0 (THRHLR0) on page 603 0x0064 Threshold Register 1 (THRHLR1) on page 603 0x0068 Threshold Register 2 (THRHLR2) on page 603 0x006C Threshold Register 3 (THRHLR3) on page 603...
Page 593 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.2 Control logic registers 23.4.2.1 Main Configuration Register (MCR) The Main Configuration Register (MCR) provides configuration settings for the ADC. Address: Base + 0x0000 Access: User read/write Reset Reset Figure 23-7. Main Configuration Register (MCR) Table 23-7.
Page 594 Chapter 23 Analog-to-Digital Converter (ADC) Table 23-7. MCR field descriptions (continued) Field Description JSTART Injection start Setting this bit will start the configured injected analog channels to be converted by software. Resetting this bit has no effect, as the injected chain conversion cannot be interrupted. CTUEN Cross trigger unit conversion enable 0 CTU triggered conversion disabled...
Page 595 Chapter 23 Analog-to-Digital Converter (ADC) Address: Base + 0x0004 Access: User read-only Reset CHADDR ACK0 ADCSTATUS Reset Figure 23-8. Main Status Register (MSR) Table 23-8. MSR field descriptions Field Description NSTART This status bit is used to signal that a Normal conversion is ongoing. JABORT This status bit is used to signal that an Injected conversion has been aborted.
Page 596 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.3 Interrupt registers 23.4.3.1 Interrupt Status Register (ISR) The Interrupt Status Register (ISR) contains interrupt status bits for the ADC. Address: Base + 0x0010 Access: User read/write Reset JEOC JECH EOC ECH Reset Figure 23-9. Interrupt Status Register (ISR) Table 23-9.
Page 597 Chapter 23 Analog-to-Digital Converter (ADC) Address: Base + 0x0020 Access: User read/write Reset Reset Figure 23-10. Interrupt Mask Register (IMR) Table 23-10. IMR field descriptions Field Description MSKEOCTU Mask for end of CTU conversion (EOCTU) interrupt When set, the EOCTU interrupt is enabled. MSKJEOC Mask for end of injected channel conversion (JEOC) interrupt When set, the JEOC interrupt is enabled.
Page 598 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.3.3 Watchdog Threshold Interrupt Status Register (WTISR) Address: Base + 0x0024 Access: User read/write Reset R CIM Reset Figure 23-11. Channel Interrupt Mask Register 0 (CIMR0) Address: Base + 0x0030 Access: User read/write Reset Reset Figure 23-12.
Page 599 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR) Address: Base + 0x0034 Access: User read/write Reset Reset Figure 23-13. Watchdog Threshold Interrupt Mask Register (WTIMR) Table 23-12. WTIMR field descriptions Field Description MSKWDGxH This corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold (for [x = 0..3]).
Page 600 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.4 DMA registers 23.4.4.1 DMA Enable (DMAE) register The DMA Enable (DMAE) register sets up the DMA for use with the ADC. Address: Base + 0x0040 Access: User read/write Reset Reset Figure 23-14. DMA Enable (DMAE) register Table 23-13.
Page 601 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.4.2 DMA Channel Select Register (DMAR[0]) DMAR0 = Enable bits for channel 0 to 15 (precision channels) Address: Base + 0x0044 Access: User read/write Reset R DMA Reset Figure 23-15. DMA Channel Select Register 0 (DMAR0) Table 23-14.
Page 602 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.5 Threshold registers 23.4.5.1 Introduction The Threshold registers store the user programmable lower and upper thresholds’ values. The inverter bit and the mask bit for mask the interrupt are stored in the TRC registers. 23.4.5.2 Threshold Control Register (TRCx, x = [0..3]) Address: Base + 0x0050 (TRC0) Base + 0x0054 (TRC1)
Page 603 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.5.3 Threshold Register (THRHLR[0:3]) The four THRHLRn registers store the user-programmable thresholds’ 10-bit values. Address: Base + 0x0060 (THRHLR0) Base + 0x0064 (THRHLR1) Base + 0x0068 (THRHLR2) Base + 0x006C (THRHLR3) Access: User read/write THRH Reset THRL Reset...
Page 604 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.6 Conversion Timing Registers CTR[0] CTR0 = associated to internal precision channels (from 0 to 15) Address: Base + 0x0094 (CTR0) Access: User read/write Reset OFFSHIFT INPCMP INPSAMP Reset Figure 23-18. Conversion Timing Registers CTR[0] Table 23-17.
Page 605 Chapter 23 Analog-to-Digital Converter (ADC) Address: Base + 0x00A4 Access: User read/write Reset CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Reset Figure 23-19. Normal Conversion Mask Register 0 (NCMR0) Table 23-18. NCMR field descriptions Field Description Sampling enable...
Page 606 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.7.3 Injected Conversion Mask Registers (JCMR[0]) JCMR0 = Enable bits of injected sampling for channel 0 to 15 (precision channels) Address: Base + 0x00B4 Access: User read/write Reset CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Reset Figure 23-20.
Page 607 Chapter 23 Analog-to-Digital Converter (ADC) 23.4.8 Delay registers 23.4.8.1 Power-Down Exit Delay Register (PDEDR) Address: Base + 0x00C8 Access: User read/write Reset PDED Reset Figure 23-21. Power-Down Exit Delay Register (PDEDR) Table 23-20. PDEDR field descriptions Field Description PDED Delay between the power-down bit reset and the start of conversion. The delay is to allow time for the ADC power supply to settle before commencing conversions.
Page 608 Chapter 23 Analog-to-Digital Converter (ADC) Address: See Table 23-6 Access: User read/write OVER RESULT Reset CDATA[0:9] (MCR[WLSIDE] = 0) Reset CDATA[0:9] (MCR[WLSIDE] = 1) Reset Figure 23-22. Channel Data Registers (CDR[0..26]) Table 23-21. CDR field descriptions Field Description VALID Used to notify when the data is valid (a new value has been written). It is automatically cleared when data is read.
Page 609 Chapter 24 Cross Triggering Unit (CTU) Chapter 24 Cross Triggering Unit (CTU) 24.1 Introduction In PWM driven systems it is important to schedule the acquisition of the state variables with respect to PWM cycle. State variables are obtained through the following peripherals: ADC, position counter (for example, quadrature decoder, resolver and sine-cos sensor) and PWM duty cycle decoder.
Page 610 Chapter 24 Cross Triggering Unit (CTU) CTU Clock (as PWM) Prescaler TRIGGER_0 PWM_REL ADC_CMD_0 PWM_ODD_x NEXT_CMD_0 FIFO_0 Trigger Scheduler PWM_EVEN_x Generator TRIGGER_1 Subunit Subunit ADC_CMD_1 NEXT_CMD_1 RPWM_x FIFO_1 ETIMER0_IN ETIMER0_TRG ETIMER1_TRG EXT_IN EXT_TRG Figure 24-1. Cross triggering unit diagram The CTU consists of two subunits: •...
Page 611 Chapter 24 Cross Triggering Unit (CTU) 24.3.2 Trigger generator subunit (TGS) The trigger generator subunit has the following two modes: • Triggered mode—Each event source for the incoming signals can generate as many as eight trigger event outputs. For the ADC, a commands list is entered by the CPU, and each event source can generate as many as eight commands or streams of commands.
Page 612 Chapter 24 Cross Triggering Unit (CTU) value written into the double-buffered register (TGSCRR), during the control cycle n – 1 and reloads all the double-buffered registers (such as Trigger Compare registers, TGSCR, TGSCRR itself). The triggers list registers consist of eight compare registers. Each triggers list register is associated with a comparator.
Page 613 Chapter 24 Cross Triggering Unit (CTU) CTU Clock (as PWM) TGS Counter Compare Register TGS Counter Comparator PWM_REL TGS Counter STOP Signal PWM_ODD_x Prescaler (1, 2, 3, 4) TGS Counter PWM_EVEN_x Event Signal TGS Counter Reload Register RPWM_x ETIMER0_IN Triggers Compare Registers EXT_IN Comparators (double-buffered)
Page 614 Chapter 24 Cross Triggering Unit (CTU) TGS Counter—Case 1 Value in TGSCCR TGS Counter Value in TGSCRR TGS Counter—Case 2 Value in TGSCCR TGS Counter Value in TGSCRR TGS Counter—Case 3 TGS Counter Value in TGSCRR Value in TGSCCR TGS Counter—Case 4 0x7FFF TGS Counter TGS Counter...
Page 615 Chapter 24 Cross Triggering Unit (CTU) When a trigger is linked to the ADC, an associated ADC command (or stream of commands) is generated. The ADC Commands List Control Register (CLCRx) sets the assignment to an ADC command or to a stream of commands.
Page 616 Chapter 24 Cross Triggering Unit (CTU) 24.4.1 ADC commands list The ADC can be controlled by the CPU (CPU Control Mode) and by the CTU (CTU Control Mode). The CTU can control the ADC by sending an ADC command only when the ADC is in CTU control mode. During the CTU control mode, the CPU is able to write to the ADC registers but it can not start a new conversion.
Page 617 Chapter 24 Cross Triggering Unit (CTU) CTU outputs and the ADC_0 inputs and it has no configuration registers. It is implemented to ensure software compatibility between MPC5602P and the 512 Kbyte memory family device, in fact it is able to virtualize ADC_1 on MPC5602P, so, for example, the user can write on MPC5602P a command to start a conversion on ADC_1 channels 0 and the CTU/ADC interface will translate this command into a command for ADC_0 channel 6.
Page 618 Chapter 24 Cross Triggering Unit (CTU) Table 24-1. ADC commands translation (continued) Input command Output command Single sampling ADC_1 Channel 11 Not valid - force EOC to CTU Single sampling ADC_1 Channel 12 Not valid - force EOC to CTU Single sampling ADC_1 Channel 13 Not valid - force EOC to CTU Single sampling ADC_1 Channel 14...
Page 619 Chapter 24 Cross Triggering Unit (CTU) If the MRS occurs while the user is updating some double-buffered registers, eg. some registers of the triggers list, the new triggers list will be a mix of the old triggers list and the new triggers list, because the user has not ended the update of the triggers list before the MRS occurrence.
Page 620 Chapter 24 Cross Triggering Unit (CTU) 24.6 Power safety mode To reduce power consumption two mechanisms are implemented: • MDIS bit in the CTUPCR • STOP mode 24.6.1 MDIS bit The MDIS bit in the CTUPCR is used for stopping the clock to all non memory mapped registers. 24.6.2 STOP mode To reduce consumption, it is also possible to enable a stop request from the Mode Entry module.
Page 621 Chapter 24 Cross Triggering Unit (CTU) • A trigger event occurs during the time when the actions of the previous trigger event are not completed (user ensures no trigger event occurs during another one is processed, but if user makes a mistake and a trigger event occurs when another one is processed, the incoming trigger event will be lost and an error occurs).
Page 622 Chapter 24 Cross Triggering Unit (CTU) The interrupt flags are shown in Table 24-2. Table 24-2. CTU interrupts Category Interrupt Interrupt function Managed MRS_I MRS Interrupt flag (IRQ193) individually T0_I Trigger 0 interrupt flag (IRQ194) T1_I Trigger 1 interrupt flag (IRQ195) T2_I Trigger 2 interrupt flag (IRQ196) T3_I...
Page 623 Chapter 24 Cross Triggering Unit (CTU) Table 24-2. CTU interrupts (continued) Category Interrupt Interrupt function ORed onto ERR_I MRS_RE Master Reload Signal Reload Error (IRQ207) SM_TO Trigger Overrun (more than 8 EV) in TGS Sequential Mode Invalid Command Error MRS_O Master Reload Signal Overrun TGS_OSM TGS Overrun in Sequential Mode...
Page 624 Chapter 24 Cross Triggering Unit (CTU) Table 24-3. CTU memory map (continued) Offset from CTU_BASE Register Location (0xFFE0_C000) 0x002E CLR2—Commands List Register 2 on page 636 0x0030 CLR3—Commands List Register 3 on page 636 0x0032 CLR4—Commands List Register 4 on page 636 0x0034 CLR5—Commands List Register 5 on page 636...
Page 625 Chapter 24 Cross Triggering Unit (CTU) Table 24-3. CTU memory map (continued) Offset from CTU_BASE Register Location (0xFFE0_C000) 0x0088 FR2 — FIFO Right aligned data register 2 on page 641 0x008C FR3 — FIFO Right aligned data register 3 on page 641 0x0080–0x009F Reserved 0x00A0...
Page 626 Chapter 24 Cross Triggering Unit (CTU) Table 24-4. TGS registers (continued) Offset from Double- Register Synchronization Reset value CTU_BASE buffered 0x0016 TGSCCR — TGS Counter Compare Register 0x0000 0x0018 TGSCRR — TGS Counter Reload Register 0x0000 Table 24-5. SU registers Offset from Double- Register...
Page 627 Chapter 24 Cross Triggering Unit (CTU) Table 24-7. FIFO registers (continued) Offset from Double- Register Synchronization Reset value CTU_BASE buffered 0x0088 FR2 — FIFO Right aligned data 2 — 0x0000_0000 0x008C FR3 — FIFO Right aligned data 3 — 0x0000_0000 0x00A0 FL0 —...
Page 628 Chapter 24 Cross Triggering Unit (CTU) Table 24-8. TGSISR field descriptions (continued) Field Description I12_RE Input 12 — PWM X[3] Rising edge Enable 0 Disabled 1 Enabled I11_FE Input 11 — PWM X[2] Falling edge Enable 0 Disabled 1 Enabled I11_RE Input 11 —...
Page 629 Chapter 24 Cross Triggering Unit (CTU) Table 24-8. TGSISR field descriptions (continued) Field Description I5_RE Input 5 — PWM OUT_TRIG 1 [0] Rising edge Enable 0 Disabled 1 Enabled I4_FE Input 4 — PWM OUT_TRIG 0 [3] Falling edge Enable 0 Disabled 1 Enabled I4_RE...
Page 630 Chapter 24 Cross Triggering Unit (CTU) Table 24-9. TGSCR field descriptions Field Description ET_TM This bit enables toggle mode for external triggers. PRES TGS and SU prescaler selection bits 00 1 01 2 10 3 11 4 MRS_SM Master Reload Selection in Sequential Mode (5 bits to select one of 32 inputs) TGS_M Trigger Generator Subunit Mode 0 Triggered Mode...
Page 631 Chapter 24 Cross Triggering Unit (CTU) 24.8.5 TGS Counter Reload Register (TGSCRR) Address: Base + 0x0018 Access: User read/write TGSCRV Reset Figure 24-13. TGS Counter Reload Register (TGSCRR) Table 24-12. TGSCRR field descriptions Field Description TGSCRV TGS Counter Reload Value 24.8.6 Commands list control register 1 (CLCR1) Address: Base + 0x001C...
Page 632 Chapter 24 Cross Triggering Unit (CTU) 24.8.7 Commands list control register 2 (CLCR2) Address: Base + 0x0020 Access: User read/write T7_INDEX T6_INDEX Reset T5_INDEX T4_INDEX Reset Figure 24-15. Commands list control register 2 (CLCR2) Table 24-14. CLCR2 field descriptions Field Description T7_INDEX Trigger 7 Commands List first command address...
Page 633 Chapter 24 Cross Triggering Unit (CTU) Table 24-15. THCR1 field descriptions (continued) Field Description T3_T1E Trigger 3 Timer 1 output enable 0 Disabled 1 Enabled T3_T0E Trigger 3 Timer 0 output enable 0 Disabled 1 Enabled T3_ADCE Trigger 3 ADC command output enable 0 Disabled 1 Enabled T2_E...
Page 634 Chapter 24 Cross Triggering Unit (CTU) Table 24-15. THCR1 field descriptions (continued) Field Description T0_ETE Trigger 0 External Trigger output enable 0 Disabled 1 Enabled T0_T1E Trigger 0 Timer 1 output enable 0 Disabled 1 Enabled T0_T0E Trigger 0 Timer 0 output enable 0 Disabled 1 Enabled T0_ADCE...
Page 635 Chapter 24 Cross Triggering Unit (CTU) Table 24-16. THCR2 field descriptions (continued) Field Description T7_ADCE Trigger 7 ADC command output enable 0 Disabled 1 Enabled T6_E Trigger 6 enable 0 Disabled 1 Enabled T6_ETE Trigger 6 External Trigger output enable 0 Disabled 1 Enabled T6_T1E...
Page 636 Chapter 24 Cross Triggering Unit (CTU) Table 24-16. THCR2 field descriptions (continued) Field Description T4_T0E Trigger 4 Timer 0 output enable 0 Disabled 1 Enabled T4_ADCE Trigger 4 ADC command output enable 0 Disabled 1 Enabled 24.8.10 Commands list register x (x = 1,...,24) (CLRx) Figure 24-18 Table 24-17 show the register configured for ADC command format in single conversion...
Page 637 Chapter 24 Cross Triggering Unit (CTU) Address: Base + 0x002C ... 0x005A Access: User read/write (See Table 24-3) FIFO CH_B CH_A Reset Figure 24-19. Commands list register x (x = 1,...,24) (CMS = 1) Table 24-18. CLRx (CMS = 1) field descriptions Field Description Command Interrupt Request bit...
Page 638 Chapter 24 Cross Triggering Unit (CTU) 24.8.12 FIFO control register (FCR) Address: Base + 0x0070 Access: User read/write Reset FULL FULL FULL FULL _EN3 _EN2 _EN1 _EN0 _EN3 _EN2 _EN1 _EN0 Reset Figure 24-21. FIFO control register (FCR) Table 24-20. FCR field descriptions Field Description OR_EN3...
Page 639 Chapter 24 Cross Triggering Unit (CTU) Table 24-20. FCR field descriptions (continued) Field Description OF_EN1 FIFO 1 threshold Overflow interrupt enable 0 Disabled 1 Enabled EMPTY_EN1 FIFO 1 Empty interrupt enable 0 Disabled 1 Enabled FULL_EN1 FIFO 1 Full interrupt enable 0 Disabled 1 Enabled OR_EN0...
Page 640 Chapter 24 Cross Triggering Unit (CTU) Table 24-21. FTH field descriptions (continued) Field Description FIFO 1 Threshold FIFO 0 Threshold 24.8.14 FIFO status register (FST) Address: Base + 0x007C Access: User read/write Reset R OR3 OF3 EMP3 FULL3 OR2 OF2 EMP2 FULL2 OR1 OF1 EMP1 FULL1 OR0 OF0 EMP0 FULL0 W r1c Reset Figure 24-23.
Page 641 Chapter 24 Cross Triggering Unit (CTU) Table 24-22. FST field descriptions (continued) Field Description FULL2 FIFO 2 Full interrupt flag 0 Interrupt has not occurred. 1 Interrupt has occurred. FIFO 1 Overrun interrupt flag A read of this bit clears it. 0 Interrupt has not occurred.
Page 642 Chapter 24 Cross Triggering Unit (CTU) Table 24-23. FRx field descriptions Field Description N_CH[4:0] Number of stored channel 0xxxx: Result comes from an ADC_1 channel 1xxxx: Result comes from an ADC_0 channel DATA Data of stored channel 24.8.16 FIFO signed Left aligned data x (x = 0,...,3) (FLx) Address: Base + 0x00A0,...,0x00AC Access: User read-only N_CH[4:0]...
Page 643 Chapter 24 Cross Triggering Unit (CTU) Table 24-25. CTUEFR field descriptions Field Description ET_OE External Trigger generation Overrun Error 0 Error has not occurred. 1 Error has occurred. T1_OE Timer 1 trigger generation Overrun Error 0 Error has not occurred. 1 Error has occurred.
Page 644 Chapter 24 Cross Triggering Unit (CTU) Table 24-26. CTUIFR field descriptions Field Description ADC_I ADC command interrupt flag 0 Interrupt has not occurred. 1 Interrupt has occurred. T7_I Trigger 7 interrupt flag 0 Interrupt has not occurred. 1 Interrupt has occurred. T6_I Trigger 6 interrupt flag 0 Interrupt has not occurred.
Page 645 Chapter 24 Cross Triggering Unit (CTU) Table 24-27. CTUIR field descriptions Field Description T7_IE Trigger 7 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T6_IE Trigger 6 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T5_IE Trigger 5 Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled T4_IE...
Page 646 Chapter 24 Cross Triggering Unit (CTU) Table 24-28. COTR field descriptions Field Description COTR Control ON-Time and Guard Time for external trigger MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 647 Chapter 24 Cross Triggering Unit (CTU) 24.8.21 Cross triggering unit control register (CTUCR) Address: Base + 0x00C8 Access: User read/write CRU_A TGSIS DC_R CTU_ R_RE ODIS Reset Figure 24-30. Cross triggering unit control register (CTUCR) Table 24-29. CTUCR field descriptions Field Description T7_SG...
Page 648 Chapter 24 Cross Triggering Unit (CTU) Table 24-29. CTUCR field descriptions (continued) Field Description General Reload Enable TGSISR_RE TGS Input Selection Register Reload Enable 24.8.22 Cross triggering unit digital filter (CTUDF) Address: Base + 0x00CA Access: User read/write Reset Figure 24-31. Cross triggering unit digital filter (CTUDF) Table 24-30.
Page 649 Chapter 25 FlexPWM Chapter 25 FlexPWM 25.1 Overview The pulse width modulator module (PWM) contains four PWM submodules, each of which capable of controlling a single half-bridge power stage and two fault input channels. This PWM is capable of controlling most motor types: AC induction motors (ACIM), Permanent Magnet AC motors (PMAC), both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper motors.
Page 650 Chapter 25 FlexPWM 25.3 Modes of operation Care must be exercised when using this module in certain device operating modes. Some motors (such 3-phase AC motors) require regular software updates for proper operation. Failure to do so could result in destroying the motor or inverter.
Page 651 Chapter 25 FlexPWM 25.4 Block diagrams 25.4.1 Module level EXT_SYNC EXT_FORCE PWMA0 PWMB0 Submodule 0 PWMX0 FAULT0–1 Fault Channel 0 PWMA1 PWMB1 Submodule 1 PWMX1 PWMA2 PWMB2 Submodule 2 PWMX2 PWMA3 PWMB3 Submodule 3 PWMX3 Figure 25-1. PWM block diagram MPC5602P Microcontroller Reference Manual, Rev.
Page 652 Chapter 25 FlexPWM 25.4.2 PWM submodule Figure 25-2. PWM submodule block diagram MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 653 Chapter 25 FlexPWM 25.5 External signal descriptions The PWM module has external pins named PWMA[n], PWMB[n], PWMX[n], FAULT[n], EXT_SYNC. The PWM module also has on-chip inputs called EXT_CLK, EXT_FORCE and on-chip outputs called OUT_TRIG[n]. 25.5.1 PWMA[n] and PWMB[n] — external PWM pair These pins are the output pins of the PWM channels.
Page 654 Chapter 25 FlexPWM 25.6 Memory map and registers 25.6.1 FlexPWM module memory map Table 25-2. FlexPWM memory map Offset from FlexPWM_BASE Register Access Reset value Location (0xFFE2_4000) 0x0000 CNT—Counter Register (Submodule 0) 0x0000 on page 657 0x0002 INIT—Initial Count Register (Submodule 0) 0x0000 on page 657 0x0004...
Page 655 Chapter 25 FlexPWM Table 25-2. FlexPWM memory map (continued) Offset from FlexPWM_BASE Register Access Reset value Location (0xFFE2_4000) 0x0060 VAL4—Value Register 4 (Submodule 1) 0x0000 on page 664 0x0062 VAL5—Value Register 5 (Submodule 1) 0x0000 on page 665 0x0064–0x0067 Reserved 0x0068 OCTRL—Output Control Register (Submodule 1) 0x0000...
Page 656 Chapter 25 FlexPWM Table 25-2. FlexPWM memory map (continued) Offset from FlexPWM_BASE Register Access Reset value Location (0xFFE2_4000) 0x00C8–0x00EF Reserved 0x00F0 CNT—Counter Register (Submodule 3) 0x0000 on page 657 0x00F2 INIT—Initial Count Register (Submodule 3) 0x0000 on page 657 0x00F4 CTRL2—Control 2 Register (Submodule 3) 0x0000 on page 658...
Page 657 Chapter 25 FlexPWM 25.6.2 Register descriptions The address of a register is the sum of a base address and an address offset. The base address is defined at the core level and the address offset is defined at the module level. There are a set of registers for each PWM submodule, for the configuration logic, and for each Fault channel.
Page 658 Chapter 25 FlexPWM NOTE The INIT register is buffered. The value written does not take effect until the LDOK bit is set and the next PWM load cycle begins. This register cannot be written when LDOK is set. Reading INIT reads the value in a buffer and not necessarily the value the PWM generator is currently using.
Page 659 Chapter 25 FlexPWM Table 25-3. CTRL2 field descriptions (continued) Field Description PWMA Initial Value PWMA_INIT This read/write bit determines the initial value for PWMA and the value to which it is forced when FORCE_INIT is asserted. PWMB Initial Value PWMB_INIT This read/write bit determines the initial value for PWMB and the value to which it is forced when FORCE_INIT is asserted.
Page 660 Chapter 25 FlexPWM Table 25-3. CTRL2 field descriptions (continued) Field Description Reload Source Select RELOAD_SEL This read/write bit determines the source of the RELOAD signal for this submodule. When this bit is set, the LDOK bit in submodule 0 should be used since the local LDOK bit will be ignored. 0 The local RELOAD signal is used to reload registers.
Page 661 Chapter 25 FlexPWM Table 25-4. CTRL1 field descriptions (continued) Field Description Full Cycle Reload FULL This read/write bit enables full-cycle reloads. A full cycle is defined by when the submodule counter matches the VAL1 register. Either the HALF or FULL bit must be set in order to move the buffered data into the registers used by the PWM generators.
Page 662 Chapter 25 FlexPWM Table 25-6. PWM prescaler PRSC PWM clock frequency /128 NOTE Reading the PRSCx bits reads the buffered values and not necessarily the values currently in effect. The PRSCx bits take effect at the beginning of the next PWM cycle and only when the load okay bit, LDOK, is set. This field cannot be written when LDOK is set.
Page 663 Chapter 25 FlexPWM 25.6.3.6 Value register 1 (VAL1) Address: Base + 0x000A (Submodule 0) Base + 0x005A (Submodule 1) Base + 0x00AA (Submodule 2) Base + 0x00FA (Submodule 3) Access: User read/write VAL1 Reset Figure 25-8. Value Register 1 (VAL1) The 16-bit signed value written to this register defines the modulo count value (maximum count) for the submodule counter.
Page 664 Chapter 25 FlexPWM 25.6.3.8 Value register 3 (VAL3) Address: Base + 0x000E (Submodule 0) Base + 0x005E (Submodule 1) Base + 0x00AE (Submodule 2) Base + 0x00FE (Submodule 3) Access: User read/write VAL3 Reset Figure 25-10. Value register 3 (VAL3) The 16-bit signed value in this register defines the count value to set PWMA low (Figure 25-2).
Page 665 Chapter 25 FlexPWM 25.6.3.10 Value register 5 (VAL5) Address: Base + 0x0012 (Submodule 0) Base + 0x0062 (Submodule 1) Base + 0x00B2 (Submodule 2) Base + 0x0102 (Submodule 3) Access: User read/write VAL5 Reset Figure 25-12. Value register 5 (VAL5) The 16-bit signed value in this register defines the count value to set PWMB low (Figure 25-2).
Page 666 Chapter 25 FlexPWM Table 25-7. OCTRL field descriptions (continued) Field Description PWMB Output Polarity POLB This bit inverts the PWMB output polarity. 0 PWMB output not inverted. A high level on the PWMB pin represents the “on” or “active” state. 1 PWMB output inverted.
Page 667 Chapter 25 FlexPWM Table 25-8. STS field descriptions Field Description Registers Updated Flag This read only flag is set when one of the INIT, VALx, or PRSC fields has been written resulting in non-coherent data in the set of double buffered registers. Clear RUF by a proper reload sequence consisting of a reload signal while LDOK = 1.
Page 668 Chapter 25 FlexPWM Table 25-9. INTEN field descriptions Field Description Reload Error Interrupt Enable REIE This read/write bit enables the reload error flag (REF) to generate CPU interrupt requests. Reset clears RIE. 0 REF CPU interrupt requests disabled. 1 REF CPU interrupt requests enabled. Reload Interrupt Enable This read/write bit enables the reload flag (RF) to generate CPU interrupt requests.
Page 669 Chapter 25 FlexPWM 25.6.3.15 Output Trigger Control register (TCTRL) Address: Base + 0x0020 (Submodule 0) Access: User read/write Base + 0x0070 (Submodule 1) Base + 0x00C0 (Submodule 2) Base + 0x0110 (Submodule 3) OUT_TRIG_EN[5:0] Reset Figure 25-17. Output Trigger Control register (TCTRL) Table 25-11.
Page 670 Chapter 25 FlexPWM 25.6.3.16 Fault Disable Mapping register (DISMAP) This register determines which PWM pins are disabled by the fault protection inputs, illustrated in Table 25-18 Section 25.8.12, “Fault protection. Reset sets all of the bits in the fault disable mapping register.
Page 671 Chapter 25 FlexPWM Address: Base + 0x0024 (Submodule 0) Base + 0x0074 (Submodule 1) Base + 0x00C4 (Submodule 2) Base + 0x0114 (Submodule 3) Access: User read/write DTCNT0 Reset Figure 25-19. Deadtime Count Register 0 (DTCNT0) Address: Base + 0x0026 (Submodule 0) Base + 0x0076 (Submodule 1) Base + 0x00C6 (Submodule 2) Base + 0x0116 (Submodule 3)
Page 672 Chapter 25 FlexPWM Table 25-13. OUTEN field descriptions Field Description PWMA Output Enables PWMA_EN[3:0] These bits enable the PWMA outputs of each submodule. 0 PWMA output disabled. 1 PWMA output enabled. 8:11 PWMB Output Enables PWMB_EN[3:0] These bits enable the PWMB outputs of each submodule. 0 PWMB output disabled.
Page 673 Chapter 25 FlexPWM Table 25-14. MASK field descriptions (continued) Field Description 8:11 PWMB Masks MASKB[3:0] These bits mask the PWMB outputs of each submodule forcing the output to logic 0 prior to consideration of the output polarity. 0 PWMB output normal. 1 PWMB output masked.
Page 674 Chapter 25 FlexPWM Table 25-15. SWCOUT field descriptions (continued) Field Description Software Controlled Output B_2 OUTB_2 This bit is only used when SELB for submodule 2 is set to 0b10. It allows software control of which signal is supplied to the deadtime generator of that submodule. 0 A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWMB.
Page 675 Chapter 25 FlexPWM Table 25-16. DTSRCSEL field descriptions Field Description PWMA_3 Control Select SELA_3 This field selects possible over-rides to the generated PWMA signal in submodule 3 that will be passed to the deadtime logic upon the occurrence of a “Force Out” event in that submodule. 00 Generated PWMA_3 signal is used by the deadtime logic.
Page 676 Chapter 25 FlexPWM Table 25-16. DTSRCSEL field descriptions (continued) Field Description 12:13 PWMA_0 Control Select SELA_0 This field selects possible over-rides to the generated PWMA signal in submodule 0 that will be passed to the deadtime logic upon the occurrence of a “Force Out” event in that submodule. 00 Generated PWMA_0 signal is used by the deadtime logic.
Page 677 Chapter 25 FlexPWM Table 25-17. MCTRL field descriptions Field Description Current Polarity IPOL[3:0] This buffered read/write bit selects between PWMA and PWMB as the source for the generation of the complementary PWM pair output. IPOL is ignored in independent mode. PWMB (Figure 25-2) generates complementary PWM pairs.
Page 678 Chapter 25 FlexPWM Table 25-18. FCTRL field descriptions Field Description Fault Level FLVL These read/write bits select the active logic level of the individual fault inputs. A reset clears FLVL. 0 A logic 0 on the fault input indicates a fault condition. 1 A logic 1 on the fault input indicates a fault condition.
Page 679 Chapter 25 FlexPWM Table 25-19. FSTS field descriptions Field Description Fault Test FTEST These read/write bits simulate a fault condition. Setting this bit will cause a simulated fault to be sent into all of the fault filters. The condition will propagate to the fault flags and possibly the PWM outputs depending on the DISMAP settings.
Page 680 Chapter 25 FlexPWM reduce the probability of noisy samples causing an incorrect transition to be recognized. The probability of an incorrect transition is defined as the probability of an incorrect sample raised to the FILT_CNT+3 power. The values of FILT_PER and FILT_CNT must also be traded off against the desire for minimal latency in recognizing input transitions.
Page 681 Chapter 25 FlexPWM 25.7 Functional description 25.7.1 Center-aligned PWMs Each submodule has its own timer that is capable of generating PWM signals on two output pins. The edges of each of these signals are controlled independently as shown in Figure 25-29.
Page 682 Chapter 25 FlexPWM course, center alignment between the signals is not restricted to symmetry around the zero count value, as any other number would also work. However, centering on zero provides the greatest range in signed mode and also simplifies the calculations. 25.7.2 Edge-aligned PWMs When the turn on edge for each pulse is specified to be the INIT value, then edge-aligned operation results,...
Page 683 Chapter 25 FlexPWM edges of different PWM signal, the signals will be phase shifted with respect to each other, as illustrated Figure 25-31. This results in certain advantages when applied to a power stage. For example, when operating a multi-phase inverter at a low modulation index, all of the PWM switching edges from the different phases occur at nearly the same time.
Page 684 Chapter 25 FlexPWM Top Left Submodule 0 Bottom Left Top Right Submodule 1 Bottom Right Left Side Right Side Transformer Figure 25-32. Phase-shifted PWMs applied to a transformer primary 25.7.4 Double switching PWMs Double switching PWM output is supported to aid in single shunt current measurement and three phase reconstruction.
Page 685 Chapter 25 FlexPWM VAL1 (0x0100) VAL3 VAL5 VAL0 (0x0000) VAL4 VAL2 INIT (0xFF00) PWMA PWMB DBLPWM Figure 25-33. Double switching output example 25.7.5 ADC triggering In cases where the timing of the ADC triggering is critical, it must be scheduled as a hardware event instead of software activated.
Page 686 Chapter 25 FlexPWM VAL1 (0x0100) VAL3 VAL5 VAL4 VAL2 INIT (0xFF00) Output Triggers Figure 25-34. Multiple output trigger generation in hardware Since each submodule has its own timer, it is possible for each submodule to run at a different frequency. One of the options possible with this PWM module is to have one or more submodules running at a lower frequency, but still synchronized to the timer in submodule 0.
Page 687 Chapter 25 FlexPWM Submodule 0 counter (PWM generation) Submodule1 counter VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 Output Triggers Figure 25-35. Multiple output triggers over several PWM cycles 25.7.6 Synchronous switching of multiple outputs Before the PWM signals are routed to the output pins, they are processed by a hardware block that permits all submodule outputs to be switched synchronously.
Page 688 Chapter 25 FlexPWM compare events (represented by the long vertical lines in the diagram) are scheduled based on the zero crossings of the back-EMF waveforms. The PWM module is configured via software ahead of time with the next state of the PWM pins in anticipation of the compare event. When it happens, the output compare of the timer drives the FORCE_OUT signal, which immediately changes the state of the PWM pins to the next commutation state with no software latency.
Page 689 Chapter 25 FlexPWM on-chip resource such as a Timer module and goes to all of the submodules. The AUX_CLK signal is broadcast from submodule 0 and can be selected as the clock source by other submodules so that the 8-bit prescaler and RUN bit from submodule 0 can control all of the submodules.
Page 690 Chapter 25 FlexPWM 25.8.3 Counter synchronization Referring to Figure 25-39, the 16-bit counter will count up until its output equals VAL1, which specifies the counter modulus value. The resulting compare causes a rising edge to occur on the Local Sync signal, which is one of four possible sources used to cause the 16-bit counter to be initialized with INIT.
Page 691 Chapter 25 FlexPWM FORCE_OUT signal is provided mainly for commutated applications. When PWM signals are commutated on an inverter controlling a brushless DC motor, it is necessary to restart the PWM cycle at the beginning of the commutation interval. This action effectively resynchronizes the PWM waveform to the commutation timing.
Page 692 Chapter 25 FlexPWM The generation of the Local Sync signal is performed exactly the same way as the other PWM signals in the submodule. While comparator 0 causes a rising edge of the Local Sync signal, comparator 1 generates a falling edge. Comparator 1 is also hardwired to the reload logic to generate the half cycle reload indicator. If VAL1 is controlling the modulus of the counter and VAL0 is half of the VAL1 register minus the INIT value, then the half cycle reload pulse will occur exactly half way through the timer count period and the Local Sync will have a 50% duty cycle.
Page 693 Chapter 25 FlexPWM signal from submodule 0, the Local Sync signal, the Master Sync signal from submodule 0, or the EXT_FORCE signal from on or off chip depending on the device architecture. The local signals are used when the user wants to change the signals on the output pins of the submodule without regard for synchronization with other submodules.
Page 694 Chapter 25 FlexPWM 25.8.7 Independent or complementary channel operation Writing a logic one to the INDEP bit of the CNFG register configures the pair of PWM outputs as two independent PWM channels. Each PWM output is controlled by its own VALx pair operating independently of the other output.
Page 695 Chapter 25 FlexPWM 25.8.8 Deadtime insertion logic Figure 25-44 shows the deadtime insertion logic of each submodule, which creates non-overlapping complementary signals when not in independent mode. DTCNT0 PWMA INDEP from Force Out logic rising start down edge counter PWMA zero detect DBLPWM...
Page 696 Chapter 25 FlexPWM When deadtime is inserted in complementary PWM signals connected to an inverter driving an inductive load, the PWM waveform on the inverter output will have a different duty cycle than what appears on the output pins of the PWM module. This results in a distortion in the voltage applied to the load. A method of correcting this, adding to or subtracting from the PWM value used, is discussed next.
Page 697 Chapter 25 FlexPWM Desired load voltage Deadtime PWM to top transistor Positive current Negative current PWM to bottom transistor Positive current load voltage Negative current load voltage Figure 25-46. Deadtime distortion During deadtime, load inductance distorts output voltage by keeping current flowing through the diodes. This deadtime current flow creates a load voltage that varies with current direction.
Page 698 Chapter 25 FlexPWM • In center-aligned operation, decreasing or increasing the PWM value by a correction value equal to one-half the deadtime typically compensates for deadtime distortion. 25.8.10 Manual correction To detect the current status, the voltage on each PWMx pin is sampled twice in a PWM period, at the end of each deadtime.
Page 699 Chapter 25 FlexPWM Deadtime PWM to top transistor Positive current Negative current PWM to bottom transistor Load voltage with high positive current Load voltage with low positive current Load voltage with high negative current Load voltage with low negative current T = Deadtime interval before assertion of top PWM B = Deadtime interval before assertion of bottom PWM Figure 25-48.
Page 700 Chapter 25 FlexPWM PWMAFS[1] PWMA Disable PWMA_EN PWMAFS[0] PWMA output PWMA POLA from Deadtime logic POLB PWMB PWMB output PWMBFS[0] PWMB_EN PWMB Disable PWMBFS[1] Figure 25-49. Output logic section 25.8.12 Fault protection Fault protection can control any combination of PWM output pins. Faults are generated by a logic one on any of the FAULTx pins.
Page 701 Chapter 25 FlexPWM DISA1 DISA0 FAULT0 FAULT1 Disable Wait/Halt Mode PWMA WAITEN Debug Mode DBGEN Stop Mode Figure 25-50. Fault decoder for PWMA Table 25-21. Fault mapping PWM pin Controlling register bits PWMA DISA[1:0] PWMB DISB[1:0] PWMX DISX[1:0] 25.8.13 Fault pin filter Each fault pin has a programmable filter that can be bypassed.
Page 702 Chapter 25 FlexPWM 25.8.14 Automatic fault clearing Setting an automatic clearing mode bit, FAUTOx, configures faults from the FAULTx pin for automatic clearing. When FAUTOx is set, disabled PWM pins are enabled when the FAULTx pin returns to logic one and a new PWM either full or half cycle begins.
Page 703 Chapter 25 FlexPWM COUNT FFPINx BIT ENABLED OUTPUTS ENABLED DISABLED FFLAGx CLEARED Figure 25-52. Manual fault clearing (FSAFE = 0) COUNT FFPINx BIT ENABLED ENABLED DISABLED OUTPUTS FFLAGx CLEARED Figure 25-53. Manual fault clearing (FSAFE = 1) NOTE Fault protection also applies during software output control when the SELA and SELB fields are set to select OUTA and OUTB bits.
Page 704 Chapter 25 FlexPWM • The prescaler divisor—from the PRSC bits in the CTRL1 register • The PWM period and pulse width—from the INIT and VALx registers LDOK allows software to finish calculating all of these PWM parameters so they can be synchronously updated.
Page 705 Chapter 25 FlexPWM Counter Reload Change Every two to every four to every to every two Reload opportunities opportunities opportunity opportunities Frequency Figure 25-56. Full and half cycle reload frequency change 25.9.3 Reload flag At every reload opportunity the PWM Reload Flag (RF) in the CTRL1 register is set. Setting RF happens even if an actual reload is prevented by the LDOK bit.
Page 706 Chapter 25 FlexPWM NOTE Even if LDOK is not set, setting RUN also sets the RF flag. To prevent a CPU interrupt request, clear the RIE bit before setting RUN. The PWM generator uses the last values loaded if RUN is cleared and then set while LDOK equals zero. When the RUN bit is cleared: •...
Page 707 Chapter 25 FlexPWM Table 25-23. DMA summary DMA request DMA enable Name Description Submodule 0 write request VALDE_0 VALx write request VALx registers need to be updated Submodule 1 write request VALDE_1 VALx write request VALx registers need to be updated Submodule 2 write request VALDE_2 VALx write request...
Page 708 Chapter 25 FlexPWM MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 709 Chapter 26 eTimer Chapter 26 eTimer 26.1 Introduction The eTimer module contains six identical counter/timer channels and one watchdog timer function. Each 16-bit counter/timer channel contains a prescaler, a counter, a load register, a hold register, two queued capture registers, two compare registers, two compare preload registers, and four control registers. The Load register provides the initialization value to the counter when the counter’s terminal value has been reached.
Page 710 Chapter 26 eTimer • DMA support of capture registers and compare registers • 32-bit watchdog capability to detect stalled quadrature counting • OFLAG comparison for safety critical applications • Programmable operation during debug mode and stop mode • Programmable input filter •...
Page 711 Chapter 26 eTimer 26.3 Module block diagram The eTimer block diagram is shown in Figure 26-1. IPBus Clock Reset Count OFLAG 0 Inp 0 Channel 0 Filter Aux Inp 0 Filter OFLAG 1 Inp 1 Watchdog Filter Channel 1 Timer Aux Inp 1 Filter Inp 2...
Page 712 Chapter 26 eTimer 26.4 Channel block diagram Each of the timer/counter channels within the eTimer are shown in Figure 26-2. Peripheral Output Clock Prescaler OFLAG Control Output Disable WD Count Edge Switch Detect UP/DN Primary Matrix/ Input Input Polarity Filter Secondary Select Input...
Page 713 Chapter 26 eTimer Table 26-1. eTimer memory map Offset from eTIMER0_BASE Register Location (FFE1_8000) eTimer Channel 0 0x0000 COMP1—Compare Register 1 on page 716 0x0002 COMP2—Compare Register 2 on page 717 0x0004 CAPT1—Capture Register 1 on page 717 0x0006 CAPT2—Capture Register 2 on page 718 0x0008 LOAD—Load Register...
Page 714 Chapter 26 eTimer Table 26-1. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x003A CMPLD2—Comparator Load Register 2 on page 728 0x003C CCCTRL—Compare and Capture Control Register on page 728 0x003E FILT—Input Filter Register on page 730 eTimer Channel 2 0x0040 COMP1—Compare Register 1 on page 716...
Page 715 Chapter 26 eTimer Table 26-1. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x0074 STS—Status Register on page 725 0x0076 INTDMA—Interrupt and DMA Enable Register on page 726 0x0078 CMPLD1—Comparator Load Register 1 on page 727 0x007A CMPLD2—Comparator Load Register 2 on page 728 0x007C CCCTRL—Compare and Capture Control Register...
Page 716 Chapter 26 eTimer Table 26-1. eTimer memory map (continued) Offset from eTIMER0_BASE Register Location (FFE1_8000) 0x00AE CTRL1—Control Register 1 on page 720 0x00B0 CTRL2—Control Register 2 on page 722 0x00B2 CTRL3—Control Register 3 on page 724 0x00B4 STS—Status Register on page 725 0x00B6 INTDMA—Interrupt and DMA Enable Register on page 726...
Page 717 Chapter 26 eTimer Address: Base + 0x0000 (eTimer0) Base + 0x0060 (eTimer3) Access: User read/write Base + 0x0020 (eTimer1) Base + 0x0080 (eTimer4) Base + 0x0040 (eTimer2) Base + 0x00A0 (eTimer5) COMP1[15:0] Reset Figure 26-3. Compare register 1 (COMP1) Table 26-2. COMP1 field descriptions Field Description COMP1[15:0] Compare 1...
Page 718 Chapter 26 eTimer Address: Base + 0x0004 (eTimer0) Base + 0x0064 (eTimer3) Base + 0x0024 (eTimer1) Base + 0x0084 (eTimer4) Base + 0x0044 (eTimer2) Base + 0x00A4 (eTimer5) Access: User read-only CAPT1[15:0] Reset Figure 26-5. Capture register 1 (CAPT1) Table 26-4. CAPT1 field descriptions Field Description CAPT1[15:0]...
Page 719 Chapter 26 eTimer Address: Base + 0x0008 (eTimer0) Base + 0x0068 (eTimer3) Access: User read/write Base + 0x0028(eTimer1) Base + 0x0088 (eTimer4) Base + 0x0048 (eTimer2) Base + 0x00A8 (eTimer5) LOAD[15:0] Reset Figure 26-7. Load register (LOAD) Table 26-6. LOAD field descriptions Field Description LOAD[15:0]...
Page 720 Chapter 26 eTimer Address: Base + 0x000C (eTimer0) Base + 0x006C (eTimer3) Access: User read/write Base + 0x002C (eTimer1) Base + 0x008C (eTimer4) Base + 0x004C (eTimer2) Base + 0x00AC (eTimer5) CNTR[15:0] Reset Figure 26-9. Counter register (CNTR) Table 26-8. CNTR field descriptions Field Description CNTR[15:0]...
Page 721 Chapter 26 eTimer Table 26-9. CTRL1 field descriptions (continued) Field Description ONCE Count Once This bit selects continuous or one-shot counting mode. 0 Count repeatedly. 1 Count until compare and then stop. When output mode 0x4 is used, the counter reinitializes after reaching the COMP1 value and continues to count to the COMP2 value, then stops.
Page 722 Chapter 26 eTimer Table 26-10. Count source values (continued) Value Meaning Value Meaning 01001 Auxiliary input #1 pin 11001 IP Bus clock divide by 2 prescaler 01010 Auxiliary input #2 pin 11010 IP Bus clock divide by 4 prescaler 01011 Reserved 11011 IP Bus clock divide by 8 prescaler...
Page 723 Chapter 26 eTimer Table 26-11. CTRL2 field descriptions (continued) Field Description FORCE Force the OFLAG output This write only bit forces the current value of the VAL bit to be written to the OFLAG output. This bit always reads as a zero. The VAL and FORCE bits can be written simultaneously in a single write operation.
Page 724 Chapter 26 eTimer Table 26-11. CTRL2 field descriptions (continued) Field Description MSTR Master Mode This bit enables the compare function’s output to be broadcast to the other channels in the module. The compare signal then can be used to reinitialize the other counters and/or force their OFLAG signal outputs.
Page 725 Chapter 26 eTimer Table 26-12. CTRL3 field descriptions Field Description STPEN Stop Actions Enable This bit allows the tristating of the timer output during stop mode. 0 Output enable is unaffected by stop mode. 1 Output enable is disabled during stop mode. Reload on Capture These bits enable the capture function to cause the counter to be reloaded from the LOAD register.
Page 726 Chapter 26 eTimer Table 26-13. STS field descriptions (continued) Field Description ICF2 Input Capture 2 Flag This bit is set when an input capture event (as defined by CPT2MODE) occurs while the counter is enabled and the word count of the CAPT2 FIFO exceeds the value of the CFWM field. This bit is cleared by writing a 1 to this bit if ICF2DE is clear (no DMA) or it is cleared automatically by the DMA access if ICF2DE is set (DMA).
Page 727 Chapter 26 eTimer Table 26-14. INTDMA field descriptions Field Description ICF2DE Input Capture 2 Flag DMA Enable Setting this bit enables DMA read requests for CAPT2 when the ICF2 bit is set. Do not set both this bit and the ICF2IE bit. ICF1DE Input Capture 1 Flag DMA Enable Setting this bit enables DMA read requests for CAPT1 when the ICF1 bit is set.
Page 728 Chapter 26 eTimer Address: Base + 0x0018 (eTimer0) Base + 0x0078 (eTimer3) Access: User read/write Base + 0x0038 (eTimer1) Base + 0x0098 (eTimer4) Base + 0x0058 (eTimer2) Base + 0x00B8 (eTimer5) CMPLD1[15:0] Reset Figure 26-15. Comparator Load 1 (CMPLD1) Table 26-15. CMPLD1 field descriptions Field Description CMPLD1[15:0] Specifies the preload value for the COMP1 register.
Page 729 Chapter 26 eTimer Table 26-17. CCCTRL field descriptions Field Description CLC2 Compare Load Control 2 These bits control when COMP2 is preloaded. It also controls the loading of CNTR. 000 Never preload. 001 Reserved 010 Load COMP2 with CMPLD1 upon successful compare with the value in COMP1. 011 Load COMP2 with CMPLD1 upon successful compare with the value in COMP2.
Page 730 Chapter 26 eTimer Table 26-17. CCCTRL field descriptions (continued) Field Description ONESHOT One-Shot Capture Mode This bit selects between free-running and one-shot mode for the input capture circuitry. If both capture circuits are enabled, then capture circuit 1 is armed first after the ARM bit is set. Once a capture occurs, capture circuit 1 is disarmed and capture circuit 2 is armed.
Page 731 Chapter 26 eTimer 26.6.2.17 Input filter considerations The FILT_PER value should be set such that the sampling period is larger the period of the expected noise. This way a noise spike will only corrupt one sample. The FILT_CNT value should be chosen to reduce the probability of noisy samples causing an incorrect transition to be recognized.
Page 732 Chapter 26 eTimer 26.6.4 Configuration registers The base address of the configuration registers is equal to the base address of the eTimer plus an offset of 0x010C. 26.6.4.1 Channel Enable register (ENBL) Address: Base + 0x010C Access: User read/write ENBL Reset Figure 26-21.
Page 733 Chapter 26 eTimer Table 26-21. DREQn field descriptions Field Description DREQn_EN DMA Request Enable Use these bits to enable each of the four module level DMA request outputs. Program the DREQ fields prior to setting the corresponding enable bit. Clearing this enable bit will remove the request but wíll not clear the flag that is causing the request.
Page 734 Chapter 26 eTimer — The value that is loaded into the counter after reaching its terminal count is programmable. • The counter can count repeatedly, or it can stop after completing one count cycle. • The counter can be programmed to count to a programmed value and then immediately reinitialize, or it can count through the compare value until the count “rolls over”...
Page 735 Chapter 26 eTimer Section 26.7.2.9, “CASCADE-COUNT mode through Section 26.7.2.12, “VARIABLE-FREQUENCY PWM mode for additional capabilities of this operating mode. 26.7.2.3 EDGE-COUNT mode When the CNTMODE field is set to 010, the counter will count both edges of the selected external clock source.
Page 736 Chapter 26 eTimer Primary Secondary CNTR OFLAG COMP1 = 18 Figure 26-25. Triggered Count mode (length = 1) 26.7.2.8 ONE-SHOT mode When the CNTMODE field is set to 110 and the counter is set to reinitialize at a compare event (LENGTH = 1), and the OFLAG OUTMODE is set to 0101 (cleared on init, set on compare), the counter works in ONE-SHOT mode.
Page 737 Chapter 26 eTimer NOTE It is possible to connect counters together by using the other (non-cascade) counter modes and selecting the outputs of other counters as a clock source. In this case, the counters are operating in a “ripple” mode, where higher order counters will transition a clock later than a purely synchronous design.
Page 738 Chapter 26 eTimer frequency. This method of PWM generation has the advantage of allowing almost any desired PWM frequency and/or constant on or off periods. This mode of operation is often used to drive PWM amplifiers used to power motors and inverters. The CMPLD1 and CMPLD2 registers are especially useful for this mode, as they allow the programmer time to calculate values for the next PWM cycle while the PWM current cycle is underway.
Page 739 Chapter 26 eTimer counted past the new compare value by the time the compare register is updated by the interrupt service routine. The counter would then continue counting until it rolled over and reached the new compare value. To address this, the compare registers are updated in hardware in the same way the counter register is reinitialized to the value stored in the LOAD register.
Page 740 Chapter 26 eTimer negative, or both) is detected. The type of edge to be captured by each circuit is determined by the CPT1MODE and CPT2MODE bits whose functionality is shown in Figure 26-17. The arming logic controls the operation of the capture circuits to allow captures to be performed in a free-running (continuous) or one-shot fashion.
Page 741 Chapter 26 eTimer 26.9 Interrupts Each of the channels within the eTimer can generate an interrupt from several sources. The watchdog also generate interrupts. The interrupt service routine (ISR) must check the related interrupt enables and interrupt flags to determine the actual cause of the interrupt. Table 26-22.
Page 742 Chapter 26 eTimer MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 743 Chapter 27 Functional Safety Chapter 27 Functional Safety 27.1 Introduction This chapter describes the following modules that help add reliability to the MPC5602P. • Register protection module • Software watchdog timer (SWT) 27.2 Register protection module 27.2.1 Overview The register protection module offers a mechanism to protect defined memory-mapped address locations in a module under protection from being written.
Page 744 Chapter 27 Functional Safety • Restrict write accesses for the module under protection to supervisor mode only • Lock registers for first 6 KB of memory-mapped address space • Address mirror automatically sets corresponding lock bit • Once configured lock bits can be protected from changes 27.2.3 Modes of operation The register protection module is operable when the module under protection is operable.
Page 745 Chapter 27 Functional Safety Area 3 is 6 KB, starting at address 0x2000 and is a mirror of area 1. A read/write access to these 0x2000 + X addresses will read/write the register at address X. As a side effect, a write access to address 0x2000 + X will set the optional Soft Lock Bits for this address X in the same cycle as the register at address X is written.
Page 746 Chapter 27 Functional Safety 27.2.5.2 Registers description This section describes in address order all the register protection registers. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. 27.2.5.2.1 Module registers (MR0–6143) This is the lower 6 KB module memory space that holds all the functional registers of the module that is...
Page 747 Chapter 27 Functional Safety Table 27-3. Soft Lock Bits vs. Protected Address Soft Lock Bit Protected address SLBR0[SLB0] SLBR0[SLB1] SLBR0[SLB2] SLBR0[SLB3] SLBR1[SLB0] SLBR1[SLB1] SLBR1[SLB2] SLBR1[SLB3] SLBR2[SLB0] 27.2.5.2.4 Global Configuration Register (GCR) The Global Configuration Register (GCR) controls global configurations related to register protection. Address: Base + 0x3FFC Access: Read Always;...
Page 748 Chapter 27 Functional Safety NOTE The GCR[UAA] bit has no effect on the allowed access modes for the registers in the Register protection module. 27.2.6 Functional description 27.2.6.1 General This module provides a generic register (address) write-protection mechanism. The protection size can be: •...
Page 749 Chapter 27 Functional Safety to SLB3 write data to SLB3 write data to SLB0 to SLB1 to SLB2 to SLB0 to SLB1 to SLB2 SLBRn[WE[3:0]] SLBRn[WE[3:0]] change allowed change allowed SLB0 SLB1 SLB2 SLB3 SLB0 SLB1 SLB2 SLB3 SLBRn[SLB[3:0]] SLBRn[SLB[3:0]] Figure 27-5.
Page 750 Chapter 27 Functional Safety write data to SLB0 to SLB1 to SLB2 to SLB3 SLBRn[WE[3:0]] update lock bits SLB0 SLB1 SLB2 SLB3 SLBR[SLB[3:0]] Figure 27-7. Change lock settings for 32-bit protected addresses Figure 27-8 shows an example that has a mixed protection size configuration. write data to SLB0 to SLB1 to SLB2 to SLB3...
Page 751 Chapter 27 Functional Safety When writing to address 0x2008 the registers MR9 and MR8 in the protected module are updated. The corresponding lock bits SLBR2.SLB[1:0] are set while the lock bits SLBR2.SLB[3:2] remain unchanged (right part of Figure 27-6). Figure 27-10 shows an example where some addresses are protected and some are not.
Page 752 Chapter 27 Functional Safety 7. Any write operation in any access mode to area #3 while Hard Lock Bit GCR[HLB] is set 27.2.7 Reset The reset state of each individual bit is shown in Section 27.2.5.2, “Registers description. In summary, after reset, locking for all MRn registers is disabled.
Page 753 Chapter 27 Functional Safety the STP bit is set, the counter is stopped in stop mode, otherwise it continues to run. As soon as out of stop mode, SWT will continue from the state it was before entering this mode. Software watchdog is not available during stand-by.
Page 754 Chapter 27 Functional Safety 27.3.5.1 SWT Control Register (SWT_CR) The SWT_CR contains fields for configuring and controlling the SWT. The reset value of this register is device specific. Some devices can be configured to automatically clear the SWT_CR[WEN] bit during the boot process.
Page 755 Chapter 27 Functional Safety Table 27-6. SWT_CR field descriptions (continued) Field Description Soft Lock This bit is cleared by writing the unlock sequence to the service register. 0 SWT_CR, SWT_TO and SWT_WN are read/write registers if HLK = 0. 1 SWT_CR, SWT_TO and SWT_WN are read only registers. Clock Selection Selects the internal 16 MHz IRC oscillator clock that drives the internal timer.
Page 756 Chapter 27 Functional Safety 27.3.5.3 SWT Time-Out register (SWT_TO) The SWT Time-Out (SWT_TO) register contains the 32-bit time-out period. The reset value for this register is device specific. This register is read only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
Page 757 Chapter 27 Functional Safety Table 27-9. SWT_WN field descriptions Field Description Window start value When window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. 27.3.5.5 SWT Service Register (SWT_SR) The SWT Time-Out (SWT_SR) service register is the target for service sequence writes used to reset the watchdog timer.
Page 758 Chapter 27 Functional Safety Table 27-11. SWT_CO field descriptions Field Description Watchdog Count When the watchdog is disabled (SWT_CR.[WEN]=0) this field shows the value of the internal down counter. When the watchdog is enabled the value of this field is 0x0000_0000. Values in this field can lag behind the internal counter value for as many as 6 system plus 8 counter clock cycles.
Page 759 Chapter 27 Functional Safety The SWT_TO register holds the watchdog time-out period in clock cycles unless the value is less than 0x0100, in which case the time-out period is set to 0x0100. This time-out period is loaded into an internal 32-bit down counter when the SWT is enabled and a valid service sequence is written.
Page 760 Chapter 27 Functional Safety MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 761 Chapter 28 Fault Collection Unit (FCU) Chapter 28 Fault Collection Unit (FCU) 28.1 Introduction The Fault Collection Unit (FCU) module provides functional safety to the device. 28.1.1 Overview The FCU provides a central capability to collect faults reported by the individual modules of the device. It represents the minimum blocking unit to develop a coherent safety strategy for the chassis family.
Page 762 Chapter 28 Fault Collection Unit (FCU) Fault Collection Unit Destructive reset FCU[0] Functional reset Input Control Unit Output Fault sources (finite state machine) Unit Unit FCU[1] 32-bit Clock/Reset/Power/Mode state 4-bit SYS_CLK IRC_CLK IPBus Figure 28-1. Fault Collection Unit (FCU) block diagram Figure 28-2 shows the flow chart of FCU fault handling.
Page 763 Chapter 28 Fault Collection Unit (FCU) FCU detects a fault Fault is collected into FFR Fault enabled? FCU takes no action (FER) FCU goes into Fault Is Timeout state and communi- enabled for this fault? cates fault to the (FCTER) external pin.
Page 764 Chapter 28 Fault Collection Unit (FCU) 28.1.2 Features The FCU includes the following features: • Collection of critical faults • Reporting of selected critical faults to external pins • Fault flag status kept over non-destructive reset for later analysis (in a “Freeze” register) •...
Page 765 Chapter 28 Fault Collection Unit (FCU) 28.2.1 Memory map Table 28-1. FCU memory map Offset from FCU_BASE Register Location (0xFFE6_C000) 0x0000 Module Configuration Register (FCU_MCR) on page 767 0x0004 Fault Flag Register (FCU_FFR) on page 768 0x0008 Frozen Fault Flag Register (FCU_FFFR) on page 770 0x000C Fake Fault Generation Register (FCU_FFGR)
Page 766 Chapter 28 Fault Collection Unit (FCU) Table 28-2. Register summary (continued) Name 0x0000_000 FCU_FFFR R FSR 0x0000_000 FCU_FFGR R ESF 0x0000_001 R EHF FCU_FER 0x0000_001 FCU_KR TR[31:16] 0x0000_001 FCU_TR TR[15:0] R TES 0x0000_001 R TEH FCU_TER 0x0000_002 FCU_MSR MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 767 Chapter 28 Fault Collection Unit (FCU) Table 28-2. Register summary (continued) Name MCPS[3:0] 0x0000_002 MCAS[3:0] FCU_MCSR FRMCPS[3:0] 0x0000_002 FCU_FMCS FRMCAS[3:0] 28.2.3 Register descriptions 28.2.3.1 Module Configuration Register (FCU_MCR) The FCU_MCR does the following: • Locks the configuration and lets the FCU go into Normal behavior state •...
Page 768 Chapter 28 Fault Collection Unit (FCU) Table 28-3. FCU_MCR field description Field Description Module Configuration Lock 0: Configuration not locked, FCU remains in Init state 1: Configuration locked, FCU moves to Normal state Test Mode TM[1:0] 00: Test Mode not entered 01: Test Mode entered (fake faults can be generated), output pins disabled 10: Test Mode entered (fake faults can be generated), output pins enabled 11: Test Mode not entered...
Page 769 Chapter 28 Fault Collection Unit (FCU) Notice that software recoverable fault flags must be kept high also if the relative signal does not show anymore a fault. Hardware recoverable fault flags are updated in real time. Reset requests are assumed as hardware-recoverable.
Page 770 Chapter 28 Fault Collection Unit (FCU) Table 28-5. Hardware/software fault description (continued) Label Module Fault type HRF5 Not used HRF6 Not used HRF7 Flash Flash Fatal Error HRF8 SW Watchdog reset HRF9 JTAG JTAG reset (TAP controller) HRF10 Comparators HRF11 LVD 4.5 HRF12 LVD 2.7 VREG...
Page 771 Chapter 28 Fault Collection Unit (FCU) Table 28-6. FCU_FFFR field descriptions Field Description Software Recoverable Fault FRSRF0– 0: No error latched FRSRF4 1: Error latched 16:31 Hardware Recoverable Fault FRHRF15 0: No error latched – 1: Error latched FRHRF0 28.2.3.4 Fake Fault Generation Register (FCU_FFGR) The FCU_FFGR allows the user to emulate a software/hardware recoverable fault in order to test the FCU logic.
Page 772 Chapter 28 Fault Collection Unit (FCU) Address: Base + 0x0010 Access: User read/write, Supervisor read/write R ESF Reset R EHF Reset Figure 28-7. Fault Enable Register (FCU_FER) Table 28-8. FCU_FER field descriptions Field Description Enable Software Recoverable Fault ESF0– 0: FCU takes no action on Software recoverable Fault [0:4] ESF4 1: FCU goes into Alarm/Fault state on Software recoverable Fault [0:4] Note.
Page 773 Chapter 28 Fault Collection Unit (FCU) 28.2.3.7 Timeout Register (FCU_TR) Once the FCU goes into Alarm state, a fault can be recovered before the timeout elapses. This timeout should be long enough for hardware or software to recover from the fault. If the fault is not recovered before the timeout elapses, the FCU goes into Fault state.
Page 774 Chapter 28 Fault Collection Unit (FCU) Table 28-10. FCU_TER field descriptions Field Description Timeout Enable for Software Recoverable Fault TESF0– 0: FCU goes into Fault state on Software recoverable Fault[0:4] TESF4 1: FCU goes into Alarm state on Software recoverable Fault[0:4] Note.
Page 775 Chapter 28 Fault Collection Unit (FCU) Address: Base + 0x0024 Access: User read-only, Supervisor read-only MCPS[3:0] Reset MCAS[3:0] Reset Figure 28-12. MC State Register (FCU_MCSR) Table 28-12. FCU_MCSR field description Field Description 12:15 MC Previous State MCPS[3:0 0000: RESET 0001: TEST 0010: SAFE 0011: DRUN 0100: RUN0...
Page 776 Chapter 28 Fault Collection Unit (FCU) 28.2.3.11 Frozen MC State Register (FCU_FMCSR) The FCU_MCSR is copied into the FCU_FMCSR each time the Fault state is entered. The FCU_FMCSR bit description is the same as that of the FCU_MCSR. Address: Base + 0x0028 Access: User read-only, Supervisor read-only FRMCPS[3:0] Reset...
Page 777 Chapter 28 Fault Collection Unit (FCU) Table 28-13. FCU_FMCSR field description Field Description 28:31 MC Actual State FRMCAS 0000: RESET [3:0] 0001: TEST 0010: SAFE 0011: DRUN 0100: RUN0 0101: RUN1 0110: RUN2 0111: RUN3 1000: HALT0 1001: Reserved 1010: STOP 1011: Reserved 1100: Reserved 1101: Reserved...
Page 778 Chapter 28 Fault Collection Unit (FCU) The register block implements all the FCU registers including input capture logic. The interface implements the read functionality and generated write and register enable signals. The timeout counter implements the counter to calculate timeout to switch from Alarm state to Fault state. The output prescaler module generates the prescaled clock to be used to generate output sequence.
Page 779 Chapter 28 Fault Collection Unit (FCU) After a functional reset, the FCU_FFR (not the Frozen Fault Flag Register (FCU_FFFR)) must be cleared and the FCU must return to Normal state. 28.3.2 Output generation protocol The FCU provides two external output signals. The FCU supports different protocols for fault indication to the external device.
Page 780 Chapter 28 Fault Collection Unit (FCU) Reset Configuration phase Normal behavior Error occurred Reset is asserted FCU[0] FCU[1] During configuration phase fake faults can be injected so outputs may be different Figure 28-16. Dual rail coding example 28.3.2.2 Time switching protocol FCU[0] is toggled between logic 0 and logic 1 with a defined frequency f = 1 kHz @ 64 MHz (f is approximated, as shown by Equation...
Page 781 Chapter 28 Fault Collection Unit (FCU) Reset Configuration phase Normal behavior Error occurred Reset is asserted FCU[0] During configuration phase fake faults can be injected so output may be different Figure 28-17. Time switching protocol example 28.3.2.3 Bi-Stable protocol In this protocol during the Init and the Fault state, faulty state is indicated. In the Normal/Alarm state, non-faulty state is indicated.
Page 782 Chapter 28 Fault Collection Unit (FCU) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 783 Chapter 29 Wakeup Unit (WKPU) Chapter 29 Wakeup Unit (WKPU) 29.1 Overview The Wakeup Unit (WKPU) supports one external source that causes non-maskable interrupt requests. 29.2 Features The WKPU provides non-maskable interrupt support with these features: • 1 NMI source •...
Page 784 Chapter 29 Wakeup Unit (WKPU) Table 29-1. WKPU memory map (continued) Offset from WKPU_BASE Register Location (0xC3F9_4000) 0x0008 NCR—NMI Configuration Register on page 784 0x000C–0x3FFF Reserved 29.4.2 Registers description This section describes the Wakeup Unit registers. 29.4.2.1 NMI Status Flag Register (NSR) This register holds the non-maskable interrupt status flags.
Page 785 Chapter 29 Wakeup Unit (WKPU) Address: Base + 0x0008 Access: User read/write NDSS Reset Reset Figure 29-2. NMI Configuration Register (NCR) Table 29-3. NCR field descriptions Field Description NMI Configuration Lock Register NLOCK Writing a 1 to this bit locks the configuration for the NMI until it is unlocked by a system reset. Writing a 0 has no effect.
Page 786 Chapter 29 Wakeup Unit (WKPU) 29.5.2 Non-Maskable Interrupts The Wakeup Unit supports one non-maskable interrupt, which is allocated to pin 1. The Wakeup Unit supports the generation of three types of interrupts from the NMI input to the device. The Wakeup Unit supports the capturing of a second event per NMI input before the interrupt is cleared, thus reducing the chance of losing an NMI event.
Page 787 Chapter 29 Wakeup Unit (WKPU) to recognize interrupts with an active rising edge, an active falling edge or both edges being active. A setting of having both edge events disabled results in no interrupt being detected and should not be configured.
Page 788 Chapter 29 Wakeup Unit (WKPU) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 789 Chapter 30 Periodic Interrupt Timer (PIT) Chapter 30 Periodic Interrupt Timer (PIT) 30.1 Introduction The Periodic Interrupt Timer (PIT) block implements several timers that can be used for DMA triggering, general purpose interrupts and system wakeup. Figure 30-1 shows the PIT block diagram. load_value Timer 0 timeout...
Page 790 Chapter 30 Periodic Interrupt Timer (PIT) • Timers can generate DMA trigger pulses to initiate DMA transfers with other peripherals (ex: initiate a SPI message transfer sequence) • Timers can generate interrupts • All interrupts are maskable • Independent timeout periods for each timer 30.2 Signal description The PIT module has no external pins.
Page 791 Chapter 30 Periodic Interrupt Timer (PIT) Table 30-1. PIT memory map (continued) Offset from PIT_BASE Register Location (0xC3FF_0000) Timer Channel 3 0x0130 LDVAL3—Timer 3 Load Value Register on page 792 0x0134 CVAL3—Timer 3 Current Value Register on page 792 0x0138 TCTRL3—Timer 3 Control Register on page 793 0x013C...
Page 792 Chapter 30 Periodic Interrupt Timer (PIT) Table 30-2. PITMCR field descriptions Field Description MDIS Module Disable Used to disable the module clock. This bit should be enabled before any other setup is done. 0: Clock for PIT Timers is enabled 1: Clock for PIT Timers is disabled (default) Freeze Allows the timers to be stopped when the device enters debug mode.
Page 793 Chapter 30 Periodic Interrupt Timer (PIT) Address: Channel Base + 0x0004 Access: User read-only CVAL0 = PIT_BASE + 0x0104 CVAL1 = PIT_BASE + 0x0114 CVAL2 = PIT_BASE + 0x0124 CVAL3 = PIT_BASE + 0x0134 R TVL31 TVL30 TVL29 TVL28 TVL27 TVL26 TVL25 TVL24 TVL23 TVL22 TVL21 TVL20 TVL19 TVL18 TVL17 TVL16 Reset R TVL15 TVL14 TVL13 TVL12 TVL11 TVL10 TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0 Reset...
Page 794 Chapter 30 Periodic Interrupt Timer (PIT) Table 30-5. TCTRLn field descriptions Field Description Timer Interrupt Enable Bit 0: Interrupt requests from Timer x are disabled 1: Interrupt will be requested whenever TIF is set When an interrupt is pending (TIF set), enabling the interrupt will immediately cause an interrupt event.
Page 795 Chapter 30 Periodic Interrupt Timer (PIT) 30.4.1.1 Timers The timers generate triggers at periodic intervals, when enabled. They load their start values, as specified in their LDVAL registers, then count down until they reach 0. Then they load their respective start value again.
Page 796 Chapter 30 Periodic Interrupt Timer (PIT) Timer Enabled New Start Start Value = p1 Value p2 set Trigger Event Figure 30-9. Dynamically setting a new load value 30.4.1.2 Debug mode In Debug mode, the timers are frozen. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system (e.g., timer values) and then continue the operation.
Page 797 Chapter 30 Periodic Interrupt Timer (PIT) Timer 3 shall be used only for triggering. Therefore Timer 3 is started by writing a 1 to bit TEN in the TCTRL3 register, bit TIE stays at 0. The following example code matches the described setup: // turn on PIT PIT_CTRL = 0x00;...
Page 798 Chapter 30 Periodic Interrupt Timer (PIT) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 799 Chapter 31 System Timer Module (STM) Chapter 31 System Timer Module (STM) 31.1 Overview The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel.
Page 800 Chapter 31 System Timer Module (STM) Table 31-1. STM memory map Offset from STM_BASE Register Location 0xFFF3_C000 0x0000 STM_CR—STM Control Register on page 800 0x0004 STM_CNT—STM Counter Value on page 801 0x0008–0x000F Reserved 0x0010 STM_CCR0—STM Channel 0 Control Register on page 802 0x0014 STM_CIR0—STM Channel 0 Interrupt Register on page 802...
Page 801 Chapter 31 System Timer Module (STM) Address: Base + 0x0000 Access: User read/write Reset CPS[7:0] FRZ TEN Reset Figure 31-1. STM Control Register (STM_CR) Table 31-2. STM_CR field descriptions Field Description CPS[7:0] Counter Prescaler Selects the clock divide value for the prescaler (1 - 256). 0x00 Divide system clock by 1.
Page 802 Chapter 31 System Timer Module (STM) Table 31-3. STM_CNT field descriptions Field Description Timer count value used as the time base for all channels. When enabled, the counter increments at the rate of the system clock divided by the prescale value. 31.5.2.3 STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) enables and services channel n of the timer.
Page 803 Chapter 31 System Timer Module (STM) Table 31-5. STM_CIRn field descriptions Field Description Channel Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect. 0 No interrupt request. 1 Interrupt request due to a match on the channel. 31.5.2.5 STM Channel Compare Register (STM_CMPn) The STM Channel Compare Register (STM_CMPn) holds the compare value for channel n.
Page 804 Chapter 31 System Timer Module (STM) 31.6 Functional description The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel.
Page 805 Chapter 32 Cyclic Redundancy Check (CRC) Chapter 32 Cyclic Redundancy Check (CRC) 32.1 Introduction The Cyclic Redundancy Check (CRC) computing unit is dedicated to the computation of CRC, thus off-loading the CPU. The MPC5602P CRC supports two contexts. Each context has a separate CRC computation engine in order to allow the concurrent computation of the CRC of multiple data streams.
Page 806 Chapter 32 Cyclic Redundancy Check (CRC) Config and Data Registers Engine Engine context 1 context 1 context 2 context 2 Figure 32-1. CRC top level diagram 32.3.1 IPS bus interface The IPS bus interface is a slave bus used for configuration and data streaming (CRC computation) purposes via CPU or DMA.
Page 807 Chapter 32 Cyclic Redundancy Check (CRC) Two standard generator polynomials are given in Equation 32-1 Equation 32-2 for the CRC computation of each context. CRC-16-CCITT (x25 protocol) Eqn. 32-1 CRC-32 (ethernet protocol) Eqn. 32-2 Serial data input (LSB first) Figure 32-2. CRC-CCITT engine concept scheme The initial seed value of the CRC can be programmed initializing the CRC_CSTAT register.
Page 808 Chapter 32 Cyclic Redundancy Check (CRC) context = n context = 1 START CRC configuration (polynomial, swap, inversion) setting the CRC_CFG register CRC seed initialization (CRC_CSTAT register) Data is written in the CRC_INP register (byte/half word/word) by CPU or DMA All the data has been passed to the CRC unit...
Page 809 Chapter 32 Cyclic Redundancy Check (CRC) Table 32-1. CRC memory map (continued) Offset from CRC_BASE Register Location 0xFFE6_8000 0x0014 CRC_INP—CRC Input Register, Context 2 on page 810 0x0018 CRC_CSTAT—CRC Current Status Register, Context 2 on page 810 0x001C CRC_OUTP—CRC Output Register, Context 2 on page 811 0x0020–0x3FFF Reserved...
Page 810 Chapter 32 Cyclic Redundancy Check (CRC) 32.5.2 CRC Input Register (CRC_INP) Address: Context 1: Base + 0x0004 Access: User read/write Context 2: Base + 0x0014 Reset Reset Figure 32-5. CRC Input Register (CRC_INP) Table 32-3. CRC_INP field descriptions Field Description 0:31 INP: Input data for the CRC computation The INP register can be written at byte, half-word (high and low) or word in any sequence.
Page 811 Chapter 32 Cyclic Redundancy Check (CRC) Table 32-4. CRC_CSTAT field descriptions Field Description 0:31 CSTAT: Status of the CRC signature The CSTAT register includes the current status of the CRC signature. No bit swap and inversion are applied to this register. In case of CRC-CCITT polynomial only the16 LSB bits are significant.
Page 812 Chapter 32 Cyclic Redundancy Check (CRC) contexts) configurable for the following type of data transfer: mem2mem, periph2mem, mem2periph, the following sequence, as given in Figure 32-8, shall be applied to manage the transmission data flow: • DMA/CRC module configuration (context x, channel x) by CPU •...
Page 813 Chapter 32 Cyclic Redundancy Check (CRC) Transmission Phase 1 Memory CRC (context x) Payload CRC_INP (mem2mem CRC_OUTP channel x) Transmission Phase 2 Memory CRC (context x) CRC_INP Payload CRC_OUTP CRC Checksum Transmission Phase 3 Memory Tx FIFO Payload (mem2periph CRC Checksum channel x) Figure 32-8.
Page 814 Chapter 32 Cyclic Redundancy Check (CRC) • Data block (payload + CRC) transfer from the PERIPH (e.g., SPI Rx fifo) module to the MEM (phase 1) by DMA (periph2mem data transfer, channel x) • Data block transfer (payload + CRC) transfer from the MEM to the CRC module (CRC_INP register) to calculate the CRC signature (phase 2) by DMA (mem2mem data transfer, channel x) •...
Page 815 Chapter 32 Cyclic Redundancy Check (CRC) Reception Phase 1 Memory Rx FIFO Payload (periph2mem CRC Checksum channel x) Received Data Reception Phase 2 Memory CRC (context x) CRC_INP Payload CRC_OUTP CRC Checksum (mem2mem channel x) Reception Phase 3 CRC (context x) CRC_INP CRC_OUTP Software Check...
Page 816 Chapter 32 Cyclic Redundancy Check (CRC) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 817 Chapter 33 Boot Assist Module (BAM) Chapter 33 Boot Assist Module (BAM) 33.1 Overview The Boot Assist Module is a block of read-only memory containing VLE code that is executed according to the boot mode of the device. The BAM allows downloading boot code via the FlexCAN or LINFlex interfaces into internal SRAM and then executing it.
Page 818 Chapter 33 Boot Assist Module (BAM) 33.5 Functional description 33.5.1 Entering boot modes The MPC5602P detects the boot mode based on external pins and device status. The following sequence applies (see Figure 33-1): • To boot either from FlexCAN or LINFlex, the device must be forced into an Alternate Boot Loader Mode via the FAB (Force Alternate Boot Mode), which must be asserted before initiating the reset sequence.
Page 819 Chapter 33 Boot Assist Module (BAM) • PAD A[2] - ABS[0], • PAD A[3] - ABS[1], • PAD A[4] - FAB Table 33-2. Hardware configuration to select boot mode Standby-RAM ABS[1:0] Boot ID Boot Mode Boot Flag — LINFlex without autobaud —...
Page 820 Chapter 33 Boot Assist Module (BAM) 33.5.3 Reset Configuration Half Word (RCHW) The MPC5602P Flash is partitioned into boot sectors as shown in Table 33-5. Each boot sector contains the Reset Configuration Half-Word (RCHW) at offset 0x00. Address: Base + 0x0000 Access: User read-only BOOT_ID[0:7] Reset...
Page 821 Chapter 33 Boot Assist Module (BAM) 128K 0x0002 0000 Boot information 0x0001 8000 Boot information 0x0001 0000 0x0000 C000 Boot information Application 0x0000 000C Application 0x0000 8000 Boot information 0x0000 0008 Application start address 0x0000 0004 RCHW 0x0000 0000 Boot information 0x0000 0000 Internal Flash Figure 33-3.
Page 822 Chapter 33 Boot Assist Module (BAM) If a valid RCHW is not found, the BAM code is executed. In this case BAM moves the MPC5602P into static mode. 33.5.4.1 Boot and alternate boot Some applications require an alternate boot sector in the flash so that the main sector in flash can be erased and reprogrammed in the field.
Page 823 Chapter 33 Boot Assist Module (BAM) 33.5.5.2 BAM software flow Figure 33-4 illustrates the BAM logic flow. BAM entry 0xFFFF_C000 Save default configuration The selected boot mode is verified by reading the SSCM_STATUS register (bits BMODE and ABD) Check boot mode Restore Boot mode default...
Page 824 Chapter 33 Boot Assist Module (BAM) Table 33-6. Fields of SSCM STATUS register used by BAM Field Description BMODE Device Boot Mode [2:0] 000 Test Flash/autobaud_scan 001 CAN Serial Boot Loader 010 SCI Serial Boot Loader 011 Single Chip 100–111Reserved This field is updated only during reset.
Page 825 Chapter 33 Boot Assist Module (BAM) Table 33-7. Serial boot mode without autobaud—baud rates Crystal frequency LINFlex baud rate FlexCAN bit rate (MHz) (baud) (bit/s) 19200 400 K 24000 500 K 48000 33.5.5.4 Download and execute the new code From a high level perspective, the download protocol follows these steps: 1.
Page 826 Chapter 33 Boot Assist Module (BAM) In case of flash with public access, the received password is compared with the public password 0xFEED_FACE_CAFE_BEEF. If public access is not allowed but the flash is not secured, the received password is compared with the value saved on NVPWD0 and NVPWD1 registers.
Page 827 Chapter 33 Boot Assist Module (BAM) SSCM. Comparison with STATUS. FEEDFACE CAFEBEEF SSCM. Comparison with STATUS. password saved on NVPWD[0:1] Write received password to SSCM.PWCMPH-L Wait Verify whether Flash is unsecured Figure 33-5. Password check flow 33.5.5.6 Download start address, VLE bit and code size The next 8 bytes received by the MCU contain a 32-bit Start Address, the VLE mode bit and a 31-bit code Length as shown in Figure...
Page 828 Chapter 33 Boot Assist Module (BAM) START_ADDRESS[31:16] START_ADDRESS[15:0] CODE_LENGTH[30:16] CODE_LENGTH[15:0] Figure 33-6. Start address, VLE bit and download size in bytes 33.5.5.7 Download data Each byte of data received is stored into device’s SRAM, starting from the address specified in the previous protocol step.
Page 829 Chapter 33 Boot Assist Module (BAM) Byte Field Start Stop Figure 33-7. LINFlex bit timing in UART mode 33.5.6.2 UART boot mode download protocol Table 33-8 summarizes the download protocol and BAM action during the UART boot mode. Table 33-8. UART boot mode download protocol (autobaud disabled) Protoco Host sent BAM response...
Page 830 Chapter 33 Boot Assist Module (BAM) NRZ Signal SYNC_SEG Time Segment 1 Time Segment 2 time quanta time quanta time quanta 1 Bit Time Sample Point Transmit Point 1 time Quanta = 4 system clock periods Figure 33-8. FlexCAN bit timing 33.6 FlexCAN boot mode download protocol Table 33-9...
Page 831 Chapter 33 Boot Assist Module (BAM) 33.6.1.1 Configuration MPC5602P devices implement the autobaud feature via FlexCAN or LINFlex selecting the active serial communication peripheral by means of an autoscan routine. When autobaud configuration is selected by ABS and FAB pins, the autoscan routine starts and listens to the active bus protocol.
Page 832 Chapter 33 Boot Assist Module (BAM) After setting up the system clock, the BAM autoscan code configures the FlexCAN RX pin (B[1] on all packages) and LINFlex RX pin (B[3] on LQFP100 or B[7] on LQFP64) as GPIO inputs and searches for FlexCAN RX pin level to verify if CAN is connected or not.
Page 833 Chapter 33 Boot Assist Module (BAM) Figure 33-9. BAM Autoscan code flow Both RDX pins have to be at high level. FlexCAN RX and LINFlex RX configured as GPIO inputs Avoid to connect them to external pull-down resistor. If CAN is connected, after reset CAN_RX has to be FlexCAN RX at high level == 1...
Page 834 Chapter 33 Boot Assist Module (BAM) Initially the UART RX pin is configured as GPIO input and it waits in polling for the first falling edge, then STM starts. UART RX pin waits again for the first rising. Then STM stops and from its measurement baud rate is computed.
Page 835 Chapter 33 Boot Assist Module (BAM) 33.6.1.2.1 Choosing the host baud rate The calculation of the UART baud rate from the length of the first 0 byte that is received, allows the operation of the boot loader with a wide range of baud rates. However, to ensure proper data transfer, the upper and lower limits have to be kept.
Page 836 Chapter 33 Boot Assist Module (BAM) Table 33-11. Maximum and minimum recommended baud rates Max baud rate for guaranteed Min baud rate for guaranteed (MHz) xtal < 2.5% deviation < 2.5% deviation 13.4 Kbit/s 30 bit/s (SBR = 19) (SBR = 8192) 26.9 Kbit/s 60 bit/s (SBR = 19)
Page 837 Chapter 33 Boot Assist Module (BAM) 33.6.1.3 Boot from FlexCAN with autobaud enabled The only difference between booting from FlexCAN with autobaud enabled and booting from FlexCAN with autobaud disabled is that the following initialization FlexCAN frame is sent for baud measurement purposes from the host to the MCU when autobaud is enabled: •...
Page 838 Chapter 33 Boot Assist Module (BAM) Start CAN_0_RX pin configured as If CAN is connected, GPIO input CAN_RX should be at high level CAN_RX == 1 ERROR CAN_RX == 0 Start STM Wait for the first recessive (HIGH) bit CAN_RX == 1 Read STM.
Page 839 Chapter 33 Boot Assist Module (BAM) 33.6.1.3.1 Choosing the host baud rate The calculation of the FlexCAN baud rate allows the operation of the boot loader with a wide range of baud rates. However, to ensure proper data transfer, the upper and lower limits have to be kept. Pins are measured until reception of the 5th recessive bit.
Page 840 Chapter 33 Boot Assist Module (BAM) Table 33-13. FlexCAN standard compliant bit timing segment settings Time Segment 1 Time Segment 2 5..10 1..2 4..11 1..3 5..12 1..4 6..13 1..4 7..14 1..4 8..15 1..4 9..16 1..4 Timing segment 2 is kept as large as possible to keep sample time within bit time. Table 33-14.
Page 841 Chapter 33 Boot Assist Module (BAM) Table 33-16. PRESDIV + 1 > 1 (YY = PRESDIV) Desired number of time quanta Register contents for CANA_CR 0xYY49_2002 0xYY49_2003 0xYY49_2004 0xYY49_2005 0xYY49_2006 0xYY49_2007 0xYY52_2007 0xYY52_2008 0xYY5B_2008 0xYY5B_2009 0xYY64_2009 0xYY64_200A 0xYY6D_200A 0xYY6D_200B 0xYY76_200B 0xYY76_200C 0xYY7F_200C 0xYY7F_200D...
Page 842 Chapter 33 Boot Assist Module (BAM) Example 33-6. 20 MHz crystal Consider case where using a 20 MHz crystal, user attempts to send 62.5 Kb/s FlexCAN message. — Time base, clocking at crystal frequency, would measure: — 62.5 Kb/s = 320 clocks/bit => 29 * 320 = 9280 clocks —...
Page 843 Chapter 33 Boot Assist Module (BAM) • NVPWD1 = 0xCAFE_BEEF This means that even if censorship was inadvertently enabled by writing to the censorship control registers, there is an opportunity to get back into the microcontroller using the default private password of 0xFEED_FACE_CAFE_BEEF.
Page 844 Chapter 33 Boot Assist Module (BAM) CAUTION (NVSCI0 and NVSCI1 do not match) (Either NVSCI0 or NVSCI1 is not set to 0x55AA) then the microcontroller will be permanently censored with no way to get back in. Table 33-18 shows all the possible modes of censorship. The red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out.
Page 845 Chapter 33 Boot Assist Module (BAM) Table 33-18. Censorship configuration and truth table Boot configuration Serial Internal Censorship censorship flash Nexus Serial JTAG control word FAB pin control word memory state password password Control options (NVSCIn[CW]) state (NVSCIn[SC]) state 0 (flash Uncensored 0xXXXX AND 0x55AA AND...
Page 846 Chapter 33 Boot Assist Module (BAM) FAB = 0 (Flash boot mode) Censored with no True NVSCI0 != password access NVSCI1 (Locked out) False Both Censored with no True SC and CW != password access 0x55AA (Locked out) False JTAG password details: Censored with True Enter password as...
Page 847 Chapter 33 Boot Assist Module (BAM) FAB = 1 (Serial boot mode) Censored with no True NVSCI0 != password access NVSCI1 (Locked out) False Both Censored with no True SC and CW != password access 0x55AA (Locked out) False Serial password details: True Public password, Enter public password...
Page 848 Chapter 33 Boot Assist Module (BAM) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 849 Chapter 34 Voltage Regulators and Power Supplies Chapter 34 Voltage Regulators and Power Supplies 34.1 Voltage regulator The power blocks are used for providing 1.2 V digital supply to the internal logic of the device. The main/input supply is 3.3 V to 5.0 V ±10% and the digital/regulated output supply has a trim target voltage of 1.28 V.
Page 850 Chapter 34 Voltage Regulators and Power Supplies The LVD_MAIN and LVD_MAIN5 detectors sense the V supply and provide DDIO and V as active high signals at 3.3 V and IOLVDMOK_H IOLVDM5OK_H IOLVDMOK_L IOLVDM5OK_L 1.2 V supply levels, respectively. Two more LVD_MAIN detectors are also used for sensing VDDREG and VDDFLASH. An LVD_DIG in the regulator senses the HPREG output.
Page 851 Chapter 34 Voltage Regulators and Power Supplies 34.1.4 Registers Description 34.1.4.1 Voltage Regulator Control Register (VREG_CTL) Address: Base + 0x0080 Access: User read/write Reset 5V_LVD _MASK Reset Figure 34-1. Voltage Regulator Control register (VREG_CTL) Table 34-1. VREG_CTL field descriptions Field Description 5V_LVD_MASK Mask bit for 5 V LVD from regulator...
Page 852 Chapter 34 Voltage Regulators and Power Supplies 34.1.4.2 Voltage Regulator Status register (VREG_STATUS) Address: Base + 0x0084 Access: User read-only Reset 5V_LVD_ STATUS Reset Figure 34-2. Voltage Regulator Status register (VREG_STATUS) Table 34-2. VREG_STATUS field descriptions Field Description 5V_LVD_STATUS Status bit for 5 V LVD from regulator 0 5 V LVD not OK 1 5 V LVD OK 34.2...
Page 853 Chapter 34 Voltage Regulators and Power Supplies • LV_CORn—Low voltage supply for the core. It is also used to provide supply for PLL and Flsah memory through double bonding. MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 854 Chapter 34 Voltage Regulators and Power Supplies MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 855 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.1 Introduction The JTAG port of the device consists of three inputs and one output. These pins include test data input (TDI), test mode select (TMS), test clock input (TCK) and test data output (TDO). TDI, TMS, TCK and TDO are compliant with the IEEE 1149.1-2001 standard and are shared with the NDI through the test access port (TAP) interface.
Page 856 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.4 Features The JTAGC is compliant with the IEEE 1149.1-2001 standard, and supports the following features: • IEEE 1149.1-2001 Test Access Port (TAP) interface • Four pins (TDI, TMS, TCK, and TDO)—see Section 35.6, “External signal description.
Page 857 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.5.2.1 Bypass mode When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass mode. While in bypass mode, the single-bit bypass shift register provides a minimum-length serial path to shift data between TDI and TDO.
Page 858 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.7.1 Instruction register The JTAGC uses a 5-bit instruction register as shown in Figure 35-2. The instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both.
Page 859 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 35-2. Device identification register field descriptions Field Description 0–3 Part revision number. Contains the revision number of the device. This field changes with each revision of the device or module. 4–9 Design center.
Page 860 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.8.3 TAP controller state machine The TAP controller is a synchronous state machine that interprets the sequence of logical values on the TMS pin. Figure 35-5 shows the machine’s states. The value shown next to each state is the value of the TMS signal sampled on the rising edge of the TCK signal.
Page 861 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) Test logic reset Select-DR-scan Run-test/idle Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-IR Exit2-DR Update-DR Update-IR NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK.
Page 862 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.8.3.1 Selecting an IEEE 1149.1-2001 register Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded in the update-IR state.
Page 863 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 35-3. JTAG instructions (continued) Instruction Code[4:0] Instruction summary Factory Debug Reserved 00101 Intended for factory debug only 00110 01010 Reserved All Other Decoded to select bypass register Codes Intended for factory debug, and not customer use. Freescale reserves the right to change the decoding of reserved instruction codes.
Page 864 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.8.4.5 HIGHZ instruction HIGHZ selects the bypass register as the shift path between TDI and TDO. While HIGHZ is active, all output drivers are placed in an inactive drive state (for example, high impedance). HIGHZ also asserts the internal system reset for the MCU to force a predictable internal state.
Page 865 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.9 e200z0 OnCE controller The e200z0 core OnCE controller supports a complete set of Nexus 1 debug. A complete discussion of the e200z0 OnCE debug features is available in the core reference manual. 35.9.1 e200z0 OnCE controller block diagram Figure 35-6...
Page 866 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) 35.9.3 e200z0 OnCE controller registers description Most e200z0 OnCE debug registers are fully documented in the core reference manual. 35.9.3.1 OnCE Command register (OCMD) The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI pin and serves as the instruction register (IR).
Page 867 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) Table 35-4. e200z0 OnCE register addressing (continued) RS[0:6] Register selected 010 0111 Data Value Compare 2 (DVC2) 010 1000 – 010 1111 Reserved 011 0000 Debug Status Register (DBSR) 011 0001 Debug Control Register 0 (DBCR0) 011 0010 Debug Control Register 1 (DBCR1)
Page 868 Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 869 Chapter 36 Nexus Development Interface (NDI) Chapter 36 Nexus Development Interface (NDI) 36.1 Introduction The Nexus Development Interface (NDI) block provides development support capabilities for the MPC5602P MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several individual Nexus blocks that are selected to provide the development support interface for MPC5602P.
Page 870 Chapter 36 Nexus Development Interface (NDI) 36.3 Block diagram Figure 36-1 shows a functional block diagram of the NDI. Figure 36-1. NDI functional block diagram 36.4 Features The NDI module of the MPC5602P is compliant with Class 1 of the IEEE-ISTO 5001-2003 standard. The following features are implemented: •...
Page 871 Chapter 36 Nexus Development Interface (NDI) NOTE If the e200z0 core has executed a wait instruction, then the Nexus1 controller clocks are gated off. While the core is in this state, it is not possible to perform Nexus read/write operations. 36.5 Modes of operation The NDI block is in reset when the TAP controller state machine is in the TEST-LOGIC-RESET state.
Page 872 Chapter 36 Nexus Development Interface (NDI) 36.7 Memory map and registers description The NDI block contains no memory-mapped registers. Nexus registers are accessed by a development tool via the JTAG port using a client-select value and a register index. OnCE registers are accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD) via the JTAG port.
Page 873 Chapter 36 Nexus Development Interface (NDI) 36.9 Debug support overview Internal debug support in the e200z0h core allows for software and hardware debug by providing debug functions, such as instruction and data breakpoints and program trace modes. For software based debugging, debug facilities consisting of a set of software accessible debug registers and interrupt mechanisms are provided.
Page 874 Chapter 36 Nexus Development Interface (NDI) 36.9.2 Additional Debug Facilities In addition to the debug functionality built on Power Architecture technology, e200z0h provides capability to link instruction and data breakpoints, and also provides a sequential breakpoint control mechanism. e200z0h also defines two new debug events (CIRPT, CRET) for debugging around critical interrupts. In addition, e200z0h implements the Debug APU, which when enabled allows Debug Interrupts to utilize a dedicated set of save/restore registers (DSRR0, DSRR1) for saving state information when a Debug Interrupt occurs, and for restoring this state information at the end of a debug interrupt handler by means...
Page 875 Chapter 36 Nexus Development Interface (NDI) with MSR . Hardware-owned resources which set DBSR bits when DBCR0 =1 will cause an entry into debug mode. DBERC0 is read-only by software. When resource sharing is enabled, (DBCR0 and DBERC0 =1), only software-owned resources may be modified by software, and all status bits associated with hardware-owned resources will be forced to ‘0’...
Page 876 Chapter 36 Nexus Development Interface (NDI) cpu_dbgack dbg_dbgrq Pipeline Breakpoint and Information Trace Logic j_tclk OnCE DATA# Controller j_tdi ADDR# j_tdo, j_tdo_en ATTR# Serial PSTAT# Interface j_tms j_trst_b jd_en_once Debug Registers jd_de_b jd_mclk_on Comparators #-internal signals to/from CPU only p_ude p_devt[1,2] jd_watchpt[0:n] jd_de_en...
Page 877 Chapter 36 Nexus Development Interface (NDI) set DBSR bits regardless of the state of MSR . A Debug interrupt will be delayed until MSR is later set to ‘1’. When a Debug Status Register bit is set while MSR =0, and DBCR0 =0 or DBCR0 =1 and the corresponding resource is owned (via DBERC0) by software debug, an Imprecise Debug Event flag...
Page 878 Chapter 36 Nexus Development Interface (NDI) events will not occur when an instruction would not have normally begun execution due to a higher priority exception at an instruction boundary. IAC compares perform a 31-bit compare for VLE instructions. Each halfword fetched by the instruction fetch unit will be marked with a set of bits indicating whether an Instruction Address Compare occurred on that halfword.
Page 879 Chapter 36 Nexus Development Interface (NDI) NOTE DAC[1,2] events are not signaled if DVC[1,2]M is non-zero and a DSI or DTLB exception occurs on the load or store, since the load or store access is not performed. For a lmw or stmw transfer however, if a DVC successfully occurs on a transfer and a later transfer encounters a DSI or DTLB exception, the DAC event will be reported, since a successful data value compare took place...
Page 880 Chapter 36 Nexus Development Interface (NDI) Table 36-1. DAC events and Resultant Updates (continued) 1st load/store class 2nd load/store Result instruction class instruction DVC DACx DSI, no DAC Take Debug exception, DBSR update setting DACx, DAC_OFST not set. DSRR0 points to 2nd load/store class instruction. No MASx register update.
Page 881 Chapter 36 Nexus Development Interface (NDI) 36.10.3 Linked Instruction Address and Data Address Compare Event Data Address Compare debug events may be ‘linked’ with an Instruction Address Compare event by setting the DAC1LNK and/or DAC2LNK control bits in DBCR2 to further refine when a Data Address Compare debug event is generated.
Page 882 Chapter 36 Nexus Development Interface (NDI) execution of an instruction is suppressed due to the instruction causing some other exception which is enabled to generate an interrupt, then the attempted execution of that instruction does not cause an Instruction Complete debug event. The sc instruction does not fall into the category of an instruction whose execution is suppressed, since the instruction actually executes and then generates a System Call interrupt.
Page 883 Chapter 36 Nexus Development Interface (NDI) If MSR =1 at the time of the execution of the se_rfi, a Debug interrupt will occur provided there exists no higher priority exception which is enabled to cause an interrupt. Debug Save/Restore Register 0 will be set to the address of the se_rfi instruction.
Page 884 Chapter 36 Nexus Development Interface (NDI) register itself. Hardware always has full access to all registers and all register fields through the OnCE register access mechanism, and it is up to the debug firmware to properly implement modifications to these registers with read-modify-write operations to implement any control sharing with software.
Page 885 Chapter 36 Nexus Development Interface (NDI) 36.11.2 Debug Control and Status Registers Debug Control Registers (DBCR0, DBCR1, DBCR2, DBCR4, and DBERC0) are used to enable debug events, reset the processor, and set the debug mode of the processor. The Debug Status register (DBSR) records debug exceptions while Internal or External Debug Mode is enabled.
Page 886 Chapter 36 Nexus Development Interface (NDI) Table 36-2 provides bit definitions for Debug Control Register 0. Table 36-2. DBCR0 Bit Definitions Bit(s) Name Description External Debug Mode. This bit is read-only by software. 0 – External debug mode disabled. Internal debug events not mapped into external debug events.
Page 887 Chapter 36 Nexus Development Interface (NDI) Table 36-2. DBCR0 Bit Definitions (continued) Bit(s) Name Description IAC2 Instruction Address Compare 2 Debug Event Enable 0 – IAC2 debug events are disabled 1 – IAC2 debug events are enabled IAC3 Instruction Address Compare 3 Debug Event Enable 0 –...
Page 888 Chapter 36 Nexus Development Interface (NDI) SPR - 309; Reset Reset Figure 36-5. DBCR1 Register Reset by processor reset p_reset_b if DBCR0 =0, as well as unconditionally by m_por. If DBCR0 DBERC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0 will be reset by p_reset_b.
Page 889 Chapter 36 Nexus Development Interface (NDI) Table 36-3. DBCR1 Bit Definitions (continued) Bit(s) Name Description IAC12M Instruction Address Compare 1/2 Mode 00 – Exact address compare. IAC1 debug events can only occur if the address of the instruction fetch is equal to the value specified in IAC1. IAC2 debug events can only occur if the address of the instruction fetch is equal to the value specified in IAC2.
Page 890 Chapter 36 Nexus Development Interface (NDI) Table 36-3. DBCR1 Bit Definitions (continued) Bit(s) Name Description 24:25 IAC34M Instruction Address Compare 3/4 Mode 00 – Exact address compare. IAC3 debug events can only occur if the address of the instruction fetch is equal to the value specified in IAC3. IAC4 debug events can only occur if the address of the instruction fetch is equal to the value specified in IAC4.
Page 891 Chapter 36 Nexus Development Interface (NDI) Table 36-4 provides bit definitions for Debug Control Register 2. Table 36-4. DBCR2 Bit Definitions Bit(s) Name Description DAC1US Data Address Compare 1 User/Supervisor Mode 00 – DAC1 debug events not affected by MSR 01 –...
Page 892 Chapter 36 Nexus Development Interface (NDI) Table 36-4. DBCR2 Bit Definitions (continued) Bit(s) Name Description DAC2LNK Data Address Compare 2 Linked 0 – no affect 1 – DAC 2 debug events are linked to IAC3 debug events. IAC3 debug events do not affect DBSR When linked to IAC3, DAC2 debug events are conditioned based on whether the instruction also generated an IAC3 debug event.
Page 893 Chapter 36 Nexus Development Interface (NDI) Table 36-4. DBCR2 Bit Definitions (continued) Bit(s) Name Description 14:15 DVC2M Data Value Compare 2 Mode When DBCR4 DVC2C 00 – DAC2 debug events not affected by data value compares. 01 – DAC2 debug events can only occur when all bytes specified in the DVC2BE field match the corresponding data byte values for active byte lanes of the memory access.
Page 894 Chapter 36 Nexus Development Interface (NDI) 36.11.2.4 Debug Control Register 4 (DBCR4) Debug Control Register 4 is used to extend data value compare matching functionality. DBCR4 is shown Figure 36-7. SPR - 563 Reset Reset Figure 36-7. DBCR4 Register DBCR4 is reset by processor reset p_reset_b if DBCR0 =0, as well as unconditionally by m_por.
Page 895 Chapter 36 Nexus Development Interface (NDI) 36.11.2.5 Debug Status Register (DBSR) The Debug Status Register (DBSR) contains status on debug events and the most recent processor reset. The Debug Status Register is set via hardware, and read and cleared via software. Bits in the Debug Status Register can be cleared using mtspr DBSR,RS.
Page 896 Chapter 36 Nexus Development Interface (NDI) Table 36-6 provides bit definitions for the Debug Status Register. Table 36-6. DBSR Bit Definitions Bit(s) Name Description Imprecise Debug Event Set to ‘1’ if MSR =0, DBCR0 =1 and a debug event causes its respective Debug Status Register bit to be set to ‘1’.
Page 897 Chapter 36 Nexus Development Interface (NDI) Table 36-6. DBSR Bit Definitions (continued) Bit(s) Name Description Return Debug Event Set to ‘1’ if a Return debug event occurred 17:20 — Reserved DEVT1 External Debug Event 1 Debug Event Set to ‘1’ if a DEVT1 debug event occurred DEVT2 External Debug Event 2 Debug Event Set to ‘1’...
Page 898 Chapter 36 Nexus Development Interface (NDI) If DBERC0 =1, all DBSR status bits corresponding to hardware-owned debug events are masked to ‘0’ when accessed by software. The actual values in the DBSR register is always visible to hardware when accessed via the OnCE port. Software-owned resources may be modified by software, but only the corresponding control and status bits in DBCR0-4 and DBSR are affected by execution of a mtspr, thus only a portion of these registers may be affected, depending on the allocation settings in DBERC0.
Page 899 Chapter 36 Nexus Development Interface (NDI) Table 36-6 provides bit definitions for the Debug External Resource Control Register. Note that DBERC0 controls are disabled when DBCR0 Table 36-7. DBERC0 Bit Definitions Bit(s) Name Description — Reserved Internal Debug Mode control 0 –...
Page 900 Chapter 36 Nexus Development Interface (NDI) Table 36-7. DBERC0 Bit Definitions (continued) Bit(s) Name Description IAC2 Instruction Address Compare 2 Debug Event 0 – Event owned by hardware debug. No mtspr access by software to IAC2 control and status fields. 1 –...
Page 901 Chapter 36 Nexus Development Interface (NDI) Table 36-7. DBERC0 Bit Definitions (continued) Bit(s) Name Description CIRPT Critical Interrupt Taken Debug Event 0 – Event owned by hardware debug. No mtspr access by software to DBCR0 CIRPT DBSR fields. CIRPT 1 – Event owned by software debug. DBCR0 and DBSR are software CIRPT...
Page 902 Chapter 36 Nexus Development Interface (NDI) Table 36-8. DBERC0 Resource Control (continued) Software Accessible via mtspr, affected by p_reset_b 1 1 — — — — — — — 1 — — — — — — — — — — — — — — IAC2, DBCR0 IAC2...
Page 903 Chapter 36 Nexus Development Interface (NDI) DBSR is always updated by p_reset_b, regardless of the value of DBCR0 or DBERC0 DBERC0 also controls which bits or fields in DBCR0–4 are reset by assertion of p_reset_b when DBCR0 =1. Only software-owned bits or fields as shown in Table 36-8 are affected in this case, except that DBCR0 and DBSR are updated by assertion of p_reset_b regardless of the value of...
Page 904 Chapter 36 Nexus Development Interface (NDI) register provides the capability of signaling the system level clock controller that the CPU clock should be activated if not already active. Updates to the DBCRx and DBSR registers via the OnCE interface should be performed with the CPU in debug mode to guarantee proper operation.
Page 905 Chapter 36 Nexus Development Interface (NDI) Auxiliary data registers OnCE mapped Debug registers j_tdi External Data registers j_tdo Bypass register TAP instruction register (OnCE OCMD) j_tclk j_tms j_tdo_en controller mux logic j_trst_b Figure 36-10. OnCE TAP Controller and Registers The OnCE controller is implemented as a 16-state FSM (finite state machine), with a one-to-one correspondence to the states defined for the JTAG TAP controller.
Page 906 Chapter 36 Nexus Development Interface (NDI) Test-Logic- Reset Select - IR Run - Test / Select DR- Scan Idle Scan Capture - DR Capture - IR Shift - DR Shift - IR Exit1 - DR Exit1 - IR Pause - DR Pause - IR Exit2 - DR Exit2 - IR...
Page 907 Chapter 36 Nexus Development Interface (NDI) output signal indicates that a debug session is in progress, and the OSR will indicate the CPU is in the debug state. Instructions may the be single-stepped by scanning new values into the CPUSCR, and performing a OnCE go+noexit command (See Section 36.12.5.2, “e200z0h OnCE Command Register (OCMD)).
Page 908 Chapter 36 Nexus Development Interface (NDI) 36.12.3.2 CPU Debug Acknowledge (cpu_dbgack) The cpu_dbgack signal is asserted by the CPU upon entering the debug state. This signal is used as part of the handshake mechanism between the OnCE control logic and the rest of the CPU. The CPU core may enter debug mode either through a software or hardware event.
Page 909 Chapter 36 Nexus Development Interface (NDI) before sending the first OnCE command. The assertion of this pin by the CPU Core acknowledges that it has entered the Debug Mode and is waiting for commands to be entered. To support operation of this system pin, the OnCE logic supplies the jd_de_en output and samples the jd_de_b input when OnCE is enabled (jd_en_once asserted).
Page 910 Chapter 36 Nexus Development Interface (NDI) selects a resource to be accessed as a data register (DR) during the TAP controller Capture-DR, Shift-DR and Update-DR states. TCLK OnCE COMMAND REGISTER UPDATE OnCE DECODER STATUS AND CONTROL REGISTERS REG WRITE REG READ MODE SELECT CPU CONTROL/STATUS Figure 36-12.
Page 911 Chapter 36 Nexus Development Interface (NDI) Table 36-10 provides bit definitions for the Once Status Register. Table 36-10. OnCE Status Register Bit Definitions Bit(s) Name Description MCLK m_clk Status Bit 0 – Inactive state 1 – Active state This status bit reflects the logic level on the jd_mclk_on input signal after capture by j_tclk. ERROR This bit is used to indicate that an error condition occurred during attempted execution of the last single-stepped instruction (GO+NoExit with CPUSCR or No Register Selected in OCMD), and that...
Page 912 Chapter 36 Nexus Development Interface (NDI) transitioned through in order for the single-step and/or exit functionality to be performed, even though the command appears to have no data resource requirement associated with it. RS[0:6] Reset - 10’b1000000010 on assertion of j_trst_b or m_por, or while in the Test_Logic_Reset state Figure 36-14.
Page 913 Chapter 36 Nexus Development Interface (NDI) Table 36-11. OnCE Command Register Bit Definitions (continued) Bit(s) Name Description Exit Command Bit 0 – Remain in debug mode 1 – Leave debug mode If the EX bit is set, the processor will leave the debug mode and resume normal operation until another debug request is generated.
Page 914 Chapter 36 Nexus Development Interface (NDI) Table 36-12. e200z0h OnCE Register Addressing (continued) RS[0:6] Register Selected 010 0111 Data Value Compare 2 (DVC2) 010 1000 – 010 1011 Reserved 010 1100 Reserved (DBCNT) 010 1101 – 010 1111 Reserved 011 0000 Debug Status Register (DBSR) 011 0001 Debug Control Register 0 (DBCR0)
Page 915 Chapter 36 Nexus Development Interface (NDI) Additionally, the DBCR0 bit is forced to ‘1’ internally while single-stepping to prevent Debug events from generating Debug interrupts. Also, during a debug session, the DBSR is frozen from updates due to debug events regardless of DBCR0 .
Page 916 Chapter 36 Nexus Development Interface (NDI) Table 36-13. OnCE Control Register Bit Definitions (continued) Bit(s) Name Description I_DVLE Instruction Side Debug TLB ‘VLE’ Attribute Bit (I_DVLE) This bit is used to provide the ‘VLE’ attribute bit to be used when the MMU is disabled during a debug session.
Page 917 Chapter 36 Nexus Development Interface (NDI) Table 36-13. OnCE Control Register Bit Definitions (continued) Bit(s) Name Description WKUP Wakeup Request Bit (WKUP) This control bit may be used to force the e200z0h p_wakeup output signal to be asserted. This control function may be used by debug firmware to request that the chip-level clock controller restore the m_clk input to normal operation regardless of whether the CPU is in a low power state to ensure that debug resources may be properly accessed by external hardware through scan sequences.
Page 918 Chapter 36 Nexus Development Interface (NDI) Table 36-14 provides a list of access requirements for OnCE registers. Table 36-14. OnCE Register Access Requirements Access Requirements Requires Requires Register Requires Requires Requires CPU to be CPU to be Name m_clk active jd_en_once to DBCR0 halted...
Page 919 Chapter 36 Nexus Development Interface (NDI) CPU must be in debug mode with clocks running. 36.12.7 Methods of Entering Debug Mode The OnCE Status Register indicates that the CPU has entered the debug mode via the DEBUG status bit. The following sections describe how e200z0h Debug Mode is entered assuming the OnCE circuitry has been enabled.
Page 920 Chapter 36 Nexus Development Interface (NDI) CPU to exit the state and enter the debug mode once the CPU clock m_clk has been restored. Note that in this case, the CPU will negate the p_waiting, p_halted and p_stopped outputs. Once the debug session has ended, the CPU will return to the state it was in prior to entering debug mode.
Page 921 Chapter 36 Nexus Development Interface (NDI) WBBR WBBR high Figure 36-16. CPU Scan Chain Register (CPUSCR) 36.12.8.1 Instruction Register (IR) The Instruction Register (IR) provides a mechanism for controlling the debug session by serving as a means for forcing in selected instructions, and then causing them to be executed in a controlled manner by the debug control block.
Page 922 Chapter 36 Nexus Development Interface (NDI) 36.12.8.2 Control State Register (CTL) The Control State Register (CTL) is a 32-bit register that stores the value of certain internal CPU state variables before the debug mode is entered. This register is affected by the operations performed during the debug session and should normally be restored by the external command controller when returning to normal mode.
Page 923 Chapter 36 Nexus Development Interface (NDI) 0100: Subtract 0x10 from PC. 0101: Subtract 0x14 from PC. all other encodings are reserved * — Internal State Bits These control bits represent internal processor state and should be restored to their original value after a debug session is completed, i.e when a e200z0h OnCE command is issued with the GO and EX bits set and not ignored.
Page 924 Chapter 36 Nexus Development Interface (NDI) 0: No Instruction Address Compare 1 event occurred on the fetch of this instruction. 1: An Instruction Address Compare 1 event occurred on the fetch of this instruction. IRStat3 — IR Status Bit 3 This control bit indicates an Instruction Address Compare 2 event status for the IR.
Page 925 Chapter 36 Nexus Development Interface (NDI) 1: If IRStat8 = ‘0’, A BookE Misaligned Instruction Fetch Exception has occurred while filling the If IRStat8 = ‘1’, IR contains an instruction with a byte-ordering error due to mismatched VLE page attributes, or due to E indicating little-endian for a VLE page. Emulation firmware should modify the content of the CTL, PC, and IR values in the CPUSCR during execution of debug related instructions as well as just prior to exiting debug with a go+exit command.
Page 926 Chapter 36 Nexus Development Interface (NDI) location, it will force the chip to execute an instruction that brings that information to WBBR. WBBR holds the 32-bit result of most instructions including load data returned for a load or load with update instruction.
Page 927 Chapter 36 Nexus Development Interface (NDI) External logic may monitor the assertion of these signals for debugging purposes. Watchpoints are signaled in the clock cycle following the occurrence of the actual event. The Nexus2+ module also monitors assertion of these signals for various development control purposes. Table 36-15.
Page 928 Chapter 36 Nexus Development Interface (NDI) • Select the DBCR0 register and update it with the DBCR0 bit set • Clear the DBSR status bits • Write appropriate values to the DBCRx, IAC, DAC registers. Note that the initial write to DBCR0 will only affect the EDM bit, so the remaining portion of the register must now be initialized, keeping the EDM bit set At this point the system is ready to commence debug operations.
Page 929 Chapter 36 Nexus Development Interface (NDI) 36.15 Functional description The NDI block is implemented by integrating the following blocks on the MPC5602P: • Nexus e200z0 development interface (OnCE subblock) • Nexus port controller (NPC) block 36.15.1 Enabling Nexus clients for TAP access After the conditions have been met to bring the NDI out of the reset state, the loading of a specific instruction in the JTAG controller (JTAGC) block is required to grant the NDI ownership of the TAP.
Page 930 Chapter 36 Nexus Development Interface (NDI) MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 931 Chapter 37 Document Revision History Chapter 37 Document Revision History Table 37-1 summarizes revisions to this document. Table 37-1. Revision history Date Revision Changes 10-Dec-2009 Initial release MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 932 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 16-Mar-2010 Preface About this book: Minor editorial changes Organization: – Corrected cross-reference to Nexus chapter – Removed bullet “Appendix B, “Memory Map” Register figure conventions: Minor editorial correction Table ii, “Acronyms and Abbreviated Terms,”...
Page 933 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 16-Mar-2010 Chapter 12, “e200z0 and e200z0h Core Section 12.2, “Features: Removed bullet “Power saving modes: doze, nap, sleep, and wait” Chapter 13, “Peripheral Bridge (PBRIDGE): Unchanged from previous revision Chapter 14, “Crossbar Switch (XBAR): Unchanged from previous revision Chapter 15, “Error Correction Status Module (ECSM)
Page 934 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 16-Mar-2010 Chapter 23, Analog-to-Digital Converter (ADC) ADC digital registers: Removed Channel Pending Registers (CEOCFR[x]) and Decode Signals Delay Register (DSDR) Section 23.3.3, ADC sampling and conversion timing: Corrected instances of bitfield name INPSAMPLE to INPSAMP Section 23.3.7, Interrupts: Removed content concerning register CEOCFR...
Page 935 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 16-Mar-2010 Chapter 33, “Boot Assist Module (BAM) Minor editorial and formatting changes Section 33.3, “Boot modes: Minor editorial changes Section 33.5.1, “Entering boot modes: Editorial changes Boot mode selection: Added Autobaud Scan boot mode Section 33.5.3, “Reset Configuration Half Word (RCHW): Removed the word “Source”...
Page 936 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 31-Mar-2011 “Preface” chapter, entirely rewrote “MPC5602P block diagram”, made arrow going from peripheral bridge to crossbar switch bidirectional “Clock Description” chapter • In the “Functional description” section, replaced all occurences of XTALOUT with EXTAL.
Page 937 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 31-Mar-2011 “Deserial Serial Peripheral Interface (DSPI)” chapter cont’d In the “DSPI memory map” table, removed access and reset columns. In the “DSPI block diagram” figure, replace arrow labels from “1” to “3”. In the DSPIx_MCR.CONT_SCKE filed description, added a note.
Page 938 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 31-Mar-2011 “Nexus Development Interface (NDI)” chapter: cont’d Minor editorial and formatting changes Throught the chapter, removed all DOZE occurrences. Replaced several references to Power Architecture™ with references to Power Architecture In the “OnCE Register Access Requirements”...
Page 939 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 31-Mar-2011 “Fault Collection and Control Unit (FCCU)” chapter: cont’d Changed the chapter title in “Fault Collection and Control Unit (FCCU)” instead of "Fault Collection Unit (FCU)". In the “FCCU memory map” table, removed access and reset columns per new agreement.
Page 940 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 28-Feb-2012 Chapter 2, MPC5602P Memory Map Table 2-1 (Memory map): Changed “Data Flash Array 0 Test Sector” size from 16K to 8K Chapter 3, Signal Description: In the Table 3-3 (Pin muxing):removed Port E[0] Chapter 4, Clock...
Page 941 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 28-Feb-2012 Chapter 21, LIN Controller (LINFlex) cont’d Figure 21-8 (LIN status register (LINSR)): changed LINS access from read/write to write only Figure 21-13 (LIN output compare register (LINOCR)): changed note from LINTCSR[LTOM] = 1 to LINTCSR[LTOM] = 0 Updated...
Page 942 Chapter 37 Document Revision History Table 37-1. Revision history (continued) Date Revision Changes 28-Feb-2012 Chapter 27, Functional Safety: cont’d Figure 27-16 (SWT Counter Output register (SWT_CO)): changed the access permission from read/write to read only Table 27-8 (SWT_TO field descriptions): updated fied description, was (SWT_CR.WENSWT_CR.=0) is (SWT_CR[WEN]=0).
Page 943 Appendix A Registers Under Protection Appendix A Registers Under Protection For MPC5602P, the Register Protection module is operable on the registers listed in Table A-1. Table A-1. Registers under protection Module Register Register size (bits) Register offset Protected bitfields Code Flash—Base address: 0xC3F8_8000 4 registers to protect Code Flash 0x0000...
Page 944 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL PCR14 0x005C bits[0:15] SIUL PCR15 0x005E bits[0:15] SIUL PCR16 0x0060 bits[0:15] SIUL PCR17 0x0062 bits[0:15] SIUL PCR18 0x0064 bits[0:15] SIUL PCR19 0x0066...
Page 945 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL PCR61 0x00BA bits[0:15] SIUL PCR62 0x00BC bits[0:15] SIUL PCR63 0x00BE bits[0:15] SIUL PCR64 0x00C0 bits[0:15] SIUL PCR65 0x00C2 bits[0:15] SIUL PCR66 0x00C4...
Page 946 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields SIUL IFMC13 0x1034 bits[0:31] SIUL IFMC14 0x1038 bits[0:31] SIUL IFMC15 0x103C bits[0:31] SIUL IFMC16 0x1040 bits[0:31] SIUL IFMC17 0x1044 bits[0:31] SIUL IFMC18 0x1048...
Page 947 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields MC ME ME_RUN_PC4 0x0090 bits[0:31] MC ME ME_RUN_PC5 0x0094 bits[0:31] MC ME ME_RUN_PC6 0x0098 bits[0:31] MC ME ME_RUN_PC7 0x009C bits[0:31] MC ME ME_LP_PC0 0x00A0...
Page 948 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields IRC_OSC RC_CTL 0x0000 bits[0:31] FM PLL 0—Base address: 0xC3FE_00A0 2 registers to protect FMPLL 0 0x0000 bits[0:31] FMPLL 0 0x0004 bits[0:31] CMU 0—Base address: 0xC3FE_0100 1 register to protect...
Page 949 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields ADC 0 CLR3 0x000C 32-bit ADC 0 CLR4 0x0010 32-bit ADC 0 TRC0 0x0034 32-bit ADC 0 TRC1 0x0038 32-bit ADC 0 TRC2 0x003C...
Page 950 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields FlexPWM—Base address: 0xFFE2_4000 41 registers to protect FlexPWM SUB0_CTRL2 0x0004 16-bit FlexPWM SUB0_CTRL 0x0006 16-bit FlexPWM SUB0_OCTRL 0x0018 16-bit FlexPWM SUB0_INTEN 0x001C 16-bit...
Page 951 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields FlexPWM SUB3_DMAEN 0x010E 16-bit FlexPWM SUB3_TCTRL 0x0110 16-bit FlexPWM SUB3_DISMAP 0x0112 16-bit FlexPWM SUB3_DTCNT0 0x0114 16-bit FlexPWM SUB3_DTCNT1 0x0116 16-bit FlexPWM MASK 0x0142...
Page 952 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields DSPI 1 DSPI_CTAR6 0x0024 32-bit DSPI 1 DSPI_CTAR7 0x0028 32-bit DSPI 1 DSPI_RSER 0x0030 32-bit DSPI 2—Base address: 0xFFF9_8000 11 registers to protect DSPI 2 DSPI_MCR 0x0000...
Page 953 Appendix A Registers Under Protection Table A-1. Registers under protection (continued) Module Register Register size (bits) Register offset Protected bitfields Safety port CANx_IMASK2 0x0024 32-bit Safety port CANx_IMASK 0x0028 32-bit MPC5602P Microcontroller Reference Manual, Rev. 4 Freescale Semiconductor...
Page 954 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based on the freescale.com information in this document.

This manual is also suitable for:

Safe assure qorivva mpc5601p