NXP Semiconductors MPC574xR Series Application Note

Clock calculator guide

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AN12020

MPC574xR Clock Calculator Guide

How to use MPC574xR tool to easily calculate device frequency domains

Rev. 5 — October 2018

by:

NXP Semiconductors

1 Introduction

NXP's MPC574xR is a dual-core 32-bit microcontroller intended for scalable

engine control and powertrain applications. This application note will refer to

any device in the MPC574xR family, MPC5743R, MPC5745R, and MPC5746R,

as simply "MPC5746R."

The MPC5746R supports an 8-40 MHz external oscillator (XOSC), a 16 MHz

internal RC oscillator (IRCOSC), and two phase locked loops (PLL) for a

maximum operating frequency of 200 MHz. The IRCOSC is selected out of

reset so increasing the operating frequency from 16 MHz requires additional

configuration. The MPC574xR Clock Calculator is meant to complement the

reference manual. It seeks to simplify the clock configuration process by providing a graphical, interactive tool to help the user

find the correct register settings in order to achieve the desired clock frequencies.

Accompanying this application note is the clock calculator. You can download it from MPC574xR_Clock_Calculator.

The clock calculator makes use of macros to perform functions like resetting the spreadsheet to initial values, configuring all clock

frequencies to the maximum allowable settings, and copying generated code. Macros must be enabled in the user's MS Excel to

access these features. If macros are turned off, however, the tool will still be able to calculate clock frequencies, but the

aforementioned features will be disabled. To turn on macros in MS Excel 2016, go to the Developer tab on the top toolbar and

click on Macro Security. A popup window will appear, select Enable all macros.

Figure 1. Enable macros

2 Clock calculator design

The MPC574xR clock calculator takes the form of an interactive Microsoft Excel spreadsheet organized into multiple tabs as shown

in the following figure.

Contents

1 Introduction.......................................... 1

2 Clock calculator design...................... 1

3 Clock tool example use sase:

Configure FlexCAN to XOSC at

40 MHz protocol clock and PLL0

50 MHz BIU/Module clock............... 14

4 Conclusion......................................... 26

5 Revision history................................. 26

Application Note

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Summary of Contents for NXP Semiconductors MPC574xR Series

Page 1 MPC574xR Clock Calculator Guide How to use MPC574xR tool to easily calculate device frequency domains Rev. 5 — October 2018 Application Note NXP Semiconductors Contents 1 Introduction 1 Introduction.......... 1 NXP’s MPC574xR is a dual-core 32-bit microcontroller intended for scalable 2 Clock calculator design......
Page 2 NXP Semiconductors Clock calculator design Figure 2. MPC574xR Clock calculator setup Clock sources (e.g. oscillators and PLLs) propagate to the various clock domains from which the MCU modules take their clocks. Most cells representing clock domain frequencies are not to be modified manually. The user is meant to enter frequencies to the few select clock sources and all clock domain frequencies derive from these sources.
Page 3 NXP Semiconductors Clock calculator design Figure 4. Clicking on a link The following subsections will explain in depth the purpose of each tab. 2.1 Tree Tree is the centerpiece of the tool. This tab is the starting point for all clock frequency calculations. It is organized to resemble the MPC5746R clock tree as presented in the following figure.
Page 4 NXP Semiconductors Clock calculator design Figure 5. MPC5746R reference manual clock tree The following figure shows, in part, the diagram’s clock tool counterpart. The difference between the two is that the latter is interactive. MPC574xR Clock Calculator Guide, Rev. 5, October 2018...
Page 5 NXP Semiconductors Clock calculator design Figure 6. Clock calculator tree The flow of the diagram generally goes from left to right. On the left are the MPC5746R clock sources and on the right are the clock domains. MCU modules run on one or more of these clock domains.
Page 6 NXP Semiconductors Clock calculator design Figure 7. Buttons 2.2 Oscillator control Oscillator Control controls the generation of the external oscillator (XOSC) frequency. MPC5746R supports two ways of XOSC generation. The chip has two external oscillator pins, XTAL and EXTAL. An 8-40 MHz external oscillator can be connected to both pins.
Page 7 NXP Semiconductors Clock calculator design 2.3 Peripheral domains Peripheral Domains is an in-depth diagram of MPC5746R modules. Where Tree leaves off at the clock domain level, Peripheral Domains picks up and progresses to the module level, shown below. Figure 9. Peripheral domains The clock domains are color-coded.
Page 8 NXP Semiconductors Clock calculator design Figure 10. LFAST in peripheral domains LFAST Clocking presents a block diagram of the module with various clocks going into it. It also supports LFAST_PLL configuration to increase the LFAST frequency up to 320 MHz. The LFAST also supports a low-speed mode as well as a high- speed mode.
Page 9 NXP Semiconductors Clock calculator design Figure 12. LFAST clocking input filter If RF_REF is 10, 13, 20, or 26 MHz, lfast_sys_clk is the same; otherwise, lfast_sys_clk is 0. MPC5746R does not actually filter RF_REF the way this tool does. The purpose of the LFAST Input Filter block is to simulate how the user can technically set RF_REF to any value, but the resulting LFAST output would be unusable.
Page 10 NXP Semiconductors Clock calculator design 2.6 Reference tables (pll0_phi, pll0_phi1, and pll1_phi) The three tabs pll0_phi, pll0_phi1, and pll1_phi are reference tables for the user to find the appropriate PLL dividers and multipliers to achieve the desired PLL frequency. There is a tab for each PLL output because input frequencies and the range of acceptable divider/multiplier values differ between each other.
Page 11 NXP Semiconductors Clock calculator design Figure 15. Register summary table The register values are displayed in either hexadecimal or binary format, where a “0x” prefix represents hexadecimal and “0b” denotes binary. A capital “X” represents a “don’t care” bit/half-byte. These bits do not affect the clock frequency, so users can set these values to whatever suits their purposes.
Page 12 NXP Semiconductors Clock calculator design Figure 16. Clock summary table This tool also supports a degree of code generation. Summary provides two sample clock initialization functions, Sysclk_Init for configuring oscillators and PLLs and InitPeriClkGen for providing sources/dividers to auxiliary clocks. The dynamic C code in these functions depend on tool settings just like the register summary.
Page 13 NXP Semiconductors Clock calculator design Figure 17. Sample initialization code 2.8 Limits Limits is the reference tab for all the color-coding rules. The values in its tables are based on the MPC5746R’s datasheet and reference manual and therefore should not be modified by the user. The following figure is a screenshot of the Limits tab.
Page 14 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 18. MPC5746R frequency limits 3 Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock The following sections will present an example application of the MPC574xR Clock Calculator.
Page 15 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 19. FlexCAN clocks. PBRIDGE_x_CLK and CAN_CLK are currently 16 MHz and 0 MHz, respectively. Configuring the clock calculator can be done in any order;...
Page 16 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 21. PBRIDGE_x_CLK to oscillators 3.1.1 Configure the oscillator Now start going downstream, configuring from the oscillator down to PBRIDGE_x_CLK. The external oscillator frequency is application-dependent and can be any value between 8 MHz and 40 MHz.
Page 17 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 23. Oscillator configuration Return to Tree.Trace forward from the XOSC block to XOSC Source Controller. The value of XOSC Source Controller is 0, meaning that the XOSC is turned off.
Page 18 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Switch the XOSC Source Controller value to 1 to turn on the XOSC. The output XOSC frequency is now 40 MHz, as show in the following figure.
Page 19 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 26. PLL0 source to XOSC Next, configure PLL0. Click on the PLL0 block to forward automatically to the PLL0 tab. This is the tab that sets up the PLL0_PHI frequency.
Page 20 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 28. PLL0_PHI reference table The PLL0 reference field is the frequency of the PLL0 input, in this case the 40 MHz XOSC. Set the target frequency and PREDIV values.
Page 21 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 30. When PLL0_PHI exceeds VCO and PLL spec Now let’s configure the PLL correctly. Turn on the PLL in the PLL0 tab by setting the PLL0 Mode Control block to 1, set Prediv to 2, Multiplier to 20, and RFDPHI to 2.
Page 22 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 32. PLL0_PHI propagated to Tree 3.1.3 Finish Setting PBRIDGE_x_CLK Next, follow the PLL0_PHI signal down to System Clock Selector. IRCOSC is the current source of SYS_CLK, PBRIDGE_x_CLK, and other system clock domains.
Page 23 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock enable, PBRIDGE_x_CLK is configured by Divider 2 of the system clock. As mentioned before, the user input for the divider field is not the desired divider, but the bitfield value that one would have to enter to achieve the desired divider.
Page 24 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock Figure 36. CAN_CLK in Tree XOSC and PLL0_PHI are already configured from the previous section, so there is no need to repeat those steps. CAN_CLK traces back to AUX Clock Selector 8, which currently follows the IRCOSC.
Page 25 NXP Semiconductors Clock tool example use sase: Configure FlexCAN to XOSC at 40 MHz protocol clock and PLL0 50 MHz BIU/Module clock 3.3 Observe the registers The final register summary table, as displayed in Summary, is shown in the following figure. Note that most of these registers would not have to be written in code to achieve the setup that this example just configured.
Page 26 NXP Semiconductors Conclusion Figure 39. Sysclk_Init after example To summarize, this example has achieved its goal: a FlexCAN whose bus interface and module clocks are driven by a PLL-sourced PBRIDGE_x_CLK at 50 MHz. The 50 MHz PBRIDGE_x_CLK is divided down from a 200 MHz PLL output; and the PLL output in turn is driven by the 40 MHz external oscillator.
Page 27 NXP Semiconductors Revision history Table continued from the previous page... Rev. No. Date Substantive Change(s) November 2017 Updated the associated MPC574xR_Clock_Calculator file. December 2017 Updated the associated AN12020SW. January 2018 Editorial updates. February 2018 Updated the associated AN12020SW. October 2018 Updated the associated AN12020SW.
Page 28 How To Reach Us Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to Home Page: design or fabricate any integrated circuits based on the information in this document. NXP nxp.com reserves the right to make changes without further notice to any products herein.

This manual is also suitable for:

Mpc5743r Mpc5745r Mpc5746r