NXP Semiconductors MPC5777M Datasheet

NXP Semiconductors
Data Sheet: Technical Data
MPC5777M Microcontroller
Data Sheet
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
®
– Power Architecture
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
embedded specification
Document Number: MPC5777M
MPC5777M
416 TEPBGA
27mm x 27 mm
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
• Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
• Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
• System Integration Unit Lite (SIUL)
• Boot Assist Module (BAM) supports factory programming
using serial bootload through 'UART Serial Boot Mode
Protocol'. Physical interface (PHY) can be:
– UART/LIN
– CAN
• GTM104 — generic timer module
• Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
• Eight deserial serial peripheral interface (DSPI) modules
• Two Peripheral Sensor Interface (PSI5) controllers
• Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
• Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
• External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
Rev. 6, 06/2016
512 TEPBGA
25 mm x 25 mm