Silicon Laboratories C8051T622 User Manual page 10

C8051T620/2-DK
Figure 4. C8051T62x Motherboard Default Shorting Block Positions
10
SW1
J1
C8051T62x-MB J14
P1
USB ACTIVE
P2
U2
USB ACTIVE
CP2103
J8
RTS_DEBUG CTS_DEBUG
P1.1 P1.2
RTS_COMM CTS_COMM
J11
RX_DEBUG TX_DEBUG
P4
P0.4 P0.5
RX_COMM TX_COMM
Figure 3. C8051T62x Motherboard
SW1
J1
J14
C8051T62x-MB
P1
USB ACTIVE
P2
U2
USB ACTIVE
CP2103
J8
RTS_DEBUG CTS_DEBUG
P1.1 P1.2
RTS_COMM CTS_COMM
J11
RX_DEBUG TX_DEBUG
P4
P0.4 P0.5
RX_COMM TX_COMM
LED1
LED2
SW2
SILICON LABS
www.silabs.com
P1.0 P0.1 P1.2 P0.6
SW2 SW1 LED2 LED1
P2.1 P2.0 P2.3 P2.2
J9 J10
J2 J15
VPP
J7
J3
J6
VDD_PWR
+3VD
VDD_PWR
VDD_EXT
VDD_PWR
J4 VDD_DEBUG
VDD_PWR
VDD_COMM
D10 D11 D12
RUN STOP
J5
U1
F326
J12
J13
RESET
R8
LED1
LED2
SW2 SILICON LABS
www.silabs.com
P0.1 P0.6
P1.0 P1.2
SW1 LED1
SW2 LED2
P2.0 P2.2
P2.1 P2.3
J9 J10
J2 J15
VPP
J7
J3
J6
VDD_PWR
+3VD
VDD_PWR
VDD_EXT
VDD_PWR
J4 VDD_DEBUG
VDD_PWR
VDD_COMM
D10
D11 D12
RUN STOP
J5
U1
F326
J12
J13
RESET
R8
Rev. 0.5
P3
PWR
DEBUG
PWR
P5
P3
PWR
DEBUG
PWR
P5