Board (Xks-Q8111) And Net-32A Board (Xks-Q8166) - Sony XVS-9000-C Service Manual

• Control of Network PHY
CADEC
FPGA configuration
FPGA configuration data is stored in the flash memory (IC207, IC2807). After power is turned on, the CADEC (IC201,
IC2801) reads necessary data from the flash memory and performs FPGA configuration.
Nios boot
After the configuration has been completed, the CADEC releases FPGA reset to boot the Nios.
Writing installation data
Installation data used in the production process is stored in the flash memory (IC207, IC208, IC2807, IC2808) through
the local bus connected to the CA-92 board.
5-6-2. NET-32 Board (XKS-Q8111) and NET-32A Board (XKS-Q8166)
The NET-32 board and the NET-32A board have the following functions.
• These boards function as a network interface board that supports Video Over IP.
• These boards convert the SDI signal in the switcher to an IP signal by using the NeptuneII ASIC.
• The external interface supports QSFP+ (40GBASE-SR4) and is provided with two Cages for mounting the QSFP
+ Module (one of them is used for redundancy).
• 4K video signals for up to four channels can be transmitted with a single board (by using 1-channel signal QSFP
+ and 16-channel 3G SDI signal).
• The NET-32 board is used to input video signals and the NET-32A board is used to output video signals.
Video signal processor
Network input (NET-32 board)
The input SFI signal (conforming to 40GBASE-SR4) from the QSFP+ module is converted to an RXAUI signal by
using the Network PHY (IC4301, IC4401) and the RXAUI signal is converted to an XAUI signal in the RXAUI-XAUI
Converter (IC2201, IC4201). This XAUI signal is transmitted to the NeptuneII (IC1301, IC1701, IC3301, IC3701). In
the NMI mode, processings of FEC, LLVC Encode/Decode, Network Packetize, and network synchronization are added
to network packets in the NeptuneII ASIC (IC1001, IC1801, IC3601, IC4401), and then processed network packets are
transmitted to the FPGA (IC501, IC2501) as User IF signals (parallel video signals conforming to SMPTE). User IF
signals transmitted from the NeptuneII to the FPGA (IC301, IC2901) are corrected to unit's REF signals in the TBC
circuit in the FPGA, and are then converted to a serial signal. This serial signal is output to the switcher as an SDI signal.
Network output (NET-32A board)
The SDI signal transmitted from the switcher to the FPGA (IC301, IC2901) is converted to parallel signals, and the
parallel signals are transmitted to the NeptuneII as User IF signals. The User IF signals transmitted from the FPGA to
the NeptuneII receive processings of FEC, LLVC Encode/Decode, Network Packetize, and Network synchronization
in the NeptuneII. The processed User IF signals are transmitted to the RXAUI-XAUI Converter IC as XAUI signals.
The Network PHY that received the XAUI signal converts this signal to an RXAUI signal by using the RXAUI-XAUI
converter. The RXAUI signal is converted to an SFI signal in the Network PHY, and then the SFI signal is transmitted
to the QSFP+ module.
Control signal processor
Nios 2 processor
The Nios 2 processor in the FPGA totally controls the board. The firmware of the Nios 2 processor is stored in the flash
memory (IC402, IC403, IC2403, IC2404) and works with the SRAM (IC401, IC2401) as work RAM.
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
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