Sony XVS-9000-C Service Manual page 172

DVP-68 (2/5)
Control Block
CN701
UART0
UART0
Debug CN T/R
IC1664 IC1665 IC1663
DDR SPD EEPROM EEPROM THRM
(SO-DIMM) 2Kbit 2Kbit
THERMAL
I2C
I2C1
I2C2
CN751
DDR3 SO-DIMM
2GB(256Mbx64)
64
DDR
RESET_DIMM
CN601
JTAG
CN
JIG Cable JTAG
JTAG ICE
ICE_RSTn to CADEC
ICE_HRESET
ICE_SRESET
ICE_BTWE_RST
ICE_TRST
IC1502
CLK Gen
Sys_CCB
DDRCLK
125M
PCIe_CLK1
PCIe_CLK2
25M_CLK
PHY_CLK
I2C_CG
PHY_CLK
IC1701
CN
(MB)
Serdes
Port0
RGMII
TRANS PHY 0-3
SCU_PHY_CTRL
LED
RESET_PHY
Serdes
Port1
0-3
CN702
CN
SD/MMC
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
IC6
Buffer
Buffer
eLBC 32
LAD
AL
LALE
Chip Select CS[3:0]
LCS[3:0]
LWE[3:0],LOE,LBCTL CTL
CTL
WAIT
LGTA
CTRL
TOF
From CA-92
REF Gen.
148.5MHz
27MHz
MDIO/MDC
INT VD/CKX
Contrl
IRQ
UID
Unit ID
From CA-92
Decoder
cfg_xxxx
CPU
Config
CTRL
P_GOOD
DEV_RESET
RESET_PHY/RESET_DIMM
RST_RCB/RST_PLL/PERST
RST_FLASH
Power
&
ICE_RSTn
Reset
RSTn_REQ
Control
RSTn_REQ
CPU_RSTn(HRESET/SRESET/TRST)
RSTn
(HRESET/SRESET/TRST)
RESET
Reset
From CA-92
25M_CLK
CTRL
8 8 16
Debug Debug 7SEG
Dipsw LED LED
8bit 8bit 16bit
PCIe_CLK1
PCIe
PCI-Express Gen1 4Lane
DIR/OE
IC1
CADEC
Nor Flash
IC1101
FPGA Data
EXT IC1102
Bus IC1103
(128Mbyte)
CTRL IC1104
Flash_DT Buffer
Data/
Address
Sel
Flash_AD
RST_FLASH
Ctl Reg.
ADRS dec.
Flash_CS
Config_CS
/WE/OE
Flash_Ctl
Sel
WE
Regen.
XLX_DT[7:0],CCLKO,
XLX_DONE,
XLX_RPGM,WRITE,
FPGA Config XLX_INIT,CS
Control
SEL
IC304
CC_CTRL1 RFSDI_CLK
CLOCK
148.5MHz
Cleaner
CTRL1
Buffer
CLOCK
Cleaner I2C_CG
CTRL3
to CLK Gen for P1022
JTAG
8
B-Con
Status
LED
5bit CN
CN1601
IC2/IC3/IC4/IC5
FPGA1/2/3
CPU I/F
CPU_CLK
Data[31:0]
ALE
CSn[3:2]
OEn
WEn
Nor Flash
Boot&Application
1GB IC1105
512MB
(64Mbyte)
TOF
INTn_FPGA
Config
IC2001
DDR_CLK
CLK
Buffer
266MHz
IC404
CLK
148.5MHz
VID_CLK
FPGA_RST[3:0]
RST_RCB
Buffer
PLL_RST[3:0]
RST_PLL
JTAG
PCIe_CLK2
To
PERST PCIe
FPGA2_2
IC4 Only
7-20