Sony XVS-9000-C Service Manual page 173

DVP-68 (3/5)
Clock Tree Block 3.3V->1.8V
Buffer
IC815
CPU_CLK
62.5MHz
TP802
OSC CLK Gen. CPU
Sys CCB
X1502 IC1502 IC6
25MHz
DDRCLK MCK0P/N SO-DIMM
MCK1P/N
CN751
125M SDHC CLK
TSEC TX CLK
PCIE LR0 TSEC RX CLK
PCIE LR1
FPGA2_PCIE_CLKP/N to FPGA2-2 IC4(Bank225)
PCIE LR2
Reserve
REF1
25M_CADEC
Ether PHY
REF2 IC1701
3.3V->1.8V
OUT1
MB CLK Buffer CLK Cleaner
IC306 OUT0 IC304
VCLK_P/N
(148.35MHz OUT3
148.5MHz)
OUT4
OUT0
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
1.8V
Buffer
OSC Buffer
IC811
FPGA_CPU_CLK[3]
X301 IC301
to FPGA3 IC5(Bank52)
50MHz
FPGA_CPU_CLK[2]
to FPGA2-2 IC4(Bank70)
FPGA_CPU_CLK[1]
to FPGA2-1 IC3(Bank70)
OSC CLK Buffer
FPGA_CPU_CLK[0]
X2002 IC2002
to FPGA1 IC2(Bank52)
156.25
MHz
CPU_CLK_CADEC
to CADEC IC1
for Aurora
SD-Card
CN702
RFCLK_CADECP/N
CLK Buffer
CL303/304
IC305
RFCLK1P/N
RFCLK2P/N
RFCLK3P/N
RFCLK4P/N
RFCLK5P/N
RFCLK6P/N
RFCLK7P/N
RFCLK8P/N
CLK Buffer
CL305/306
IC306
RFCLK9P/N
RFCLK10P/N
RFCLK11P/N
RFCLK12P/N
RFCLK13P/N
CLK Buffer
IN1
IC404
VIDCLK1P/N
VIDCLK2P/N
VIDCLK3P/N
VIDCLK4P/N
VID_SEL
By CADEC(Default IN1)
CADEC
CPU_CLK CADEC
IC1
RFCLK_CADECP/N
25M_CADEC
TP301
FPGA1
IC2
BANK133 BANK73
AURORA_CLK1_P/N
DDR3
BANK132 AURORA BANK72
64bit
RFCLK3P/N
BANK131 BANK71
BANK68
BANK128
AURORA_CLK2_P/N
DDR3
BANK127 No used BANK67
to FPGA2-1 IC3(Bank226)
32bit
BANK126 BANK66
AURORA_CLK3_P/N
BANK233 BANK53
to FPGA2-2 IC4(Bank226)
BANK232 BANK52
CPUIF
RFCLK1P/N REF
BANK231 SDI 6G BANK51
BANK230 BANK46
DDR3
BANK229 BANK45
32bit
BANK228 BANK44
BANK227
RFCLK2P/N
BANK226 SDI 3G
BANK225 BANK70
BANK224
BANK65
FPGA2-1
IC3
BANK133
BANK73
DDR4
BANK132 No used BANK72
32bitx2
BANK131 BANK71
BANK128 BANK68
Test
DDR4
RFCLK6P/N
BANK127 BANK67
32bitx2
BANK126 SDI 6G BANK66
BANK233 BANK53
DDR4
BANK232
BANK52
32bitx2
RFCLK4P/N
BANK231 SDI 6G BANK51
BANK230
BANK46
DDR4
BANK229 BANK45
32bitx2
AURORA_CLK2_P/N BANK228 BANK44
AURORA
BANK227
RFCLK5P/N
BANK226
BANK70
CPUIF
BANK225 PCle
REF
BANK224 BANK65
FPGA2-2
IC4
BANK133
BANK73
DDR4
BANK132 No used BANK72
32bitx2
BANK131
BANK71
BANK128 BANK68
Test
DDR4
RFCLK9P/N
BANK127 BANK67
32bitx2
BANK126 SDI 6G
BANK66
BANK233
BANK53
DDR4
BANK232 BANK52
32bitx2
RFCLK7P/N
BANK231 SDI 6G BANK51
BANK230
BANK46
DDR4
BANK229 BANK45
32bitx2
BANK228 BANK44
AURORA_CLK3_P/N
AURORA
BANK227
RFCLK8P/N
BANK226
BANK70
CPUIF
PCle
BANK225
REF
FPGA2_PCIE_CLK_P/N
BANK224 BANK65
FPGA3
IC5
BANK133 BANK73
RFCLK13P/N DDR3
BANK132 SDI 6G BANK72
64bit
BANK131 BANK71
BANK128 BANK68
RFCLK12P/N
BANK127 SDI 6G No Used BANK67
BANK66
BANK126
BANK233 BANK53
BANK232 BANK52
CPUIF
RFCLK10P/N REF
BANK231 SDI 6G BANK51
BANK230 BANK46
DDR3
BANK229 BANK45
32bit
BANK228 SDI 6G BANK44
BANK227
RFCLK11P/N
BANK226 SDI 3G
BANK225
BANK70
BANK224 BANK65
CLK Buffer OSC
IN0
IC2003 X2003
DDR3_SYSCLK3P/N
233.33
MHz
for DDR3
DDR3_SYSCLK1P/N
FPGA1_CPU_CLK[0]
VID_CLK1P/N
DDR3_SYSCLK2P/N
DDR3_SYSCLK4P/N
to FPGA3 IC5(Bank44)
DDR3_SYSCLK5P/N
to FPGA3 IC5(Bank73)
CLK Buffer
IC2001
DDR4_SYSCLK4P/N
DDR4_SYSCLK3P/N
for DDR4
OSC
IN1
X2004
DDR4_SYSCLK2P/N
266.66
MHz
DDR4_SYSCLK1P/N
FPGA2_CPU_CLK[0]
VID_CLK2P/N
DDR4_SYSCLK8P/N
DDR4_SYSCLK7P/N
DDR4_SYSCLK6P/N
DDR4_SYSCLK5P/N
FPGA2_CPU_CLK[1] INTP_DDR_CLK_SEL
By CADEC(Default IN1)
VID_CLK3P/N
DDR3_SYSCLK5P/N
FPGA1_CPU_CLK[0]
VID_CLK4P/N
DDR3_SYSCLK4P/N
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