Gpio Configuration - Xycom Xembedded XPMC-6710 Reference Manual

GPIO Configuration

Each GPIO pin can be configured as an input, an input with open-drain capability, or an output.
The GPIOs are connected to the Tsi109 Host Bridge GPIO pins. The GPIO Interface has a set
of output latches, which depending on configuration, either drive the output enables or the
output pins. The Interface also has a set of input buffers that provides the state of the GPIO
pins and can be read at any time.
The GPIO pins can also be used as additional interrupt inputs by mapping the pins to one or
more of the four interrupt output pins. Each pin can be configured to generate an interrupt on
an edge-detected transition (low-to-high or a high-to-low), or a level-detected state. Table 1
below list the location and destination of the GPIOs.
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
NOTE:
Document Number: 646710
Table 1 GPIOs Signals and Destinations
Signal
J4, Pin 35
J4, Pin 36
J4, Pin 37
J4, Pin 38
J4, Pin 39
J4, Pin 40
J4, Pin 41
J4, Pin 42
R6: Pull up to SW2 Pin 8
R7: To on-board CPLD (not used by default)
SEL/F/B: Select front or rear connection for
the Gigabit Ethernet port). This pin by default
has a pull down. Driving the pin high and
routes the Gigabit to the front. Default = Front
(the open boot drives this pin high)
*MR: Master Reset, pulling this pin low will
reset the board
LED0 (Front Panel) see note
LED1 (Front Panel) see note
LED2 (Front Panel) see note
LED3 (Front Panel) see note
*All LED's (LED0 to LED3) are active low.
Destination
Overview
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