1. Manuals
  2. Brands
  3. Xycom Manuals
  4. Computer Hardware
  5. XVME-113
  6. User manual

Xycom XVME-113 User Manual

Ram/rom memory module
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
r e t i r e d
XVME-113
RAM/ROM Memory
Module
P/N 74113-001(F)
© 1998 XYCOM, INC.
Printed in the United States of America

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the XVME-113 and is the answer not in the manual?

Questions and answers

Related Manuals for Xycom XVME-113

Summary of Contents for Xycom XVME-113

  • Page 1 XVME-113 RAM/ROM Memory Module P/N 74113-001(F) © 1998 XYCOM, INC. Printed in the United States of America...
  • Page 2 Brand or product names are registered trademarks of their respective owners. Copyright Information This document is copyrighted by Xycom Incorporated (Xycom) and shall not be reproduced or copied without expressed written authorization from Xycom. The information contained within this document is subject to change without notice.

  • Page 3: Table Of Contents

    Manual Structure Module Operational Description Specifications XVME-113 INSTALLATION Introduction Location of Components Relevant to Installation Installing Memory Chips on the XVME-113 Jumper and Switch List Jumper and Switch Descriptions 2.5.1 Bank 1 and Bank 2 Address Select 2.5.1.1 Extended/Standard Select 2.5.1.2 Bank 1 and Bank 2 Addressing Boundaries...
  • Page 4 Notched End of the Memory Chip 2-14 TABLE TITLE PAGE XVME-113 Memory Module Hardware Specifications Memory Module Environmental Specifications Switch and Jumper List VME Base Address Select Bank 1 & 2 Memory Device Size (Bank 1 and Bank 2) Address Modifier Switches...

  • Page 5: Introduction

    SYSRESET under this condition. Another option is to drive SYSFAIL when a low battery is detected on power up. The XVME-113 is designed to be used with 8-, 16-, and 32-bit VMEbus processor modules. It supports read modify write (RMW) cycles as well as unaligned transfers (UAT).

  • Page 6: Manual Structure

    Chapter 1 – Introduction 1.2 MANUAL STRUCTURE The purpose of Chapter One is to introduce the general specifications and functional capabilities of the XVME-113. Chapter Two will develop the various aspects of module installation and operation. Chapter Three provides information on how to program the Real Time Clock (RTC).

  • Page 7: Module Operational Description

    XVME-113 RAM/ROM Memory Module October 1992 1.3 MODULE OPERATIONAL DESCRIPTION Figure 1-1 below shows an operational block diagram of the XVME-113 RAM/ROM Memory Module. Figure 1-1. Operational Block Diagram...

  • Page 8: Introduction

    Chapter 1 – Introduction 1.4 SPECIFICATIONS Table 1-1 lists the XVME-113 Memory Module's Hardware Specifications. Table 1-1. XVME-113 Memory Module Hardware Specifications Characteristic Specification Maximum Memory Capacity: 1 bank of 16 sites, 1 bank of 8 sites 12 Mbytes Total...
  • Page 9 XVME-113 RAM/ROM Memory Module October 1992 Table 1-2 lists the XVME-113 Memory Module's Environmental Specifications. Table 1-2. Memory Module Environmental Specifications Characteristic Specification Temperature: Operating 0° to 65° C (32° to 149° F) Non-operating -40° to 85° C (-40° to 185° F)
  • Page 10 Chapter 1 – Introduction...
  • Page 11 %JCRVGT  +056#..#6+10  +0641&7%6+10 6JKU EJCRVGT GZRNCKPU JQY VQ EQPHKIWTG VJG :8/'  /GOQT[ /QFWNG DGHQTG KPUVCNNKPI VJG OQFWNG KPVQ C 8/'DWU U[UVGO +PHQTOCVKQP QP LWORGT CPF UYKVEJ QRVKQPU CPF NQECVKQPU KU CNUQ KPENWFGF  .1%#6+10 1( %1/210'065 4'.'8#06 61 +056#..#6+10 6JG LWORGTU UYKVEJGU OGOQT[ UQEMGVU CPF VJG 8/'DWU 2 CPF 2 EQPPGEVQTU QP VJG :8/'  /GOQT[ /QFWNG CTG KNNWUVTCVGF KP (KIWTG   QP VJG HQNNQYKPI RCIG...
  • Page 12 Chapter 2 - Installation (KIWTG   .QECVKQP QH ,WORGTU 5YKVEJGU 5QEMGVU CPF %QPPGEVQTU...
  • Page 13 XVME-113 RAM/ROM Memory Module October 1992 +056#..+0) /'/14; %*+25 10 6*' :8/'  #U RTGXKQWUN[ OGPVKQPGF VJGTG CTG C VQVCN QH VYGPV[ HQWT  RKP UQEMGVU KPVGPFGF HQT WUG D[ 4#/ '241/ (.#5* CPF ''241/ FGXKEGU QP VJG :8/'  /QFWNG...
  • Page 14 Chapter 2 - Installation · .KPG WR VJG RKPU QP GCEJ EJKR YKVJ VJG UQEMGV JQNGU HQWPF CV VJG KPUKFG VQR QH GCEJ UQEMGV NQECVKQP CPF RWUJ GCEJ EJKR HKTON[ CPF GXGPN[ KPVQ RNCEG · %JGEM VQ OCMG UWTG VJCV VJG EJKRU CTG HWNN[ UGCVGF KP VJG DQVVQO QH VJG UQEMGVU YKVJ PQ RKPU DGPV QT QWV QH CNKIPOGPV KP VJG UQEMGVU  ,7/2'4 #0&...
  • Page 15 XVME-113 RAM/ROM Memory Module October 1992  ,7/2'4 #0& 59+6%* &'5%4+26+105 6JG VYQ OGOQT[ DCPMU CTG KPFGRGPFGPVN[ EQPHKIWTCDNG XKC LWORGTU CPF UYKVEJGU VQ FGHKPG UKZ FKHHGTGPV OGOQT[ OQFWNG RCTCOGVGTU · 8/' #FFTGUU · #FFTGUU /QFKHKGT &GEQFG · /GOQT[ &GXKEG 5RGGF ·...
  • Page 16 Chapter 2 - Installation *GZ UYKVEJGU  CPF  YKNN DG WUGF VQ FKCN KP VJG GZVGPFGF CFFTGUU CPF JKIJ QTFGT CFFTGUU DKVU # # 6CDNG   UJQYU JGZ UYKVEJGU  CPF  6CDNG   *GZ 5YKVEJGU  CPF  'ZVGPFGF #FFTGUU 5YKVEJ  5YKVEJ  7RRGT *GZ 0KDDNG...
  • Page 17 XVME-113 RAM/ROM Memory Module October 1992 *GZ UYKVEJ  KU WUGF VQ UGNGEV VJG XCNKF UVCTVKPI DCUG CFFTGUU # # HQT $CPM  CPF *GZ UYKVEJ  KU WUGF VQ UGNGEV VJG XCNKF UVCTVKPI DCUG CFFTGUU # # HQT $CPM  6CDNG   UJQYU CNN $CPM  CFFTGUU UGNGEVKQPU...
  • Page 18 Chapter 2 - Installation 6CDNG   $CPM  #FFTGUU 5GNGEVKQP $#0-  8CNKF 5VCTVKPI #FFTGUU 5YKVEJ  - Z  - Z  - Z  - Z  2QUKVKQP &GXKEGU :: :: :: :: :: :: :: :: :: :: ::...
  • Page 19 XVME-113 RAM/ROM Memory Module October 1992  $CPM  CPF $CPM  #FFTGUUKPI $CPM  QH VJG :8/'  QEEWRKGU C 8/'DWU CFFTGUU URCEG QH  VKOGU VJG OGOQT[ EJKR UK\G 6JG DCPM OWUV DG CUUKIPGF VQ C UVCTVKPI CFFTGUU DQWPFCT[ YJKEJ KU C OWNVKRNG QH  VKOGU VJG OGOQT[ EJKR UK\G $CPM  QH...
  • Page 20 Chapter 2 - Installation (KIWTG   UJQYU VJG :8/'  /GOQT[ /CR 2-10...
  • Page 21 XVME-113 RAM/ROM Memory Module October 1992  $CPM  #FFTGUU %QPHKIWTCVKQP 'ZCORNG 6JG HQNNQYKPI KU CP GZCORNG QH $CPM  EQPHKIWTCVKQP YKVJ C 8/'DWU DCUG CFFTGUU QH ' KP VJG GZVGPFGF CFFTGUU TCPIG 5YKVEJ  5YKVEJ  5YKVEJ  5YKVEJ  2QUKVKQP ...
  • Page 22 Chapter 2 - Installation 6CDNG   #FFTGUU /QFKHKGT 5YKVEJGU $#0-  59+6%*  215+6+10  %NQUGF 5WRGTXKUQT[ QPN[ #/  1RGP 5WRGTXKUQT[ PQP RTKXKNGIGF #/PQ RTGHGTGPEG  1RGP 2TQITCO #EEGUU 4GURQPFU VQ CFFTGUU OQFKHKGT EQFGU '* QT #* '* QT #* KH KP VJG GZVGPFGF CFFTGUU TCPIG  %NQUGF 0Q RTQITCO CEEGUU 9KNN PQV TGURQPF VQ '* QT #* '* QT #* KH KP VJG...
  • Page 23 XVME-113 RAM/ROM Memory Module October 1992  /GOQT[ &GXKEG 5RGGF 6YQ UYKVEJ UGVVKPIU GZKUV HQT GCEJ DCPM VQ FGHKPG VJG URGGF QH VJG OGOQT[ FGXKEGU 5GNGEVKQPU CTG    CPF  PU CEEGUU VKOGU 6CDNG   NKUVU VJG UYKVEJGU CPF URGGF FGHKPKVKQP HQT GCEJ FGXKEG 6CDNG   /GOQT[ &GXKEG 5RGGF 5YKVEJ...
  • Page 24 Chapter 2 - Installation  /GOQT[ &GXKEG 6[RG 6JGTG CTG VYQ UYKVEJ UGVVKPIU CPF HKXG LWORGTU RGT $CPM QP VJG :8/'  VJCV FGVGTOKPG VJG FGXKEG V[RG 6JGUG CTG NKUVGF KP 6CDNGU   CPF   QP VJG HQNNQYKPI RCIG 6CDNG   $CPM  /GOQT[ &GXKEG 2KPQWV ,WORGTU $#0-  /'/14;...
  • Page 25 XVME-113 RAM/ROM Memory Module October 1992 6CDNG   $CPM  /GOQT[ &GXKEG 2KPQWV ,WORGTU $#0-  /'/14; 6;2' 59+6%*  '241/ %NQUGF %NQUGF %NQUGF 1RGP ''241/ 1RGP %NQUGF 8 (.#5* 944& 1RGP %NQUGF 8 (.#5* 4& 8 (.#5* 1RGP...
  • Page 26 Chapter 2 - Installation (KIWTGU   VJTW   UJQY VJG OGOQT[ EJKR RKPQWVU HQT '241/ 54#/ CPF (.#5*''241/ (KIWTG   '241/ /GOQT[ %JKR 2KPQWVU (KIWTG   54#/ /GOQT[ %JKR 2KPQWVU 2-16...
  • Page 27 XVME-113 RAM/ROM Memory Module October 1992 (KIWTG   (.#5*''241/ /GOQT[ %JKR 2KPQWVU  /GOQT[ &GXKEG 5K\G 6JG :8/'  EQPVCKPU VYQ UYKVEJ UGVVKPIU RGT $CPM VJCV FGVGTOKPG VJG FGXKEG UK\G 6CDNG   UJQYU VJG OGOQT[ FGXKEG UK\G HQT $CPMU  CPF  6CDNG   $CPM  CPF $CPM  /GOQT[ &GXKEG 5K\G...
  • Page 28 Chapter 2 - Installation  /GOQT[ $CEMWR 2QYGT &WTKPI RQYGT NQUU %/15 4#/ EJKRU OC[ JCXG CP CNVGTPCVKXG RQYGT UQWTEG EQPPGEVGF VQ TGVCKP VJG FCVC UVQTGF 6YQ CNVGTPCVKXG RQYGT UQWTEGU CTG CXCKNCDNG VJG QP DQCTF DCVVGT[ QT VJG 8 56&$; UKIPCN HTQO VJG 8/'DWU 6JG HQNNQYKPI EJCTV UJQYU VJG LWORGT EQPHKIWTCVKQP HQT GCEJ QRVKQP #NVGTPCVKXG 2QYGT 5QWTEG...
  • Page 29 XVME-113 RAM/ROM Memory Module October 1992 +P QTFGT VQ CEJKGXG OCZKOWO DCVVGT[ NKHG 4#/ EJKRU OWUV JCXG C UOCNN FCVC TGVGPVKQP EWTTGPV /QUV UVCVKE 4#/ UWRRNKGTU JCXG EJKRU VJCV IWCTCPVGG XGT[ NQY FCVC TGVGPVKQP EWTTGPVU 6Q ECNEWNCVG VJG V[RKECN DCVVGT[ NKHG...
  • Page 30 Chapter 2 - Installation  5;5(#+. &TKXGT # 5;5(#+. FTKXGT KU RTQXKFGF VQ CUUGTV 5;5(#+. YJGP C NQY DCVVGT[ KU FGVGEVGF CV RQYGT WR # NQY DCVVGT[ .'& QP VJG HTQPV RCPGN YKNN CNUQ NKIJV 6Q GPCDNG VJG 5;5(#+. FTKXGT QRGP UYKVEJ  RQUKVKQP  6Q FKUCDNG VJG 5;5(#+.
  • Page 31 XVME-113 RAM/ROM Memory Module October 1992  #FFTGUUKPI QH 46%%QPHKIWTCVKQP 2QTV # 4GCN 6KOG %NQEM KU CNUQ RTQXKFGF CPF TGUKFGU KP VJG 8/' 5JQTV +1 CFFTGUU URCEG 6JG FGXKEG UK\G CPF V[RG HQT VJG VYQ DCPMU CTG TGCFCDNG KP VJG UCOG 8/' 5JQTV +1 CFFTGUU URCEG  46%%QPHKIWTCVKQP 2QTV 'PCDNG&KUCDNG...
  • Page 32 Chapter 2 - Installation (KIWTG   46%%QPHKIWTCVKQP 2QTV $CUG #FFTGUU 5YKVEJGU 2-22...
  • Page 33 XVME-113 RAM/ROM Memory Module October 1992 9JGP C UYKVEJ KU KP VJG ENQUGF RQUKVKQP KG YJGP KV KU RWUJGF KP QP VJG QRRQUKVG GPF QH VJG UYKVEJ DCPM HTQO VJG QRGP NCDGN VJG EQTTGURQPFKPI DCUG CFFTGUU DKV YKNN DG NQIKE   9JGP C UYKVEJ KU UGV VQ VJG QRGP...
  • Page 34 Chapter 2 - Installation Table 2-11. Base Address Switch Options - Continued Switch 7 VME Base Address in VME Short I/O Address Space 1(A15) 2(A14) 3(A13) 4(A12) 5(A11) 6(A10) 8000H 8400H 8800H 8C00H 9000H 9400H 9800H 9C00H A000H A400H A800H AC00H B000H B400H...

  • Page 35: Supervisory/Non-Privilidged Mode Selection

    October 1992 2.5.9.3 Supervisory/Non-Privileged Mode Selection The XVME-113 RTC/Configuration port can be configured to respond to Supervisory access only, or to either Supervisory or non-privileged accesses. Switch 7 position 8 controls which configuration is selected, as shown in Table 2-12.
  • Page 36 Chapter 2 - Installation NOTE It should not be necessary to use excess pressure of force to engage the connectors. If the board does not properly connect with the backplane, remove the module and inspect all connectors and guide slots for possible damage or obstructions. Once the board is properly seated, tighten the two machine screws at the top and bottom of the front panel.

  • Page 37: Real Time Clock Programming

    Chapter 3 - REAL TIME CLOCK PROGRAMMING INTRODUCTION This chapter focuses on programming the Real Time Clock (RTC). It gives a complete description of each of the RTC registers, as well as procedures for programming the various functions of the RTC. The following is a list of Acronyms and Abbreviations used in this chapter.

  • Page 38: Real Time Clock/Readable Bank Information Address Map

    Chapter 3 – Real Time Clock REAL TIME CLOCK/READABLE BANK INFORMATION ADDRESS MAP All writes and reads to the Real Time Clock are at odd memory locations (D7-D0). The Real Time Clock uses 16 registers, and the remaining odd memory locations in the 1K address space are shadowed on 32 byte blocks. Table 3-1, shows the location of the registers.

  • Page 39: Register Map

    Real Time Clock Bits REGISTER MAP Table 3-3, on the following page, shows the address map of the 16 RTC registers. The registers are accessed on odd-byte addresses, beginning at the base address of the XVME-113 in the VMEbus Short I/O space.
  • Page 40 Chapter 3 – Real Time Clock Table 3-3. RTC Register Map Reg. Bit Definitions Register Name Offset 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 64 Hz Counter Seconds Counter c-mi c-mi c-mi c-mi c-mi c-mi c-mi...

  • Page 41: Register Descriptions

    XVME-113 RAM/ROM Memory Module October 1992 REGISTER DESCRIPTIONS The functions of the bits in the RTC registers are described in detail in the following sections. 3.4.1 64 Hz Counter (RTC Register 01h) The 64 Hz Counter Register is a read-only register which can be used to gain access to time values with greater resolution than one second.
  • Page 42 The RTC then sets the Alarm Flag (AF) bit in Control Register A. Since interrupts from the RTC are not used on the XVME-113, the AF bit is the only indication to the host processor that the alarm time has been reached.
  • Page 43 XVME-113 RAM/ROM Memory Module October 1992 3.4.6.1 Carry Flag (CF) The CF bit indicates that an internal carry has overlapped with a read from the 64 Hz Counter Register or a carry occurred from the Seconds Counter Register. After each read operation, the CF bit should be polled to ensure that the data read is valid.
  • Page 44 Chapter 3 – Real Time Clock 3.4.7.1 RAM These bits may be used as RAM or as flag bits at the user's discretion. These are readable/writable bits which retain their state upon power down. These bits may only be used if the TEST bit has been set to '0'. 3.4.7.2 TEST This bit is used to test the RTC at the factory and should always be set to '0' by the user's program.

  • Page 45: Programming Procedures

    Power-on Initialization The RTC on the XVME-113 must be initialized after power is first applied to the device. Initialization is only required when the power is initially turned on. As long as battery backup is enabled, the RTC will not need to be initialized after the VMEbus system is powered up.
  • Page 46 Delay for 3 seconds before continuing with initialization. This time is required for oscillator stabilization within the RTC chip. Since interrupts from the RTC are not used on the XVME-113, clear the CIE (bit 4 of Control Register A) and AIE (bit 3 of Control Register A) bits to '0'.
  • Page 47 XVME-113 RAM/ROM Memory Module October 1992 3.5.2.1 Setting the Time with the RTC Stopped If all of the date and time registers need to be set, stopping the clock is the preferred method for initializing the RTC. The procedure for setting the RTC time while it is stopped is described in the flow chart and instructions below.
  • Page 48 Chapter 3 – Real Time Clock 3.5.2.2 Setting Registers with the RTC Running If only one or a few of the date and time registers need to be set, they can be set while the RTC is running. The algorithm is more complicated, involving verification of the write operations by checking the CF.
  • Page 49 XVME-113 RAM/ROM Memory Module October 1992 3.5.3 Time Reading Procedure The following flow chart and instructions demonstrate the procedure for reading the RTC time and date. Reading the RTC time and date requires the use of the CF to validate the data read from the counter registers.
  • Page 50 Chapter 3 – Real Time Clock 3.5.4 RTC Alarm Function The RTC alarm function can be used to determine when the RTC time has reached a specified time, without having to read the entire set of RTC registers. The alarm time is specified by the user, and when the RTC time reaches the alarm time, the AF is set.
  • Page 51 XVME-113 RAM/ROM Memory Module October 1992 3.5.5 Application as a Long Term Timer The RTC can be used as a long-term timer and will keep accurate track of the year, month and day. If used in this application, setting the correct date is required. The RTC will properly handle the number of days in each of the twelve months, including leap years.
  • Page 53 APPENDIX A - VMEBUS CONNECTOR/PIN DESCRIPTION VMEBUS SIGNAL IDENTIFICATION Table A-1 (on pages 1 through 5) shows the VMEbus Signal Identification. Table A-2, on page 6, shows the Backplane P1 pin assignments. Table A-1. VMEbus Signal Identification Signal Connector and Mnemonic Pin Number Signal Name and Description...
  • Page 54 Appendix A - VMEbus Connector/Pin Description Table A-1. VMEbus Signal Identification (Continued) Connector Signal Pin Number Mnemonic Signal Name and Description A01-A23 1A:24-30 ADDRESS BUS (bits 1-23): Three-state driven address lines that specify a 1C:15-30 memory address. A24-A31 2B:4-11 ADDRESS BUS (bits 24-31): Three-state driven bus expansion address lines.
  • Page 55 XVME-113 RAM/ROM Memory Module October 1992 Table A-1. VMEbus Signal Identification (Continued) Connector Signal Mnemonic Pin Number Signal Name and Description BR0*-BR3* 1B:12-15 BUS REQUEST (0-3): Open-collector driven signals generated by Requesters. These signals indicate that a DTB master in the daisy-chain requires access to the bus.
  • Page 56 Appendix A - VMEbus Connector/Pin Description Table A-1. VMEbus Signal Identification (Continued) Connector Signal Pin Number Mnemonic Signal Name and Description IACK* 1A:20 INTERRUPT ACKNOWLEDGE: Open-collector or three-state driven signal from any master processing an interrupt request. It is routed via the backplane to slot 1, where it is looped-back to become slot 1 IACKIN* in order to start the interrupt acknowledge daisy-chain.
  • Page 57 XVME-113 RAM/ROM Memory Module October 1992 Table A-1. VMEbus Signal Identification (Continued) Connector Signal Mnemonic Pin Number Signal Name and Description SYSFAIL* 1C:10 SYSTEM FAIL: Open-collector driven signal that indicates that a failure has occurred in the system. It may be generated by any module on the VMEbus.
  • Page 58 Appendix A - VMEbus Connector/Pin Description BACKPLANE CONNECTOR P1 The following table lists the P1 pin assignments by pin number order. (The connector consists of three rows of pins labeled rows A, B, and C.) Table A-2. P1 Pin Assignments Row A Row B Row C...
  • Page 59 #22'0&+: $ 37+%- 4'('4'0%' )7+&' 6CDNGU $  $  CPF $  NKUV VJG LWORGTU UYKVEJ DKVU CPF VJGKT HWPEVKQP 6CDNG $  $CPM  %QPHKIWTCVKQP 5YKVEJGU $CPM  5YKVEJ  2QUKVKQP 5YKVEJ $KV &GUETKRVKQP 1RGP %NQUGF $CPM  5WRT0QPRTKX 5GNGEV 5WRT 5WRT0QPRTKX $CPM  2TQITCO #EEGUU...
  • Page 60 Appendix B - Quick Reference Guide 6CDNG $  $CPM  %QPHKIWTCVKQP 5YKVEJGU $CPM  5YKVEJ  2QUKVKQP 5YKVEJ $KV &GUETKRVKQP 1RGP %NQUGF $CPM  5WRT0QPRTKX 5GNGEV 5WRT 5WRT0QPRTKX $CPM  2TQITCO #EEGUU 4GURQPF VQ 2TQI #EE &QP V 4GURQPF $CPM  &CVC #EEGUU 4GURQPF VQ &CVC #EE &QP V 4GURQPF...
  • Page 61 XVME-113 RAM/ROM Memory Module October 1992 6CDNG $  $KV .QECVKQP 5YKVEJ $KV $KV .QECVKQP & /GOV[RGD &GVGTOKPGU /GOQT[ 6[RG $CPM  WRRGT DKV & /GOV[RGC &GVGTOKPGU /GOQT[ 6[RG $CPM  NQYGT DKV & /GOUK\GD &GVGTOKPGU /GOQT[ 5K\G $CPM  WRRGT DKV &...
  • Page 62 Appendix B - Quick Reference Guide 6CDNG $  UJQYU VJG LWORGT EQPHKIWTCVKQP HQT DCVVGT[ DCEMWR QRVKQPU 6CDNG $  ,WORGT %QPHKIWTCVKQP #NVGTPCVKXG 2QYGT 5WRRN[ 0QPG $CVVGT[ 8 1P 8 5VCPFD[ 8 1P 8 5VCPFD[ (CEVQT[ UJKRRGF EQPHKIWTCVQP 6CDNG $  &GXKEG 2CTCOGVGTU (QT /GOQT[ 5KVGU $CPMU  CPF  4#/ &GXKEG %JQUGP #EEGUU 6KOGU 2CTCOGVGT...
  • Page 63 XVME-113 RAM/ROM Memory Module October 1992 A write occurs during the overlap of a low CS1 and a low WE. A write begins at the latest transition among CS1 going low, and WE going low. A write ends at the earliest transition among CS1 going high, and WE going high.
  • Page 64 Appendix B - Quick Reference Guide Figure B-2. Read Timing Waveform...
  • Page 65 APPENCIX C - BLOCK DIAGRAM/ASSEMBLY DRAWING/SCHEMATICS Figure C-1. XVME-113 Block Diagram...
  • Page 66 Appendix C - Block Diagram/Assembly Drawing/Schematics Figure C-2. Assembly Drawing...

Table of Contents