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BMR46 series PoL Regulators
BMR46 series PoL Regulators
Input 4.5-14 V, Output up to 50 A / 165 W
Input 4.5-14 V, Output up to 50 A / 165 W
Output Voltage Adjust using PMBus
The output voltage set by pin-strap can be overridden by
configuration file or by using a PMBus command. See
Electrical Specification for adjustment range.
When setting the output voltage by configuration file or by a
PMBus command, the specified output voltage accuracy is
valid only when the set output voltage level falls within the
same bin range as the voltage level defined by the pin-strap
resistor R
. The applicable bin ranges are defined in the
SET
table below. Valid accuracy for voltage levels outside the
applicable bin range is two times the specified.
Example:
Nominal V
is set to 1.10 V by R
O
within the bin range 0.988-1.383 V, thus specified accuracy is
valid when adjusting V
within 0.988-1.383V.
O
V
bin ranges [V]
O
0.600 – 0.988
0.988 – 1.383
1.383 – 1.975
1.975 – 2.398
2.398 – 2.963
2.963 – 3.753
For parallel operation, see application notes AN307.
Output Voltage Range Limitation
The output voltage range that is possible to set by
configuration or by the PMBus interface is limited by the pin-
strap resistor R
The maximum output voltage is set to 110%
SET.
of the nominal output value defined by R
. This protects the load from an over
1
V
1 .
V
O
,
MAX
O
,
RSET
voltage due to an accidental wrong PMBus command.
Output Voltage Adjust Limitation using PMBus
In addition to the maximum output voltage limitation by the pin-
strap resistor R
, there is also a limitation in how much the
SET
output voltage can be increased while the output is enabled. If
output is disabled then R
SET
Example:
If the output is enabled with output voltage set to 1.0 V, then it
is only possible to adjust/change the output voltage up to 1.7-
V as long as the output is enabled.
V
setting
O
when enabled [V]
0.000 – 0.988
0.988 – 1.383
1.383 – 1.975
1.975 – 2.398
2.398 – 2.963
2.963 – 3.753
= 26.1 kΩ. 1.10 V falls
SET
,
SET
resistor is the only limitation.
V
set range
O
while enabled [V]
~0.2 to >1.2
~0.2 to >1.7
~0.2 to >2.5
~0.2 to >2.97
~0.2 to >3.68
~0.2 to >4.65
Technical Specification
Technical Specification
1/28701-BMR 464 Rev.B
1/28701-BMR 464 Rev.B
© Flex
© Flex
Over Voltage Protection (OVP)
The product includes over voltage limiting circuitry for
protection of the load. The default OVP limit is 15% above the
nominal output voltage. If the output voltage exceeds the OVP
limit, the product can respond in different ways:
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the
device attempts a restart, i.e. the output voltage is pulled to
ground level (crowbar function).
The default response from an overvoltage fault is to
immediately shut down as in 2. The device will continuously
check for the presence of the fault condition, and when the
fault condition no longer exists the device will be re-enabled.
For continuous OVP when operating from an external clock for
synchronization, the only allowed response is an immediate
shutdown. The OVP limit and fault response can be
reconfigured using the PMBus interface.
Under Voltage Protection (UVP)
The product includes output under voltage limiting circuitry for
protection of the load. The default UVP limit is 15% below the
nominal output voltage. The UVP limit can be reconfigured
using the PMBus interface.
Power Good
The product provides a Power Good (PG) flag in the Status
Word register that indicates the output voltage is within a
specified tolerance of its target level and no fault condition
exists. If specified in section Connections, the product also
provides a PG signal output. The PG pin is active high and by
default open-drain but may also be configured as push-pull via
the PMBus interface.
By default, the PG signal will be asserted when the output
reaches above 90% of the nominal voltage, and de-asserted
when the output falls below 85% of the nominal voltage. These
limits may be changed via the PMBus interface. A PG delay
period is defined as the time from when all conditions within
the product for asserting PG are met to when the PG signal is
actually asserted. The default PG delay is set to 10 ms. This
value can be reconfigured using the PMBus interface.
For products with DLC the PG signal is by default asserted
directly after the DLC operation have been completed. If DLC
is disabled the configured PG delay will be used. This can be
reconfigured using the PMBus interface.
Switching Frequency
The fundamental switching frequency is 320 kHz, which yields
optimal power efficiency. The switching frequency can be set
to any value between 200 kHz and 640 kHz using the PMBus
interface. The switching frequency will change the
efficiency/power dissipation, load transient response and
output ripple. For optimal control loop performance in a product
without DLC, the control loop must be re-optimized when
changing the switching frequency.
53
July 2019
July 2019
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