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BMR46 series PoL Regulators
BMR46 series PoL Regulators
Input 4.5-14 V, Output up to 50 A / 165 W
Input 4.5-14 V, Output up to 50 A / 165 W
When changing DLC from enabled to disabled:
When changing DLC from enabled to disabled, the PID setting
in the user non-volatile memory will be loaded to RAM. Any
new optimized PID setting in RAM will be lost, if not first stored
to the user non-volatile memory.
When DLC is disabled:
When DLC is disabled and input power has been applied, the
PID setting in the user non-volatile memory will be loaded to
RAM and used in the control loop.
The original PID setting in the user non-volatile memory is
quite slow and not recommended for optimal performance. If
DLC is disabled it is recommended to either:
1.
Use the DLC to find optimized PID setting.
2.
Use Flex Power Designer to find appropriate PID
setting.
3.
Use Universal PID as defined below.
The Universal PID setting (taps) is:
A = 3289.56,
B = -6248.12,
C = 2964.06
Write 0x7CB941FDC3417CCD99 to PID_TAPS register and
write command STORE_USER_ALL
Note that if DLC is enabled, for best results V
before DLC algorithm begins.
Load Transient Response Optimization
The product incorporates a Non-Linear transient Response,
NLR, loop that decreases the response time and the output
voltage deviation during a load transient. The NLR results in a
higher equivalent loop bandwidth than is possible using a
traditional linear control loop. The product is pre-configured
with appropriate NLR settings for robust and stable operation
for a wide range of input voltage and a capacitive load range
as defined in the section External Decoupling Capacitors. For
an application with a specific input voltage, output voltage, and
capacitive load, the NLR configuration can be optimized for a
robust and stable operation and with an improved load
transient response. This will also reduce the amount of output
decoupling capacitors and yield a reduced cost. However, the
NLR slightly reduces the efficiency. In order to obtain maximal
energy efficiency the load transient requirement has to be met
by the standard control loop compensation and the decoupling
capacitors. The NLR settings can be reconfigured using the
PMBus interface.
See application note AN306 for further information.
Remote Sense
The product has remote sense that can be used to
compensate for voltage drops between the output and the
point of load. The sense traces should be located close to the
PWB ground layer to reduce noise susceptibility. Due to
derating of internal output capacitance the voltage drop should
be kept below
V
5 (
DROPMAX
will impact the electrical performance of the regulator. If the
remote sense is not needed, +S should be connected to VOUT
must be stable
I
.
A large voltage drop
5 .
V
)
2 /
O
Technical Specification
Technical Specification
1/28701-BMR 464 Rev.B
1/28701-BMR 464 Rev.B
© Flex
© Flex
and −S should be connected to GND.
Output Voltage Adjust using Pin-strap Resistor
VSET
R SET
PREF
R
also sets the maximum output voltage, see section
SET
"Output Voltage Range Limitation". The resistor is sensed only
during product start-up. Changing the resistor value during
normal operation will not change the output voltage. The input
voltage must be at least 1 V larger than the output voltage in
order to deliver the correct output voltage. See Ordering
Information for output voltage range.
The following table shows recommended resistor values for
R
. Maximum 1% tolerance resistors are required.
SET
V
[V]
R
[kΩ]
O
SET
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6
1.25
34.8
1.30
38.3
1.40
42.2
The output voltage and the maximum output voltage can be pin
strapped to three fixed values by connecting the VSET pin
according to the table below.
V
[V]
O
0.60
1.2
2.5
52
July 2019
July 2019
Using an external Pin-strap
resistor, R
, the output
SET
voltage can be set in the
range 0.6 V to 3.3 V at 28
different levels shown in the
table below. The resistor
should be applied between
the VSET pin and the PREF
pin.
V
[V]
R
[kΩ]
O
SET
1.50
46.4
1.60
51.1
1.70
56.2
1.80
61.9
1.90
68.1
2.00
75
2.10
82.5
2.20
90.9
2.30
100
2.50
110
3.00
121
3.30
133
VSET
Shorted to PREF
Open "high impedance"
Logic High, GND as reference
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