Advertisement
BMR46 series PoL Regulators
BMR46 series PoL Regulators
Input 4.5-14 V, Output up to 50 A / 165 W
Input 4.5-14 V, Output up to 50 A / 165 W
• If the capacitors capacitance value is
use at least
capacitors where
N
C
and
min
ESR
ESR
N
C
• If the ESR value is
ESR
capacitors of that type where
C
ESR
and
N
C
ESR
max
• If the
value is
ESR
ESR
should be
ESR
.
min
C
C
min
ESR
For a total capacitance outside the above stated range or
capacitors that do not follow the stated above requirements
above a re-design of the control loop parameters will be
necessary for robust dynamic operation and stability.
See technical paper TP022 for further information.
Control Loop
The product uses a voltage-mode synchronous buck controller
with a fixed frequency PWM scheme. Although the product
uses a digital control loop, it operates much like a traditional
analog PWM controller. As in the analog controller case, the
control loop compares the output voltage to the desired voltage
reference and compensation is added to keep the loop stable
and fast. The resulting error signal is used to drive the PWM
logic. Instead of using external resistors and capacitors
required with traditional analog control loops, the product uses
a digital Proportional-Integral-Derivative (PID) compensator in
the control loop. The characteristics of the control loop is
configured by setting PID compensation parameters. These
PID settings can be reconfigured using the PMBus interface.
Control Loop Compensation Setting
The products without DLC are by default configured with a
robust control loop compensation setting (PID setting) which
allows for a wide range operation of input and output voltages
and capacitive loads as defined in the section External
Decoupling Capacitors. For an application with a specific input
voltage, output voltage, and capacitive load, the control loop
can be optimized for a robust and stable operation and with an
improved load transient response. This optimization will
minimize the amount of required output decoupling capacitors
for a given load transient requirement yielding an optimized
cost and minimized board space. The optimization together
with load step simulations can be made using the Flex Power
Designer software.
Dynamic Loop Compensation (DLC)
Only some of the products that this specification covers have
this feature (see section Ordering Information).
The DLC feature might in some documents be referred to as
"Auto Compensation" or "Auto Tuning" feature.
The DLC feature measures the characteristics of the power
train and calculates the proper compensator PID coefficients.
one must
C
C
min
C
.
min
min
C
one must use at least N
ESR
max
.
min
N
the capacitance value
ESR
min
Technical Specification
Technical Specification
1/28701-BMR 464 Rev.B
1/28701-BMR 464 Rev.B
© Flex
© Flex
The default configuration is that once the output voltage ramp
up has completed, the DLC algorithm will begin and a new
optimized compensator solution (PID setting) will be found and
implemented. The DLC algorithm typically takes between 50
ms and 200 ms to complete.
By the PMBus command AUTO_COMP_CONFIG the user
may select between several different modes of operation:
•
Disable
•
Autocomp once, will run DLC algorithm each time the
output is enabled (default configuration)
Autocomp every second will initiate a new DLC
•
algorithm each 1 second
Autocomp every minute will initiate a new DLC
•
algorithm every minute.
The DLC can also be configured to run once only after the first
ramp up (after input power have been applied) and to use that
temporary stored PID settings in all subsequent ramps. If input
power is cycled a new DLC algorithm will be performed after
the first ramp up. The default setting is however to run the DLC
algorithm after every ramp up.
The DLC algorithm can also be initiated manually by sending
the AUTO_COMP_CONTROL command.
The DLC can also be configured with Auto Comp Gain Control.
This scales the DLC results to allow a trade-off between
transient response and steady-state duty cycle jitter. A setting
of 100% will provide the fastest transient response while a
setting of 10% will produce the lowest jitter. The default is 50%.
Changing DLC and PID Setting
Some caution must be considered while DLC is enabled and
when it is changed from enabled or disabled.
When operating, the controller IC uses the settings loaded in
its (volatile) RAM memory. When the input power is applied the
RAM settings are retrieved from the pin-strap resistors and the
two non-volatile memories (DEFAULT and USER). The
sequence is described in the "Initialization Procedure" section.
When DLC is enabled:
When DLC is enabled, the normal sequence (after input power
has been applied) that a value stored in the user non-volatile
memory overwrites any previously loaded value does not apply
for the PID setting (stored in the PID_TAPS register). The PID
setting in the user non-volatile memory is ignored and a non-
configurable default PID setting is loaded to RAM to act as a
safe starting value for the DLC. Once the output has been
enabled and the DLC algorithm has found a new optimized PID
setting, it will be loaded in RAM and used by the control loop.
When saving changes to the user non-volatile memory, all
changes made to the content of RAM will be saved. This also
includes the default PID setting (loaded to RAM to act as a
safe starting value) or the PID setting changed by the DLC
algorithm after enabling output. The result is that as long as
DLC is enabled the PID setting in the user non-volatile memory
is ignored, but it might accidentally get overwritten.
When changing DLC from disabled to enabled:
A non-configurable default PID setting is loaded to RAM to act
as a safe starting value for the DLC (same as above).
51
July 2019
July 2019
Advertisement
