Pcie Switch Configuration - GE IPN250RTM Hardware Reference Manual

NVMRO
Table 3-2 IPN250RTMA P8 Switch Assignments
P8
Function
Switch
1 NT_UPORT0
2
NT_UPORT1
3
NT_UPORT2
4 NT_UPORT4
NT_ENABLE~
5
6 EP_PCFG0~
7 EP_PCFG1
8
Unconnected
a. In the default build state of the IPN250, this also enables the non-transparent PCI to PCI bridge.
Upstream Port
Selection
Station 1 Port
Configuration
Publication No. IPN250RTM-HRM/2
CAUTION
If NVMRO is to be set elsewhere instead of on the IPN250RTM, ensure that the DIP switch/link is
set/left open.

3.1.2 PCIe Switch Configuration

LINK
Refer to Figure 1-1 for the location of the P8 switch bank.
The IPN250 includes a PCIe switch, some basic configuration of which can be
done using strapping options. These strapping options may be adjusted on the
IPN250RTM using the P8 DIP switches. Closing a switch takes the corresponding
function to the low (GND) state.
Description
Sets the Non-Transparent Upstream port (bit 0) - see below
Sets the Non-Transparent Upstream port (bit 1) - see below
Sets the Non-Transparent Upstream port (bit 2) - see below
Sets the Non-Transparent Upstream port (bit 4) - see below
Closed/linked = Non-transparent mode enabled
Open = Non-transparent mode disabled
Sets the port configuration for station 1 (bit 0) - see below
Sets the port configuration for station 1 (bit 0) - see below
Leave open
The upstream port is selected by the binary value set on switches 1 to 4 , e.g.
00000 = port 0
b
10000 = port 16
b
Where 0 = switch closed and 1 = switch open.
NOTE
Bit 3 of the port number cannot be set. It is always zero.
The station 1 port configuration is selected by the binary value set of switches 6
and 7, as follows:
00 = x16
b
01 = x4, x4, x4, x4
b
10 = x8, x4, x4
b
11 = x8, x8
b
Where 0 = switch closed and 1 = switch open.
NOTE
An inverter has been included on the bit 0 signal line to invert operation to that described for this bit
in the PCIe switch data sheet.
a
Associated
LED
DS33
DS32
DS31
DS30
DS29
DS28
DS27
-
Switches and LEDs 27