Infineon TLS820F3ELVxx Manual

Infineon TLS820F3ELVxx Manual

Optireg linear voltage regulator demoboard

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OPTIREG
linear voltage regulator TLS820F3ELVxx
demoboard
Z8F68163446

Preface

Scope and purpose
This document describes the usage of the OPTIREG
linear voltage regulator TLS820F3ELVxx demoboard for
the TLS820F3ELV33 and TLS820F3ELV50 from Infineon Technologies AG. Please also refer to the corresponding
datasheets.
Intended audience
This document is intended for engineers who develop applications.
User manual
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 1.0
www.infineon.com/OPTIREG-linear
2020-02-26

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Table of Contents
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Summary of Contents for Infineon TLS820F3ELVxx

  • Page 1: Preface

    ™ This document describes the usage of the OPTIREG linear voltage regulator TLS820F3ELVxx demoboard for the TLS820F3ELV33 and TLS820F3ELV50 from Infineon Technologies AG. Please also refer to the corresponding datasheets. Intended audience This document is intended for engineers who develop applications.
  • Page 2: Table Of Contents

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 Table of contents Table of contents Preface ................1 Table of contents .
  • Page 3: Introduction

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 1 Introduction Introduction General description The TLS820F3ELV33 and TLS820F3ELV50 are monolithic integrated low drop out voltage regulators for loads up to 200 mA in a PG-SSOP-14 package. With an input voltage range of 3 V to 42 V and very low quiescent current of only 26 µA, these devices are perfectly suitable for automotive or other supply systems connected to the...
  • Page 4: Block Diagram

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 1 Introduction Block diagram Current Limitation Enable RADJ Reset & Watchdog Bandgap Temperature Generator Reference Shutdown WINH Figure 1 Block diagram TLS820F3ELVxx User manual Rev. 1.0 2020-02-26...
  • Page 5: Demoboard

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 2 Demoboard Demoboard Assembly There are two different demoboard assemblies available. One for the TLS820F3ELV33 and one for the TLS820F3ELV50. They differ only by the resistor divider values on the RADJ pin, see...
  • Page 6: Operating Conditions

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 2 Demoboard Operating conditions To avoid electrical damage of the demoboard, the values in Table 1 must be maintained. Table 1 Limit values for operation Parameter Symbol Values Unit Note or condition Min.
  • Page 7: Configuration

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 2 Demoboard Configuration The demoboard can be easily configured via jumpers on the board. The board provides the following configuration options: • connect the enable signal EN to VIN or to GND with a jumper •...
  • Page 8: Radj Selection

    2 Demoboard 2.3.2 RADJ selection The TLS820F3ELVxx features adjustable reset thresholds. By applying a voltage divider between the Q pin and the RADJ-pin. The demoboard resistors R4 and R7 set the reset adjust threshold, see Figure 4. There are two...
  • Page 9 ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 2 Demoboard Figure 5 RADJ jumper User manual Rev. 1.0 2020-02-26...
  • Page 10: Signal Adaption

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 2 Demoboard 2.3.3 Signal adaption For easy signal adaption, for example connecting probes of an oscilloscope, test points are scattered across the PCB. The label of each test point indicates the probed signal. For further information on the mapping between...
  • Page 11: Schematic And Layout

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 3 Schematic and layout Schematic and layout Schematic The schematic for the TLS820F3ELV50 is assembled with two different configurations for the resistors R4 and R7, depending on whether the TLS820F3ELV33 or TLS820F3ELV50 is mounted, see Table 2 for details.
  • Page 12: Layout

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 3 Schematic and layout Layout The PCB uses a four layer standard stack-up. The product can also be soldered to double layer boards. However, four layers offer better thermal characteristics. The configuration on this demoboard is comparable to the 2s2p thermal interface situation.
  • Page 13 ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 3 Schematic and layout Figure 9 Internal layer 1 TLS820F3ELV50 User manual Rev. 1.0 2020-02-26...
  • Page 14 ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 3 Schematic and layout Figure 10 Internal layer 2 TLS820F3ELV50 User manual Rev. 1.0 2020-02-26...
  • Page 15 ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 3 Schematic and layout Figure 11 Bottom layer TLS820F3ELV50 User manual Rev. 1.0 2020-02-26...
  • Page 16: Bill Of Materials

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 4 Bill of materials Bill of materials The bill of materials shows the components on the TLS820F3ELV50. For the mounting condition of each component see Figure 7 Figure 8. Mechanical parts, such as connectors or test-points are not mentioned.
  • Page 17: Restrictions

    This demoboard offers limited features only for evaluation and testing of Infineon products. The demoboard is not an end product or finished appliance, nor is it intended or authorized by Infineon to be integrated into end products. The demoboard may not be used in any production system.
  • Page 18: Revision History

    ™ OPTIREG linear voltage regulator TLS820F3ELVxx demoboard Z8F68163446 6 Revision history Revision history Revision Date Changes 2020-02-26 Document created. User manual Rev. 1.0 2020-02-26...
  • Page 19: Disclaimer

    Infineon Technologies, All Rights Reserved. of any kind, including without limitation warranties of Infineon Technologies’ products may not be used in non-infringement of intellectual property rights of any any applications where a failure of the product or third party.

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