T0 Dpll; Table 4-1. Mapping Between Input Clock Software Fields And Ds3106 Register Fields; Table 4-2. Mapping Between T0 Dpll Software Fields And Ds3106 Register Fields - Microsemi DS3106DK Manual

_________________________________________________________________________________________ DS3106DK

Table 4-1. Mapping Between Input Clock Software Fields and DS3106 Register Fields

SOFTWARE FIELD
Input Clock Status LEDs 3 and 4
FREQ 3 and 4
LK MODE 3 and 4
SEL REF
FREQ (ppm)
PHASE (deg)
LEAKY BUCKET SETTINGS
8K Polarity
Freq Range Enable
4.3

T0 DPLL

The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE text box. The STATE and
SRFAIL buttons represent latched status bits in the device. When the button is red, the corresponding latched
status bit has been set in the DS3106. Pressing the button clears the latched status bit and changes the color of
the button back to green. The STATE button indicates that the state of the T0 DPLL has changed since the last
time the button was pressed. SRFAIL indicates that the selected reference has failed since the last time the button
was pressed. The state of the T0 DPLL can be forced using the combo box to the left of the STATE text box.
The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3106 T0 DPLL). The
acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set
by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0
DPLL's selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of
the main window), the SOFTLIM LED turns red.
When the Freerun Holdover box is checked, the T0 DPLL will holdover at 0ppm with respect to the REFCLK
oscillator rather than at the long-term frequency average of the last valid input clock. When the Freerun Holdover
box is not checked, holdover type can be set to instant or averaged. The PALARM status LED and the phase
detector 2 (PD2) fields are advanced topics. See

Table 4-2. Mapping Between T0 DPLL Software Fields and DS3106 Register Fields

SOFTWARE FIELD
STATE combo box
STATE status box
STATE latched status button
PALARM
SOFTLIM
AUTOBW
Freerun Holdover
Holdover Type
HO Ready
PD2 Enable
PD2G8K
DIVN
FREQ
ABW
LBW
DAMP
SRFAIL
LIMINT
PD2G
DS3106 REGISTER FIELDS
LED red when ACT = 1, LOCK = 0
LED green when ACT = 0, LOCK = 0
LED magenta when LOCK = 1
ICR3 and ICR4:FREQ[3:0]
ICR3 and ICR4:LOCK8K, and DIVN
FREQ1, FREQ2, and FREQ3 registers concatenated
PHASE1 and PHASE2 register concatenated
LBxU, LBxL, BLxS, LBxD (x = 1 to 4)
Table 4-2 and the DS3106 data sheet for more details.
DS3106 REGISTER FIELDS
Fixed by T0 DPLL architecture
ISR2 register
PTAB1:SELREF
DIVN1, DIVN2
TEST1:8KPOL
MCR1:FREN
MCR1:T0STATE
OPSTATE:T0STATE
T0ABW
T0LBW
T0CR2:DAMP
MSR2:STATE
MSR2:SRFAIL
TEST1:PALARM
OPSTATE:T0SOFT
MCR9:AUTOBW
MCR9:LIMINT
MCR3:FRUNHO
HOCR3:AVG
VALSR2:HORDY
T0CR3:PD2EN
T0CR3:PD2G
T0CR2:PD2G8K
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