Texas Instruments TPS7A3301EVM-061 User Manual page 4

Thermal Guidelines and Layout Recommendations
5.2 Output Load Transient
Figure 3 shows the load transient response (Vout - C1, yellow) for a full-load step transient from 100 mA
to 1 A (C3, blue). This test was run with the EVM set up for –5-V –VOUT and –VIN was set at –8 V.
6 Thermal Guidelines and Layout Recommendations
Thermal management is a key component of the design of any power converter and is especially
important when the power dissipation in the LDO is high. Use the following formula to approximate the
maximum power dissipation for the particular ambient temperature:
T T P
= +
J A D
where T is the junction temperature, T
J
device (watts), and θ
Celsius. The maximum silicon junction temperature, T
design must use copper trace and plane areas smartly, as thermal sinks, in order not to allow T
the absolute maximum rating under all temperature conditions and voltage conditions across the part. The
designer must consider carefully the thermal design of the PCB for optimal performance over temperature.
The actual allowable power dissipation on a PCB is a strong function of its layout.
Heat flows from the device to the ambient air through many paths, each of which represents resistance to
the heat flow; this resistance is called thermal resistance.
The total thermal resistance of a system is defined by
T T
(
-
J A
q =
JA
P
D
where θ is the thermal resistance (in °C/W), T
JA
°C), T is the maximum temperature of the ambient cooling air (in °C), and P
A
(heat) generated by the device (in W).
Whenever a heatsink is installed, the total thermal resistance (θ
resistances from the device, going through its case and heatsink to the ambient cooling air.
q = q + q
JA JC
Realistically, the user can only control two resistances, θ
θ , θ and θ
become the main design variables in selecting a heat sink.
JC CS SA
4
TPS7A3301EVM-061
Figure 3. Load Step and Transient Response
´ q
JA
is the ambient temperature, P
A
is the thermal resistance from junction to ambient. All temperatures are in degrees
JA
)
+ q
CS SA
Copyright © 2011, Texas Instruments Incorporated
is the power dissipation in the
D
, must not be allowed to exceed 150°C. The layout
J
Equation 4:
is the allowable junction temperature of the device (in
J
) is the sum of all the individual
JA
and θ . Therefore, for a device with a known
CS SA
www.ti.com
to exceed
J
is the amount of power
D
SLVU602 – November 2011
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C002
(3)
(4)
(5)