Philips SAA7102 Datasheet page 54

Philips Semiconductors
Digital video encoder
LOGIC
DATA BYTE
LEVEL
OHS
PHS
Table 89 Subaddresses 98H and 99H
DATA BYTE
HLEN
horizontal length;
Table 90 Subaddress 99H
DATA BYTE
IDEL input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received
valid pixel
Table 91 Subaddresses 9AH and 9CH
DATA BYTE
XINC
incremental fraction of the horizontal scaling engine;
Table 92 Subaddresses 9BH and 9CH
DATA BYTE
YINC
incremental fraction of the vertical scaling engine;
Table 93 Subaddresses 9DH and 9FH
DATA BYTE
YIWGTO
weighting factor for the first line of the odd field;
Table 94 Subaddresses 9EH and 9FH
DATA BYTE
YIWGTE
weighting factor for the first line of the even field;
2004 Mar 01
0 pin HSVGC is switched to input
1 pin HSVGC is switched to active output
0 polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
number of PIXCLKs
HLEN ---------------------------------------------------- - 1
=
DESCRIPTION
DESCRIPTION
–
line
DESCRIPTION
DESCRIPTION
XINC
DESCRIPTION
YINC
=
DESCRIPTION
YIWGTO =
DESCRIPTION
YIWGTE
54
Product specification
SAA7102; SAA7103
number of output pixels
------------------------------------------------------------- -
line
= ------------------------------------------------------------- -
number of input pixels
--------------------------------------------------------- -
line
number of active output lines
--------------------------------------------------------------------------- -
number of active input lines
YINC
+ 2048
------------- -
2
YINC YSKIP
–
=
------------------------------------- -
2
×
4096
×
4096