Philips SAA7102 Datasheet page 53

Philips Semiconductors
Digital video encoder
Table 87 Subaddress 96H
LOGIC
DATA BYTE
LEVEL
EFS
PCBN
SLAVE
ILC
YFIL
HSL
Table 88 Subaddress 97H
LOGIC
DATA BYTE
LEVEL
HFS
VFS
OFS
PFS
OVS
PVS
2004 Mar 01
0 frame sync signal at pin FSVGC ignored in slave mode
1 frame sync signal at pin FSVGC accepted in slave mode
0 normal polarity of CBO signal (HIGH during active video)
1 inverted polarity of CBO signal (LOW during active video)
0 the SAA7102; SAA7103 is timing master to the graphics controller
1 the SAA7102; SAA7103 is timing slave to the graphics controller
0 if hardware cursor insertion is active, set LOW for non-interlaced input signals
1 if hardware cursor insertion is active, set HIGH for interlaced input signals
0 luminance sharpness booster disabled
1 luminance sharpness booster enabled
0 normal trigger event handling of the horizontal state machine, if the SAA7102;
SAA7103 is slave to HSVGC input
1 trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted
to a late HSVGC in slave mode
0 horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
1 horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
0 vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
1 vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
0 pin FSVGC is switched to input
1 pin FSVGC is switched to active output
0 polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
0 pin VSVGC is switched to input
1 pin VSVGC is switched to active output
0 polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
DESCRIPTION
DESCRIPTION
53
Product specification
SAA7102; SAA7103