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Philips Semiconductors
Digital video encoder
Table 24 "ITU-R BT.601" signal component levels
COLOUR
Y
White
235
Yellow
210
Cyan
170
Green
145
Magenta
106
Red
81
Blue
41
Black
16
Note
1. Transformation:
a) R = Y + 1.3707 × (C
b) G = Y − 0.3365 × (C
c) B = Y + 1.7324 × (C
Table 25 Pin assignment for input format 0
8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED
RGB/C
PIN
CLOCK EDGE
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
2004 Mar 01
(1)
SIGNALS
C
C
R
G
B
R
128
128
235
235
16
146
235
235
166
16
16
235
54
34
16
235
202
222
235
16
90
240
235
16
240
110
16
16
128
128
16
16
− 128)
R
− 128) − 0.6982 × (C
B
− 128).
B
-Y-C
B
R
FALLING
RISING
CLOCK EDGE
G3/Y3
R7/C
G2/Y2
R6/C
G1/Y1
R5/C
G0/Y0
R4/C
B7/C
7
R3/C
B
B6/C
6
R2/C
B
B5/C
5
R1/C
B
B4/C
4
R0/C
B
B3/C
3
G7/Y7
B
B2/C
2
G6/Y6
B
B1/C
1
G5/Y5
B
B0/C
0
G4/Y4
B
Table 26 Pin assignment for input format 1
5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
B
PIN
235
PD7
16
PD6
235
PD5
16
PD4
235
PD3
16
PD2
235
PD1
16
PD0
Table 27 Pin assignment for input format 2
5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB
− 128)
R
PIN
PD7
PD6
PD5
PD4
PD3
PD2
7
R
PD1
6
R
PD0
5
R
4
R
Table 28 Pin assignment for input format 3
3
R
8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED C
2
R
1
R
PIN
0
R
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
35
SAA7102; SAA7103
FALLING
CLOCK EDGE
G2
G1
G0
B4
B3
B2
B1
B0
FALLING
CLOCK EDGE
G2
G1
G0
B4
B3
B2
B1
B0
FALLING
RISING
FALLING
CLOCK
CLOCK
EDGE
EDGE
n
n
C
7(0)
Y7(0)
B
C
6(0)
Y6(0)
B
C
5(0)
Y5(0)
B
C
4(0)
Y4(0)
B
C
3(0)
Y3(0)
B
C
2(0)
Y2(0)
B
C
1(0)
Y1(0)
B
C
0(0)
Y0(0)
B
Product specification
RISING
CLOCK EDGE
X
R4
R3
R2
R1
R0
G4
G3
RISING
CLOCK EDGE
R4
R3
R2
R1
R0
G5
G4
G3
-Y-C
B
R
RISING
CLOCK
CLOCK
EDGE
EDGE
n + 1
n + 1
C
7(0)
Y7(1)
R
C
6(0)
Y6(1)
R
C
5(0)
Y5(1)
R
C
4(0)
Y4(1)
R
C
3(0)
Y3(1)
R
C
2(0)
Y2(1)
R
C
1(0)
Y1(1)
R
C
0(0)
Y0(1)
R
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