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4 to 1,
44 to 41,
16 to 19
PD11 to
INPUT
PD0
FORMATTER
DECIMATOR
4 : 4 : 4 to 4 : 2 : 2
(OR BYPASS)
15
PIXCLKI
BORDER
GENERATOR
20
CGC
PIXCLKO
LOW-PASS
V
V
DDD2
DDA2
V
V
V
V
DDD1
SSD1
SSD2
DDA1
10
9
40
39
36
29
RGB LUT
(OR BYPASS)
HORIZONTAL
SCALER
VIDEO
ENCODER
OSCILLATOR/
DTO
23
35
34
XTALI
XTAL
TTX_SRES
FSVGC
27 MHz
Fig.1 Block diagram.
V
SSA1
TRST
RSET
TDO
DUMP
TDI
TCK
33
32
31
38
37
8
RGB TO Y-C
-C
B
CURSOR
MATRIX
INSERTION
(OR BYPASS)
VERTICAL
SCALER AND
FIFO
ANTI-FLICKER
FILTER
TRIPLE
DAC
SAA7102H
SAA7103H
2
TIMING
I
C-BUS
GENERATOR
CONTROL
13
14
21
22
24
12
11
VSVGC
HSVGC
SDA
RESET
SCL
CBO
TTXRQ_XCLKO2
TMS
7
6
R
30
BLUE_CB_CVBS
28
GREEN_VBS_CVBS
27
RED_CR_C
26
HSM_CSYNC
25
VSM
5
mhb963
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