Rgb Y-C B -C R Matrix; Horizontal Scaler; Vertical Scaler And Anti-Flicker Filter - Philips SAA7102 Datasheet

Philips Semiconductors
Digital video encoder
It can have any position in the bit map. The actual position
register describe the co-ordinates of the hot spot.
Again 0,0 is the upper left corner. While it is not possible to
move the hot spot beyond the left respectively upper
screen border this is perfectly legal for the right
respectively lower border. It should be noted that the
cursor position is described relative to the input resolution.
Table 4 Cursor bit map
BYTE D7 D6
0 row 0
column 3
1 row 0
column 7
2 row 0
column
11
... ...
6 row 0
column
27
7 row 0
column
31
... ...
254 row 31
column
27
255 row 31
column
31
Table 5 Cursor modes
CURSOR
PATTERN
CMODE = 0
00 second cursor colour second cursor colour
01 first cursor colour
10 transparent
11 inverted input
7.5 RGB Y-C -C matrix
B R
RGB input signals to be encoded to PAL or NTSC are
converted to the Y-C -C
B
colour difference signals are fed through low-pass filters
and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream
for further processing.
2004 Mar 01
D5 D4 D3 D2
row 0 row 0
column 2 column 1
row 0 row 0
column 6 column 5
row 0 row 0
column column 9
10
... ...
row 0 row 0
column column
26 25
row 0 row 0
column column
30 29
... ...
row 31 row 31
column column
26 25
row 31 row 31
column column
30 29
CURSOR MODE
CMODE = 1
first cursor colour
transparent
auxiliary cursor
colour
colour space in this block. The
R
The matrix and formatting blocks can be bypassed for
Y-C -C
B R
When the auxiliary VGA mode is selected, the output of the
cursor insertion block is immediately directed to the triple
DAC.
7.6

Horizontal scaler

The high quality horizontal scaler operates on the 4 : 2 : 2
data stream. Its control engines compensate the colour
D1 D0
phase offset automatically.
row 0
The scaler starts processing after a programmable
column 0
horizontal offset and continues with a number of input
row 0
pixels. Each input pixel is a programmable fraction of the
column 4
current output pixel (XINC/4096). A special case is
row 0 XINC = 0, this sets the scaling factor to 1.
column 8
If the SAA7102; SAA7103 input data is in accordance with
"ITU-R BT.656" , the scaler enters another mode. In this
...
event, XINC needs to be set to 2048 for a scaling factor
row 0 of 1. With higher values, upscaling will occur.
column
The phase resolution of the circuit is 12 bits, giving a
24
maximum offset of 0.2 after 800 input pixels. Small FIFOs
row 0
rearrange a 4 : 2 : 2 data stream at the scaler output.
column
28
7.7 Vertical scaler and anti-flicker filter
...
The functions scaling, Anti-Flicker Filter (AFF) and
row 31
re-interlacing are implemented in the vertical scaler.
column
Besides the entire input frame, it receives the first and last
24
lines of the border to allow anti-flicker filtering.
row 31
column The circuit generates the interlaced output fields by scaling
28
down the input frames with different offsets for odd and
even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off;
see Table 95.
The programming is similar to the horizontal scaler. For the
re-interlacing, the resolutions of the offset registers are not
sufficient, so the weighting factors for the first lines can
also be adjusted. YINC = 0 sets the scaling factor to 1;
YIWGTO and YIWGTE must not be 0.
Due to the re-interlacing, the circuit can perform upscaling.
The maximum factor depends on the setting of the
anti-flicker function and can be derived from the formulae
given in Section 7.17.
12
SAA7102; SAA7103
graphics input.
Product specification