Philips SAA7102 Datasheet page 43

Philips Semiconductors
Digital video encoder
Table 43 Subaddress 1BH
LOGIC
DATA BYTE
LEVEL
MSM 0
1
RCOMP 0
(read only)
1
GCOMP 0
(read only)
1
BCOMP 0
(read only)
1
Table 44 Subaddresses 26H and 27H
LOGIC
DATA BYTE
LEVEL
−
WSS
WSSON 0
1
Table 45 Subaddress 28H
LOGIC
DATA BYTE
LEVEL
−
BS
Table 46 Subaddress 29H
LOGIC
DATA BYTE
LEVEL
SRES 0
1
−
BE
2004 Mar 01
monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset
monitor sense mode on
check comparator at DAC on pin RED_CR_C is active, output is loaded
check comparator at DAC on pin RED_CR_C is inactive, output is not loaded
check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded
check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded
check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded
check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded
wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
wide screen signalling output is disabled; default after reset
wide screen signalling output is enabled
DESCRIPTION
starting point of burst in clock cycles
DESCRIPTION
pin TTX_SRES accepts a teletext bit
stream (TTX)
pin TTX_SRES accepts a sync reset input
(SRES)
ending point of burst in clock cycles
DESCRIPTION
DESCRIPTION
PAL: BS = 33 (21H); default after reset if
strapping pin 13 tied to HIGH
NTSC: BS = 25 (19H); default after reset if
strapping pin 13 tied to LOW
default after reset
a HIGH impulse resets synchronization of the
encoder (first field, first line)
PAL: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to HIGH
NTSC: BE = 29 (1DH); default after reset if
strapping pin FSVGC tied to LOW
43
Product specification
SAA7102; SAA7103
REMARKS
REMARKS