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Philips Semiconductors
Digital video encoder
Table 50 Subaddress 3AH
LOGIC
DATA BYTE
LEVEL
CBENB
0
1
SYMP
0
1
DEMOFF
0
1
CSYNC
0
1
Y2C
0
1
UV2C
0
1
Table 51 Subaddress 54H
LOGIC
DATA BYTE
LEVEL
VPSEN
0
1
EDGE2
0
1
EDGE1
0
1
Table 52 Subaddresses 55H to 59H
DATA BYTE
VPS5
fifth byte of video programming system data
VPS11
eleventh byte of video programming system data
VPS12
twelfth byte of video programming system data
VPS13
thirteenth byte of video programming system data
VPS14
fourteenth byte of video programming system data
2004 Mar 01
data from input ports is encoded
colour bar with fixed colours is encoded
horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default
after reset
horizontal and vertical trigger is decoded out of "ITU-R BT.656" compatible data at PD port
Y-C
-C
to RGB dematrix is active; default after reset
B
R
Y-C
-C
to RGB dematrix is bypassed
B
R
pin 26 provides a horizontal sync for non-interlaced VGA components output (at PIXCLK)
pin 26 provides a composite sync for interlaced components output (at XTAL clock)
input luminance data is twos complement from PD input port
input luminance data is straight binary from PD input port; default after reset
input colour difference data is twos complement from PD input port
input colour difference data is straight binary from PD input port; default after reset
video programming system data insertion is disabled; default after reset
video programming system data insertion in line 16 is enabled
internal PPD2 data is sampled on the rising clock edge
internal PPD2 data is sampled on the falling clock edge; see Tables 25 to 30; default after
reset
internal PPD1 data is sampled on the rising clock edge; see Tables 25 to 30; default after
reset
internal PPD1 data is sampled on the falling clock edge
DESCRIPTION
DESCRIPTION
DESCRIPTION
in line 16; LSB first; all other bytes are not
relevant for VPS
45
Product specification
SAA7102; SAA7103
REMARKS
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