Philips SAA7102 Datasheet page 52

Philips Semiconductors
Digital video encoder
Table 81 Subaddresses 81H to 83H
DATA BYTE
PCL defines the frequency of the synthesized pixel clock PIXCLKO;
f
PIXCLK
640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
Table 82 Subaddresses 90H and 94H
DATA BYTE
XOFS horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
Table 83 Subaddresses 91H and 94H
DATA BYTE
XPIX pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
Table 84 Subaddresses 92H and 94H
DATA BYTE
YOFSO vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
Table 85 Subaddresses 93H and 94H
DATA BYTE
YOFSE vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
Table 86 Subaddresses 95H and 96H
DATA BYTE
YPIX defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE − YOFSO
2004 Mar 01
 
PCL
× ×
f 8 ; f
= ---------- -
 
XTAL
XTAL
24
2
DESCRIPTION
= 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH;
DESCRIPTION
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Product specification
SAA7102; SAA7103