Philips SAA7102 Datasheet page 49

Philips Semiconductors
Digital video encoder
Table 65 Subaddress 6DH
DATA BYTE
VTRIG sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
Table 66 Subaddress 6EH
LOGIC
DATA BYTE
LEVEL
BLCKON 0
1
−
PHRES
−
LDEL
−
FLC
Table 67 Logic levels and function of PHRES
DATA BYTE
PHRES1 PHRES0
0 0
0 1
1 0
1 1
Table 68 Logic levels and function of LDEL
DATA BYTE
LDEL1 LDEL0
0 0
0 1
1 0
1 1
Table 69 Logic levels and function of FLC
DATA BYTE
FLC1 FLC0
0 0
0 1
1 0
1 1
2004 Mar 01
encoder in normal operation mode; default after reset
output signal is forced to blanking level
selects the phase reset mode of the colour subcarrier generator; see Table 67
selects the delay on luminance path with reference to chrominance path; see Table 68
field length control; see Table 69
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
49
Product specification
SAA7102; SAA7103