HP Net Vectra Technical Reference Manual page 19

Data Path
Level-2 Cache Memory
Controller
Main Memory Controller
support up to four ISA slots without any external buffering.
Storage elements are provided for bidirectional data buffering among the
64-bit PL data bus, the 64-bit memory data bus, and the 32-bit PCI address/
data bus. This buffering is used, partly, to smooth the differences in
bandwidths between the three buses, thereby improving the overall system
performance.
The Level-2 cache memory controller supports either write through or
write back direct mapped pipelined burst static RAM. On the HP Net Vectra
PC, 256KB of write back cache memory is implemented as two 32K
chips soldered on the system board. An 8-bit tag is implemented in a
separate 32K 8-bit, 15 ns static RAM, and allows the lowermost 64 MB of
main memory to be cached (if more than 64 MB of main memory is installed,
accesses to the uppermost regions will be made directly to the main memory
modules, and not via the cache memory mechanism).
The cache memory line width is 32-bytes (256-bits), four times the width of
the Processor-Local data bus. Reads and writes always involve a full cache
line, and so require four back-to-back cycles on the bus. Since they involve
accesses to related addresses, they do not need four independent accesses
to main memory, but can be organized as a pipelined burst. The second,
third and fourth cycles in each burst require less time to complete than the
first, the first cycle having included the addressing phase and memory pre-
charge timing. The read and write access timing has the pattern 3-1-1-1.
However, the timing for 64-byte burst reads can be even better than this (3-
1-1-1,1-1-1-1 for a back-to-back burst read) provided that the main memory
banks have been filled contiguously.
There are two programmable non-cacheable regions, with an option to
disable local memory in these regions. A 64 KB to 1 MB cache summary is
provided.
The main memory controller supports up to 384 MB of EDO, FPM or
SDRAM double interline memory modules (DIMMs). The HP Net Vectra PC
supports three modules of SDRAM (synchronous dynamic random access
memory). With the 64 MB module from HP, this gives a maximum total
capacity of 192 MB.
In the case of 66 MHz PL bus operation, memory accesses have a timing
pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss,
and to 11-2-2-2 for a page-miss. When the banks have been filled in an
2 System Board
Chip-Set
32-bit
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