Seco Qseven CQ7-D59 User Manual page 43

For rel. 2.0 / 2.1 compliant modules on 3.5” form factor

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PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair.

PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair.

PCIE0_CLK+ / PCIE0_CLK-: PCI Express Reference Clock for lane #0, Differential Pair.

PCIE_WAKE#: Board's Wake Input, it must be externally driven by the M.2 WWAN module inserted in the slot when it requires waking up the system.

PCIE_RST#: Reset Signal that is sent from Qseven

WWAN module. It is a +3.3V_ALW active-low signal.

PCIE0_CLOCK_REQUEST# PCI Express Clock Request Input. This signal shall be driven correctly by any module inserted in the M.2 WWAN slot, in order to ensure

that the PCI-e clock buffer available on the carrier board makes available the reference clock for the M.2 WWAN slot.

USB_P3+/ USB_P3-: Qseven

Module USB Port #3 differential pair

UIM_PWR: Power line for UIM module.

UIM_DATA: Bidirectional Data line between M.2 WWAN card and UIM module.

UIM_CLK: Clock line, output from M.2 WWAN card to the UIM module.

UIM_RESET: Reset signal line, sent from M.2 WWAN card to the UIM module.

Please be aware that all signals related to User Identity Modules are managed directly by the M.2 WWAN module circuitry, they don't involve neither carrier board's

nor Qseven

module's management. The CQ7-D59 carrier board embeds only clamping diodes for ESD protection on UIM signal and voltage lines.

CQ7-D59

module to all PCI-e devices available on the board (i.e. the optional additional GbE controller) and on the M.2

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