Motorola M5271EVB User Manual page 12

MCF5271 Microprocessor
• Three universal asynchronous receiver/transmitters (UARTs) with DMA support
• Inter-integrated circuit (I
• Queued serial peripheral interface (QSPI) module
• Hardware cryptography accelerator (optional)
— Random number generator
— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator
• Four channel 32-bit direct memory access (DMA) controller
• Four channel 32-bit input capture/output compare timers with optional DMA
support
• Four channel 16-bit periodic interrupt timers (PITs)
• Programmable software watchdog timer
• Interrupt controller capable of handling up to 126 interrupt sources
• Clock module with Phase Locked Loop (PLL)
• External bus interface module including a 2-bank synchronous DRAM controller
• 32-bit non-multiplexed bus with up to 8 chip select signals that support page-mode
FLASH memories
The MCF5271 communicates with external devices over a 32-bit wide data bus, D[31:0].
The MCF5271 can address a 32 bit address range. However, only 24 bits are available on
the external bus A[23:0]. There are internally generated chip selects to allow the full 32 bit
address range to be selected. There are regions that can be decoded to allow supervisor,
user, instruction, and data each to have the 32-bit address range.
All the processor's signals are available via daughter card expansion connectors. Refer to
the schematic (Appendix B) for their pin assignments.
The MCF5271 processor has the capability to support both BDM and JTAG. These ports
are multiplexed and together. In BDM mode it can be used with third party tools to allow
the user to download code to the board. In JTAG mode it can be used for boundary scan
operations. The board is configured to boot up in the normal/BDM mode of operation. The
BDM signals are available at the port labeled BDM.
Figure 1-2 shows the MCF5271 processor block diagram.
1-4
2
C) bus controller
M5271EVB User's Manual