Renesas IE850A User Manual page 34

E2, IE850A
5.4.22 Cautionary points regarding asynchronous debugging mode
In the asynchronous debugging mode, peripheral break functions cannot be used. Even if peripheral break
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functions are enabled, peripheral functions are not stopped.
In the asynchronous debugging mode, when any of CPUs is in the break state, no user system resets are
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acceptable.
During execution of a user program, there may be a case that the ECC error function does not normally
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operate for flash memory.
Example: When any CPU accesses flash memory during execution of a user program causing an ECC
error and another CPU which is in the break state accesses the same resources in the memory window at
the same timing, the debugger temporarily controls the ECC error and no ECC error occurs in any CPU.
5.4.23 Cautionary points regarding trace data acquired by software tracing (LPD output) [E2]
Table 5-3 shows the times required for the LPD output of software trace data generated by executing
debugging instructions. When this interval follows the execution of a debugging instruction, overflows (losses)
of software trace data can be avoided. Even if debugging instructions are executed in shorter intervals than
those listed, the device has an internal buffer for tracing and an overflow (a loss of data) will not occur
immediately; however, note that an overflow occurs if the internal buffer becomes full. For a DBPUSH
instruction, set the total number of registers to less than 5 to avoid an overflow.
Table 5-3 Interval between Execution of the Embedded Instruction and the LPD Output
Debugging Instruction
DBCP
DBTAG imm10
DBPUSH rh-rt
When the software tracing (LPD output) is in use, access to memory during the execution of a program,
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changes to event conditions, the reading of internal trace memory, and the display of state indicators such
as STOP are disabled.
A timestamp indicates the time that the E2 emulator acquires the software tracing data, not the time the
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instruction in the software being debugged was executed. The E2 emulator requires execution of the
program by the MCU to start only after it has started counting its timestamp values. Since the start of
counting of timestamp values cannot be precisely synchronized with the start of program execution, the
timestamps which have been added to the software tracing data stored from the head of the E2 storage
may include some errors.
When a break is generated as a forced break, a trace-full break from the E2 storage, or a break due to the
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input of an external trigger, information from a debugging instruction that was executed immediately before
the break will not be stored in the E2 storage.
When a debugging instruction is executed during single-stepped execution and a software break or
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hardware break is specified and executed by the debugging instruction, software trace data are not output
through the LPD interface.
When trace acquisition is stopped due to a break generated by a software break, hardware break, event
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break, or trace-full break from internal trace memory, the history of execution from a DBCP instruction
executed in the debugging area is stored as the final trace data in the E2 storage and internal trace
memory after the break in execution.
R20UT4140EJ0300 Rev.3.00
Oct.09.20
Interval between Execution of the Embedded Instruction (4-pin LPD (33 MHz))
1.727 usec
0.576 usec (without the PC value)
1.727 usec (One register is output without the PC value.)
5. Notes on Usage
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