Tews Technologies TXMC638 FPGA Manuals

Manuals and User Guides for Tews Technologies TXMC638 FPGA. We have 1 Tews Technologies TXMC638 FPGA manual available for free PDF download: User Manual

Tews Technologies TXMC638 User Manual (86 pages)

Reconfigurable FPGA with 24 x 16 Bit Analog Input

Brand: Tews Technologies | Category: Computer Hardware | Size: 2 MB

Table of Contents
4
Product Description
8
Figure 1-1 : Block Diagram
8
Technical Specification
9
Table 2-1 : Technical Specification
10
Handling and Operation Instruction
11
ESD Protection
11
Thermal Considerations
11
Assembling Hints
11
Pci Device Topology
12
Figure 4-1 : Pcie/Pci Device Topology
12
Table 4-1 : On-Board Pcie / Pci Devices
12
User FPGA (Kintex-7)
13
BCC (Board Configuration Controller) FPGA
13
PCI Configuration Registers (PCR)
13
PCI BAR Overview
13
Table 4-2 : Pci Configuration Registers
13
Table 4-3 : Pci Bar Overview
13
Local Configuration Register Space
14
Table 4-4 : Local Configuration Register Space
14
In-System Programming Data Space
15
Register Description
16
User FPGA (Kintex-7)
16
Board Configuration Controller (BCC - FPGA)
16
Interrupt Enable Register - 0Xc0
16
Interrupt Status Register - 0Xc4
16
Table 5-1 : Interrupt Enable Register
16
Table 5-2 : Interrupt Status Register
16
User FPGA Configuration Control/Status Register - 0Xd0
17
Table 5-3 : User Fpga Configuration Control/Status Register
17
User FPGA Configuration Data Register - 0Xd4
18
Table 5-4 : User Fpga Configuration Data Register
18
ISP Control Register - 0Xe0
19
ISP Configuration Register - 0Xe4
19
Table 5-5 : Isp Control Register
19
Table 5-6 : Isp Configuration Register
19
ISP Command Register - 0Xe8
20
ISP Status Register - 0Xec
20
Table 5-7 : Isp Command Register
20
Table 5-8 : Isp Status Register
20
TXMC638 Serial Number - 0Xf8
21
BCC - FPGA Code Version - 0Xfc
21
Table 5-9 : Txmc638 Serial Number
21
Table 5-10: Bcc - Fpga Code Version
21
Interrupts
22
Interrupt Sources
22
User FPGA (Kintex-7)
22
Board Configuration Controller (BCC - FPGA)
22
Interrupt Handling
22
Functional Description
23
User FPGA Block Diagram
23
Figure 7-1 : Fpga Block Diagram
23
User FPGA Highlights
24
Table 7-1 : Txmc638 Fpga Feature Overview
24
Table 7-2 : Fpga Bank Usage
24
User FPGA Gigabit Transceiver (MGT)
25
Figure 7-2 : Gtp Block Diagram
25
Table 7-3 : Mgt Connections
25
Table 7-4 : Multi Gigabit Transceiver Reference Clocks
26
User FPGA Configuration
27
Master Serial SPI Flash Configuration
27
Manually User FPGA SPI Flash Reconfiguration
28
Slave Select Map Configuration
29
Configuration Via JTAG
31
Figure 7-3 : User Jtag-Chain
31
Figure 7-4 : Tews Factory Jtag-Chain
31
Programming User FPGA SPI Configuration Flash
32
Erasing User FPGA SPI Configuration Flash
33
Sector Erasing User FPGA SPI Configuration Flash
34
Reading User FPGA SPI Configuration Flash
35
Board Configuration Controller (BCC - FPGA)
35
Clocking
36
FPGA Clock Sources
36
Figure 7-5 : Fpga Clock Sources
36
Table 7-5 : Available Fpga Clocks
37
Si514 Free Programming Clock Source
38
Table 7-6 : Fpga I2C Si514 Connections
38
Back I/O Interface
39
Table 7-7 : Digital Back I/O Interface
40
Memory
41
Ddr3 Sdram
41
Table 7-8 : Ddr3 Sdram Interface
42
SPI-Flash
44
I2C - Eeprom
44
I2C Calibration Data
44
Table 7-9 : Fpga Spi-Flash Connections
44
Table 7-10: Fpga I2C Eeprom Connections
44
ADC Calibration Data Values
45
Table 7-11: Adc Calibration Data Values
45
ADC Data Correction Formula
46
Serial ADC Interface
47
Overview
47
Figure 7-6 : Analog Input Section
47
Figure 7-7 : Analog Input Block Diagram
47
ADC Digital Output Coding
48
Table 7-12: Adc Data Coding Example
48
Table 7-13: Adc Data Coding
48
User FPGA Pinning
49
Table 7-14: Adc Interface Connections
52
Programming Hints LTC2323-16
53
Figure 7-8 : Digital Adc to Fpga Interface
53
Figure 7-9 : Timing Diagram Ltc2323-16
53
AC Coupled Differential Inputs
54
Figure 7-10: Block Diagram Differential Inputs
54
Table 7-15: Ac Coupled Differential Inputs
54
Serial Number Allocation
55
Device Addressing and Operation
55
Figure 7-11: Configuration Fpga Slave Address
55
Figure 7-12: Configuration Fpga Start and Stop Condition
55
Table 7-16: User Fpga I2C Interface to Configuration Fpga
55
Table 7-17: Txmc638 Serial Number
55
Read Operation
56
Write Operation
56
Figure 7-13: Configuration Fpga Output Acknowledge
56
Figure 7-14: Configuration Fpga Slave Access
56
On-Board Indicators
57
Table 7-18: Board-Status and User Leds
57
Thermal Management
58
Figure 7-15: Txmc638 with Heatsink
58
Design Help
59
Board Reference Design
59
Installation
60
I/O Interface
60
Front I/O - ADC Analog Input Level
60
Table 9-1 : Differential Input Voltage
60
Front I/O - AC Coupled Differential Inputs
62
Back I/O Interface
62
FPGA JTAG Connector
63
Figure 9-1 : Fpga Jtag Connector X4
63
Pin Assignment - I/O Connector
64
Overview
64
X1 Front Panel I/O Connector
65
Connector Type
65
Pin Assignment
65
Table 10-1: Pin Assignment Front Panel I/O Connector X1
66
Back I/O XMC Connector P14
67
Connector Type
67
Pin Assignment
67
Figure 10-1: Pin Assignment P14 Back I/O Connector Txmc638
68
P16 Back I/O Connector
69
Connector Type
69
Pin Assignment
69
Figure 10-2: Pin Assignment P16 Back I/O Connector Txmc638
69
X4 FPGA JTAG Header
70
Connector Type
70
Pin Assignment
70
Table 10-2: Pin Assignment Fpga Jtag Header X4
70

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I/O Systems Control Unit Computer Hardware Recording Equipment Controller

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Tews Technologies TXMC638 User Manual (86 pages)

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