Seco Smarc LEVY User Manual page 34

3.2.2.6 SPI interface signals
The signals related to SPI0 are as follows:
SPI0_CS0#: SPI primary Chip select, active low output signal. Electrical level +1.8V_RUN
SPI0_CS1#: SPI secondary Chip select, active low output signal. Electrical level +1.8V_RUN. This signal must be used only in case there are two SPI devices on
the carrier board, and the first chip select signal (SPI_CS0#) has already been used. It must not be used in case there is only one SPI device
SPI0_CK: SPI Clock Output to carrier board's SPI embedded devices. Electrical level +1.8V_RUN
SPI0_DIN: SPI0 Master Data Input, electrical level +1.8V_RUN. Input to i.MX 8M from SPI devices embedded on the Carrier Board.
SPI0_DO: SPI0 Master Data Output, electrical level +1.8V_RUN. Output from i.MX 8M to SPI devices embedded on the Carrier Board
The signals related to QuadSPI are as follows:
QSPI_CS0#: QuadSPI primary Chip select, active low output signal. Electrical level +1.8V_RUN.
QSPI_CK: QuadSPI Master Clock Output. Electrical level +1.8V_RUN. The reference timing signal for all the serial input and output operations
QSPI_IO_[0:3]: QuadSPI Master Data Bidirectional . Electrical level +1.8V_RUN. Data transfer between the master and slaves. In Single I/O mode, QSPI_IO_0 is the
QSPI master output/QSPI slave input (MOSI) whereas QSPI_IO_1 is the QSPI master input/QSPI slave output (MISO).
SPI interface can support speed up to 20MHz.
3.2.2.7 Audio interface signals
Here are following the signals related to I2S Audio interfaces:
The first I2S interface managed by the SAI2 group of signals of the SoC is always available on the edge pinout:
AUDIO_MCK: Master clock output to Audio codec. Output from the module to the Carrier board, electrical level +1.8V_RUN
I2S0_LRCK: Left& Right audio synchronization clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_RUN
I2S0_SDOUT: Digital audio Output. Output from the module to the Carrier board, electrical level +1.8V_RUN
I2S0_SDIN: Digital audio Input. Input from the module to the Carrier board, electrical level +1.8V_RUN
I2S0_CK: Digital audio clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_RUN
A second I2S interface managed by the SAI3 group of signals of the SoC is available by default on the edge pinout; as a factory alternative can be routed to the
BTLE module to support Bluetooth Audio.
I2S2_LRCK: Left& Right audio synchronization clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_RUN
I2S2_SDOUT: Digital audio Output. Output from the module to the Carrier board, electrical level +1.8V_RUN
I2S2_SDIN: Digital audio Input. Input from the module to the Carrier board, electrical level +1.8V_RUN
I2S2_CK: Digital audio clock. Bi-Directional between the module to the Carrier board, electrical level +1.8V_RUN
Signals routed to the Carrier Board have to be connected to I2S Audio Codecs. Please refer to the chosen Codec's Reference Design Guide for correct
LEVY
LEVY User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: S.O. - Reviewed by N.P. - Copyright © 2022 SECO S.p.A.
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