Mitsubishi A1SJH User Manual page 169

APPENDICES
Number Name
D9196
D9197
Faulty station
detection
D9198
D9199
Table 2.2 Special registers list (Continue)\
Description
• Bit which corresponds to faulty I/O module or remote
terminal module is set (1).
(Bit which corresponds to a faulty station is set when
normal communication cannot be restored after
executing the number of retries set at D9174.)
• If automatic online return is enabled, bit which
corresponds to a faulty station is reset (0) when the
Bit pattern of the faulty
station is restored to normal.
station
• Data configuration
Address
D9196
D9197
D9198
D9199
POINTS
(1) Special registers are cleared when the PC is switched off or the RESET switch
is set to LATCH CLEAR or RESET. Data remains unchanged when the RUN
key switch is set to STOP.
(2) The above special registers marked
remain unchanged after normal status is restored. For this reason, use one of
the following methods to clear the registers.
(a) Method by user program
Insert the circuit shown at right into
the program and turn on the clear
execution command contact to clear
the contents of register.
(b) Method by peripheral equipment
Set the register to "0" by changing the present value by the test function of
peripheral equipment or set to "0" by forced reset. For the operation
procedure, refer to the Instruction Manual for peripheral equipment.
(c) By moving the RESET key switch at the CPU front to the RESET position,
the special register is set to "0".
(3) Data is written to special registers marked
(4) Data is written to special registers marked
peripheral equipment.
Details
b15 b14 b13 b12 b11 b10 b9 b8 b7
Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion
16 15 14 13 12 11 10 9 8
Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion
32 31 30 29 28 27 26 25 24
Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion
48 47 46 45 44 43 42 41 40
Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion Stasion
64 63 62 61 60 59 58 57 56
1 above are latched and their data will
APP - 35
MELSEC-A
Applicable CPU
—
b6 b5 b4 b3 b2 b1 b0
Stasion Stasion Stasion Stasion Stasion Stasion Stasion
7 6 5 4 3 2 1
Stasion Stasion Stasion Stasion Stasion Stasion Stasion
23 22 21 20 19 18 17
Stasion Stasion Stasion Stasion Stasion Stasion Stasion
39 38 37 36 35 34 33
Stasion Stasion Stasion Stasion Stasion Stasion Stasion
55 54 53 52 51 50 49
1: Error
0: Normal
Clear execution
command
RST
Special function register to be cleared
2 above in the sequence program.
3 above in test mode of the
Usable with A2C
and A52G.
D9005