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(3) Timing Requirements
Table 5.7 and Figures 5.6 show timing requirements in memory expansion mode and microprocessor
mode.
Table 5.7 Timing requirements
Symbol
tsu(DB-RD)
Data input setup time
tsu(RDY-BCLK)
RDY* input setup time
tsu(HOLD-BCLK)
HOLD* input setup time
th(RD-DB)
Data input hold time
th(BCLK-RDY)
RDY* input hold time
th(BCLK-HOLD)
HOLD* input hold time
td(BCLK-HLDA)
HLDA* output delay time
Common to "with wait" and "no-wait" (actual MCU)
Common to "with wait" and "no-wait" (this product)
Figure 5.6 Timing requirements
* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.
Item
( 62 / 80 )
Vcc1 = Vcc2 = 3 V
Actual MCU
This product
[ns]
[ns]
Min.
Max.
Min.
65
50
55
40
50
65
0
See left
0
See left
0
See left
40
Max.
See left
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