Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
Page 3 User’s Manual µ PD789881 Subseries 8-Bit Single-Chip Microcontrollers µ PD789881 µ PD78F9882 µ PD789881(A) Document No. U15172EJ2V1UD00 (2nd edition) Date Published August 2005 N CP(K) 2002 Printed in Japan...
Page 4 [MEMO] User’s Manual U15172EJ2V1UD...
Page 5 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 6 EEPROM and FIP are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc.
Page 7 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of August, 2005. The information is subject to change without notice.
Page 8 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 9 Major Revisions in This Edition Pages Description Major revisions in modification version (U15172EJ2V1UD00) pp. 23, 24 CHAPTER 1 GENERAL • Addition of lead-free products p. 235 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS • Addition of soldering conditions of lead-free products in Table 21-1 Surface Mounting Type Soldering Conditions The mark shows major revised points.
Page 10 INTRODUCTION Target Readers This manual is intended to give user engineers an understanding of the functions of the µ PD789881 Subseries to design and develop its application systems and programs. Target products: µ µ • PD789881 Subseries: PD789881, 78F9882, 789881(A) Purpose This manual is designed to deepen your understanding of the following functions using the following organization.
Page 11 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ...
Page 12 Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 13: Table Of Contents
CONTENTS CHAPTER 1 GENERAL .......................... 23 Features ............................23 Applications ..........................23 Ordering Information ......................... 23 Quality Grade ..........................24 Pin Configuration (Top View) ....................25 78K/0S Series Lineup ........................ 27 Block Diagram..........................30 Overview of Functions ......................31 Differences Between Standard Quality Grade Products and (A) Products ......32 CHAPTER 2 PIN FUNCTIONS.......................
Page 14 3.1.1 Internal program memory space....................44 3.1.2 Internal data memory (internal high-speed RAM) space ...............45 3.1.3 Special function register (SFR) area .....................45 3.1.4 Data memory addressing ......................46 Processor Registers ........................48 3.2.1 Control registers ..........................48 3.2.2 General-purpose registers......................50 3.2.3 Special function registers (SFRs) ....................51 Instruction Address Addressing ....................54 3.3.1 Relative addressing........................54...
Page 15 Clock Generator Configuration ....................80 Registers Controlling Clock Generator ................... 82 System Clock Oscillators......................84 5.4.1 Main system clock oscillator......................84 5.4.2 Subsystem clock oscillator ......................84 5.4.3 Example of incorrect resonator connection ................... 85 5.4.4 Divider circuit ..........................86 ×4 subsystem clock multiplication circuit..................
Page 16 Watchdog Timer Operation .....................140 8.4.1 Operation as watchdog timer ......................140 8.4.2 Operation as interval timer ......................141 CHAPTER 9 SERIAL INTERFACE UART0 ..................142 Functions of Serial Interface UART0..................142 Configuration of Serial Interface UART0 ................143 Registers Controlling Serial Interface UART0 ..............144 Operation of Serial Interface UART0..................148 9.4.1 Operation stop mode........................148 9.4.2...
Page 17 13.4.3 Multiple interrupt servicing ......................195 13.4.4 Putting interrupt requests on hold ....................196 CHAPTER 14 STANDBY FUNCTION....................197 14.1 Standby Function and Configuration ..................197 14.2 Standby Function Operation ....................197 14.2.1 HALT mode setting and operation status ..................197 14.2.2 Releasing HALT mode ........................ 198 CHAPTER 15 RESET FUNCTION .......................200 15.1 Reset Types..........................200 15.2 Reset Processing Operation....................201...
Page 18 APPENDIX A DEVELOPMENT TOOLS....................236 Software Package ........................238 Language Processing Software .....................238 Control Software ........................239 Flash Memory Writing Tools ....................239 Debugging Tools (Hardware) ....................240 Debugging Tools (Software) ....................241 APPENDIX B REGISTER INDEX ......................242 Register Index (Alphabetic Order of Register Name)............242 Register Index (Alphabetic Order of Register Symbol)............245 User’s Manual U15172EJ2V1UD...
Page 19 LIST OF FIGURES (1/4) Figure No. Title Page I/O Circuit Types ............................40 µ Memory Map ( PD789881)..........................42 µ Memory Map ( PD78F9882) ......................... 43 µ Data Memory Addressing ( PD789881) ......................46 µ Data Memory Addressing ( PD78F9882) ...................... 47 Program Counter Configuration ........................
Page 20 LIST OF FIGURES (2/4) Figure No. Title Page Control Register Settings for Interval Timer Operation.................100 Configuration Diagram for Interval Timer .....................100 Interval Timer Operation Timing........................101 6-10 Control Register Settings for PPG Output Operation ...................102 6-11 Configuration of PPG Output........................103 6-12 PPG Output Operation Timing ........................103 6-13 Control Register Settings for Pulse-Width Measurement with Free-Running Counter...
Page 21 LIST OF FIGURES (3/4) Figure No. Title Page 7-11 Timing of Square-Wave Output Operation....................131 7-12 Description of 8-Bit Timer Control Register 5n Settings During PWM Output Operation ......132 7-13 Timing of PWM Output Operation (When Active Level = H) ................ 133 7-14 Timing of PWM Output Operation (When CR5n = 00H, Active Level = H)...........
Page 22 LIST OF FIGURES (4/4) Figure No. Title Page Multiplier Operation Timing (Example of AAH × D3H)..................180 11-3 12-1 Block Diagram of Power Supply Block ......................181 12-2 Connecting Capacitors ..........................182 13-1 Basic Configuration of Interrupt Function .....................185 13-2 Format of Interrupt Request Flag Registers ....................187 13-3 Format of Interrupt Mask Flag Registers......................188 13-4...
Page 23 LIST OF TABLES (1/2) Table No. Title Page Standard Quality Grade Products and (A) Products ..................32 Types of Pin I/O Circuits ..........................39 Internal ROM Capacity........................... 44 Vector Table ..............................44 Special Function Registers ..........................52 Port Functions..............................64 Configuration of Port ............................
Page 24 LIST OF TABLES (2/2) Table No. Title Page 10-6 Select and Deselect Voltages (COM0)......................171 10-7 Select and Deselect Voltages (COM0 to COM3) ..................174 13-1 Interrupt Source ............................184 13-2 Flags Corresponding to Interrupt Request Signal Name ................186 13-3 Time from Generation of Maskable Interrupt Request to Servicing..............193 14-1 Operation Statuses in HALT Mode.......................197 14-2...
Page 25: Chapter 1 General
CHAPTER 1 GENERAL Features • ROM and RAM capacities Item Program Memory Data Memory (ROM) Internal High-Speed LCD Display RAM Part Number µ 26 × 4 bits PD789881 Mask ROM 16 KB 512 bytes µ PD78F9882 Flash memory 32 KB µ...
Page 26: Quality Grade
CHAPTER 1 GENERAL Quality Grade Part Number Package Quality Grade µ 64-pin plastic LQFP (10 × 10) PD789881GB-×××-8EU Standard µ 64-pin plastic LQFP (10 × 10) PD78F9882GB-8EU Standard µ 64-pin plastic LQFP (10 × 10) PD789881GB-×××-8EU-A Standard µ 64-pin plastic LQFP (10 × 10) PD78F9882GB-8EU-A Standard µ...
Page 27: Pin Configuration (Top View)
CHAPTER 1 GENERAL Pin Configuration (Top View) 64-pin plastic LQFP (10 × 10) µ µ PD789881GB-×××-8EU PD789881GB-×××-8EU-A µ µ PD78F9882GB-8EU PD78F9882GB-8EU-A µ PD789881GB(A)-×××-8EU 63 62 61 60 59 58 57 56 55 54 53 52 51 50 CAPH2 CAPL2 P80/S15 CAPL1 P81/S16 CAPH1...
Page 28 CHAPTER 1 GENERAL Pin Name CAPH1, CAPL1: Voltage halver capacitance RESET: Reset CAPH2, CAPL2: LCD power supply capacitance control RxD0: Receive data COM0 to COM3: Common output S0 to S25: Segment output FPCLK: Flash clock input TI00, 01, 50, 51: Timer input Voltage halver capacitance TO00, 50, 51: Timer output...
Page 29: 0S Series Lineup
CHAPTER 1 GENERAL 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass Products under production development Y subseries supports SMB. Small-scale package, general-purpose applications µ µ PD789074 with subsystem clock added 44-pin PD789046...
Page 30 CHAPTER 1 GENERAL The major differences between subseries are shown below. Series for General-Purpose and LCD Drive Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity 8-Bit 16-Bit Watch WDT MIN.Value Subseries (Bytes) µ − − − PD789046 Small- 16 K 1 ch 1 ch 1 ch...
Page 31 CHAPTER 1 GENERAL Series for ASSP Function Timer 8-Bit 10-Bit Serial Interface Remarks Capacity 8-Bit 16-Bit Watch WDT MIN.Value Subseries (Bytes) µ − − − − − PD789803 8 K to 16 K 2 ch 1 ch 2 ch (USB: 1 ch) 3.6 V µ...
Page 32: Block Diagram
CHAPTER 1 GENERAL Block Diagram TI00/TO0/P30 16-bit timer/ Port 0 P00 to P03 event counter 0 TI01/P31 8-bit timer/ TI50/TO50/P32 Port 1 P10, P11 event counter 50 8-bit timer/ TI51/P33 TO51/P20 event counter 51 Port 2 P20 to P22 Watchdog timer 78K/0S (flash Port 3...
Page 33: Overview Of Functions
CHAPTER 1 GENERAL Overview of Functions µ µ PD789881 PD78F9882 Item Internal memory 16 KB 32 KB (flash memory) High-speed RAM 512 bytes 26 × 4 bytes LCD display RAM µ Minimum instruction execution time s (@500 kHz (TYP.) operation with main system clock) µ...
Page 34: Differences Between Standard Quality Grade Products And (A) Products
CHAPTER 1 GENERAL Differences Between Standard Quality Grade Products and (A) Products µ µ A more stringent quality assurance program is applied to the PD789881(A) than the PD789881 (standard quality grade product) (NEC classifies the former as a special quality grade product). µ...
Page 35: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS List of Pin Functions (1) Port pins Pin Name Function After Reset Alternate Function − P00 to P03 Port 0. Input 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register 0 (PUB0).
Page 36 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input External interrupt input for which the valid edge (rising edge, Input P30/TO0/TI00 falling edge, or both rising and falling edges) can be specified. INTP1 P31/TI01 INTP2 P32/TO50/TI50...
Page 37: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PUB0) in 1-bit units.
Page 38: P30 To P33 (Port 3)
CHAPTER 2 PIN FUNCTIONS 2.2.4 P30 to P33 (Port 3) These pins constitute a 4-bit I/O port. In addition, they also function as timer I/O and external interrupt input. Port 3 can be specified in the following operation modes in 1-bit units. (1) Port mode In this mode, P30 to P33 functions as a 4-bit I/O port.
Page 39: P90 To P95 (Port 9)
CHAPTER 2 PIN FUNCTIONS 2.2.7 P90 to P95 (Port 9) These pins function as a 6-bit I/O port. In addition, they also function as segment output. Port 9 can be specified in the following operation modes in 1-bit units. (1) Port mode These pins function as a 6-bit I/O port.
Page 40: Vss0 , Vss1
CHAPTER 2 PIN FUNCTIONS 2.2.16 V is the ground potential pin for ports. is the ground potential pin for other than ports. µ 2.2.17 V PD78F9882 only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified.
Page 41: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1.
Page 42 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (1/2) Type 2 Type 13-P Data IN/OUT Output N-ch disable Schmitt-triggered input with hysteresis characteristics. Input enable Type 5-H Type 13-Q Mask Pull-up P-ch option enable Data IN/OUT Output N-ch Data P-ch disable IN/OUT...
Page 43 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (2/2) Type 17-M Type 18-C Pull-up P-ch enable P-ch P-ch N-ch Data P-ch P-ch N-ch IN/OUT data N-ch P-ch Output N-ch disable P-ch N-ch N-ch Input enable P-ch N-ch data P-ch N-ch output disable...
Page 44: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE Memory Space µ PD789881 Subseries can access 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps. µ Figure 3-1. Memory Map ( PD789881) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM...
Page 45 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F9882) F F F F H Special function registers 256 × 8 bits F F 0 0 H F E F F H Internal high-speed RAM 512 × 8 bits F D 0 0 H F C F F H Reserved...
Page 46: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). µ PD789881 Subseries provides internal ROM (or flash memory) with the following capacity for each product. Table 3-1.
Page 47: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space µ PD789881 Subseries products incorporate the following RAM. (1) Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FD00H and FEFFH. The internal high-speed RAM is also used as a stack. (2) LCD display RAM LCD display RAM is incorporated in the area between FA00H and FA19H.
Page 48: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing µ PD789881 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area (FD00H to FFFFH) especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available.
Page 49 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Data Memory Addressing ( PD78F9882) F F F F H Special function registers SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H Short direct addressing Internal high-speed RAM...
Page 50: Processor Registers
CHAPTER 3 CPU ARCHITECTURE Processor Registers µ PD789881 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 51 CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-7. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10...
Page 52: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 53: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 54 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 55 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits − √ − FF70H 8-bit timer counter 50 TM50 − √ −...
Page 56: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 57: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 58: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 59: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 60: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 61: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 62: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8- bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 63: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 64: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored.
Page 65: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS Port Functions µ PD789881 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. The functions of each port are shown in Table 4-1. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 66: Port Configuration
CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P03 I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by means of pull-up resistor option register 0 (PUB0).
Page 67: Port 0
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 This is a 4-bit I/O port with an output latch. Port 0 can be specified in the input or output mode in 1-bit units by port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 0 (PUB0).
Page 68: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units by port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 1 (PUB1).
Page 69: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 This is a 3-bit I/O port with an output latch. Port 2 can be specified in the input or output mode in 1-bit units by port mode register 2 (PM2). When using the P20 to P22 pins as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 2 (PUB2).
Page 70 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 PUB2 PUB21 P-ch PORT Output latch P21/TxD0 (P21) PM21 Alternate function PUB2: Pull-up resistor option register 2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15172EJ2V1UD...
Page 71 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 PUB2 PUB22 P-ch Alternate function PORT Output latch P22/RxD0 (P22) PM22 PUB2: Pull-up resistor option register 2 Port mode register Port 2 read signal Port 2 write signal User’s Manual U15172EJ2V1UD...
Page 72: Port 3
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 This is a 4-bit I/O port with an output latch. Port 3 can be specified in the input or output mode in 1-bit units by port mode register 3 (PM3). When using the P30 to P33 pins as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 3 (PUB3).
Page 73 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P31 and P33 PUB3 PUB31, PUB33 P-ch Alternate function PORT Output latch (P31, P33) P31/INTP1/TI01 P33/INTP3/TI51 PM31, PM33 PUB3: Pull-up resistor option register 3 Port mode register Port 3 read signal Port 3 write signal User’s Manual U15172EJ2V1UD...
Page 74: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 This is a 4-bit N-ch open-drain I/O port with an output latch. Port 5 can be specified in the input or output mode in 1-bit units by port mode register 5 (PM5). For a mask ROM version, use of an on-chip pull-up resistor can be specified by a mask option.
Page 75: Port 8
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 8 This is a 5-bit I/O port with an output latch. Only the bits for which a port function is selected by port function register 8 (PF8) can be used. Port 8 can be specified in the input or output mode in 1-bit units by port mode register 8 (PM8). When the P80 to P84 pins are used as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 8 (PUB8).
Page 76: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 9 This is a 6-bit I/O port with an output latch. Only the bits for which a port function is selected by port function register 9 (PF9) can be used. Port 9 can be specified in the input or output mode in 1-bit units by port mode register 9 (PM9). When the P90 to P95 pins are used as input port pins, on-chip pull-up resistors can be specified in 1-bit units by pull-up resistor option register 9 (PUB9).
Page 77: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0 to PM3, PM5, PM8, PM9) • Pull-up resistor option registers (PUB0 to PUB3, PUB8, PUB9) • Port function registers (PF8, PF9) (1) Port mode registers (PM0 to PM3, PM5, PM8, PM9) Input and output can be specified in 1-bit units.
Page 78 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions PM×× P×× Pin Name Alternate Function Name TO51 Output × INTP0 Input Output × TI00 Input × INTP1 Input × TI01 Input × INTP2 Input TO50...
Page 79 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PUB0 to PUB3, PUB8, PUB9) These registers set whether to use on-chip pull-up resistors for pins P00 to P03, P10, P11, P20 to P22, P30 to P33, P80 to P84, and P90 to P95. An on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has been specified using PUB0 to PUB3, PUB8, and PUB9.
Page 80 CHAPTER 4 PORT FUNCTIONS (3) Port function registers (PF8, PF9) These registers set in 1-bit units whether to use port 8 and port 9 as port or segment pins. PF8 and PF9 can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 81: Port Function Operation
CHAPTER 4 PORT FUNCTIONS Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 82: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock oscillator This circuit oscillates a clock of 500 kHz (TYP.). Oscillation can be stopped by setting the processor clock control register (PCC).
Page 83 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator ×4 multiplication circuit Clock to peripheral Subsystem hardware clock Prescaler oscillator Main system Prescaler clock oscillator (ring oscillator) Standby Wait CPU clock controller controller CLS CSS0 MCC PCC1 Processor clock control Subclock control register (PCC) register (CSS)
Page 84: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR Registers Controlling Clock Generator The clock generator is controlled by the following two registers. • Processor clock control register (PCC) • Subclock control register (CSS) (1) Processor clock control register (PCC) This register is used to select the CPU clock and set the main system clock oscillator operation/stop. PCC can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 85 CHAPTER 5 CLOCK GENERATOR (2) Subclock control register (CSS) This register is used to select the CPU clock and specifies the CPU clock operation status. CSS can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSS to 00H. Figure 5-3.
Page 86: System Clock Oscillators
CHAPTER 5 CLOCK GENERATOR System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the internal ring oscillator (500 kHz (TYP.)). 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins.
Page 87: Example Of Incorrect Resonator Connection
CHAPTER 5 CLOCK GENERATOR 5.4.3 Example of incorrect resonator connection Figure 5-5 shows examples of incorrect resonator connection. Figure 5-5. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current...
Page 88: Divider Circuit
CHAPTER 5 CLOCK GENERATOR Figure 5-5. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched 5.4.4 Divider circuit The divider circuit divides the output of the subsystem clock oscillator (f ) to generate various clocks. ×4 subsystem clock multiplication circuit 5.4.5 This circuit multiplies the subsystem clock by four and supplies the resultant clock to the CPU and peripheral hardware.
Page 89: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The operation and function of the clock generator are determined by the processor clock control register (PCC) and subclock control register (CSS), as follows.
Page 90: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 91 CHAPTER 5 CLOCK GENERATOR <1> The CPU is reset when the RESET pin is made low on power application. When the RESET pin is later made high, an internal wait time of several seconds (refer to Table 5-3) elapses to ensure that subclock oscillation is stabilized.
Page 92: Chapter 6 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 16-bit timer/event counter 0 can be used for various functions including as an interval timer, external event counter, PPG output, for pulse width measurement (infrared ray remote control receive function), or square wave output of any frequency.
Page 93 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-1 shows the block diagram of 16-bit timer/event counter 0. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 0 Internal bus 16-bit capture/ compare control register 0 (CRC0) CRC02 CRC01 CRC00 INTTM00 16-bit capture/compare TI01/P31/INTP1 register 00 (CR00) Match...
Page 94: Configuration Of 16-Bit Timer/Event Counter 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Configuration of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 consists of the following hardware. Table 6-1. 16-Bit Timer/Event Counter 0 Configuration Item Configuration 16 bits × 1 (TM0) Timer register Capture/compare register: 16 bits × 2 (CR00 and CR01) Register Timer output 1 (TO0)
Page 95 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) 16-bit capture/compare register 00 (CR00) CR00 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of 16-bit capture/compare control register 0 (CRC0).
Page 96: 16-Bit Timer/Event Counter 0 Control Registers
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Cautions 1. Set a value other than 0000H in CR00 in the mode in which clear & start occurs on a match of TM00 and CR00. If CR00 is set to 0000H in the free-running mode and in the clear mode using the valid edge of the TI00 pin, an interrupt request (INTTM00) is generated when the value of CR00 changes from 0000H to 0001H following TM00 overflow (FFFFH).
Page 97 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer mode control register 0 (TMC0) This register is used to detect an overflow and to set the 16-bit timer operation mode, the 16-bit timer counter 0 clear mode, and output timing. TMC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 98 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) 16-bit capture/compare control register 0 (CRC0) This register is used to control the operation of the 16-bit capture/compare registers (CR00 and CR01). CRC0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0 to 00H.
Page 99 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter 0 output controller. It controls R-S type flip-flop (LV0) set/reset, output inversion enable/disable, and timer output enable/disable of 16-bit timer/event counter 0.
Page 100 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (4) 16-bit timer prescaler mode register 0 (PRM0) This register is used to set the count clock of 16-bit timer counter 0 (TM0) and the valid edge of the TI00 or TI01 input. PRM0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears PRM0 to 00H.
Page 101 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Cautions 1. To select the valid edge of TI00 as a count clock, do not set the mode in which the timer is cleared and started by the valid edge of TI00, and do not specify TI00 as a capture trigger. In this case, P30/TI00/TO0/INTP0 pin cannot also be used as a timer output (TO0).
Page 102: 16-Bit Timer/Event Counter 0 Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 16-Bit Timer/Event Counter 0 Operations 6.4.1 Interval timer operation Setting 16-bit timer mode control register 0 (TMC0) and 16-bit capture/compare control register 0 (CRC0) as shown in Figure 6-7 allows 16-bit timer/event counter 0 operate as an interval timer. Interrupt requests are generated repeatedly using the count value set in advance to 16-bit capture/compare register 00 (CR00) as the interval.
Page 103 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-9. Interval Timer Operation Timing Count clock TM0 count value 0000H 0001H 0000H 0001H 0000H 0001H Count start Clear Clear CR00 INTTM00 Interrupt request Interrupt request acknowledged acknowledged Interval time Interval time Interval time Interval time = (N + 1) ×...
Page 104: Ppg Output Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.2 PPG output operations Setting 16-bit timer mode control register 0 (TMC0) and 16-bit capture/compare control register 0 (CRC0) as shown in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, rectangular waves are output from the TO0/TI00/INTP0/P30 pin with the pulse width and the cycle that correspond to the count values preset in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/compare register 00 (CR00), respectively.
Page 105 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-11. Configuration of PPG Output 16-bit capture/compare register 00 (CR00) Clear 16-bit timer counter 0 circuit (TM0) TO0/TI00/INTP0/P30 16-bit capture/compare register 01 (CR01) Figure 6-12. PPG Output Operation Timing Count clock M − 1 N −...
Page 106: Pulse-Width Measurement Operations
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.3 Pulse-width measurement operations It is possible to measure the pulse width of the signal input to the TI00/TO0/P30/INTP0 pin and TI01/P31/INTP1 pin using 16-bit timer counter 0 (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/TO0/P30/INTP0 pin.
Page 107 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-14. Configuration Diagram for Pulse-Width Measurement by Free-Running Counter OVF0 16-bit timer counter 0 (TM0) Noise 16-bit capture/compare register 01 TI00/TO0/INTP0/P30 elimi- (CR01) nator INTTM01 Internal bus Figure 6-15. Timing of Pulse-Width Measurement Operation with Free-Running Counter and One Capture Register (When Both Edges Are Specified as Valid Edge) Count clock D0 −...
Page 108 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0 (TM0) is operated in free-running mode (see the register setting in Figure 6-16), it is possible to simultaneously measure the pulse widths of the signal input to the TI00/TO0/INTP0/P30 pin and TI01/INTP1/P31 pin.
Page 109 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 • Capture operation mode (free-running mode) The capture register operation when a capture trigger is input is shown below. Figure 6-17. CR01 Capture Operation When Rising Edge Is Specified as Valid Edge Count clock N −...
Page 110 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0 (TM0) is operated in free-running mode (see the register setting in Figure 6-19), it is possible to measure the pulse width of the signal input to the TI00/TO0/INTP0/P30 pin. When the edge specified by bits 4 and 5 (ES00 and ES01) of 16-bit timer prescaler mode register 0 (PRM0) is input to the TI00/TO0/INTP0/P30 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
Page 111 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-20. Timing of Pulse-Width Measurement Operation with Free-Running Counter and Two Capture Registers (When Rising Edge Is Specified as Valid Edge) Count clock TM0 count value 0000H 0001H D0 + 1 D1 + 1 FFFFH 0000H D2 + 1...
Page 112 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-21. Control Register Settings for Pulse-Width Measurement by Means of Restart (a) 16-bit timer mode control register 0 (TMC0) TMC02 TMC01 OVF0 TMC0 Clear & start mode at the TI00/TO0/INTP0/P30 pin valid edge (b) 16-bit capture/compare control register 0 (CRC0) CRC02 CRC01...
Page 113: External Event Counter Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/TO0/INTP0/P30 pin by 16-bit timer counter 0 (TM0). TM0 is incremented each time the specified valid edge is input to the TI00/TO0/INTP0/P30 pin when the valid edge of TI00 is selected as the count clock by 16-bit timer prescaler mode register 0 (PRM0).
Page 114 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Figure 6-24. Configuration Diagram for External Event Counter Internal bus 16-bit capture/compare register 00 (CR00) Match INTTM00 Clear Noise 16-bit timer counter 0 OVF0 Valid edge of TI00 elimi- (TM0) nator Figure 6-25. External Event Counter Operation Timing (When Rising Edge Is Specified as Valid Edge) TI00 pin input (after noise eliminated) N −...
Page 115: Square Wave Output Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 6.4.5 Square wave output operation This is an operation whereby a square wave of any selected frequency is output using the count value preset in 16- bit capture/compare register 00 (CR00). The TO0/TI00/INTP0/P30 pin output status is reversed at the intervals of the count value preset in CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of 16-bit timer output control register 0 (TOC0) to 1.
Page 116: Cautions For 16-Bit Timer/Event Counter 0 Operation
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 Cautions for 16-Bit Timer/Event Counter 0 Operation (1) Timer start errors An error of a maximum of one clock may occur in the time required for a match signal to be generated after timer start. This is because 16-bit timer counter 0 (TM0) is started asynchronously with the count pulse. Figure 6-28.
Page 117 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (5) Valid edge setting Set the valid edge of the TI00 and TI01 pins after the timer operation is stopped by clearing bits 2 and 3 (TMC01 and TMC02) of 16-bit timer mode control register 0 (TMC0) to 0, 0, respectively. The valid edges of the TI00 and TI01 pins are specified by setting bits 4 and 5 (ES00 and ES01) and bits 6 and 7 (ES10 and ES11) of 16-bit timer prescaler mode register 0 (PRM0).
Page 118 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (8) Timer operation (a) Even if 16-bit timer counter 0 (TM0) is read, the value is not captured in 16-bit capture/compare register 01 (CR01). (b) Regardless of the operation mode of the CPU, if the timer is stopped, the noise of the external input (TI00 or TI01) is not eliminated.
Page 119 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 (11) Edge detection (a) When the TI00 pin is high immediately after system reset, if the valid edge of TI00 pin is set to rising edge or both rising and falling edges and the operation of 16-bit timer counter 0 (TM0) is enabled, the rising edge will be detected immediately after these settings.
Page 120: Chapter 7 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output (1) 8-bit interval timer Interrupts are generated at preset time intervals.
Page 121 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit compare INTTM50 Selector register 50 (CR50) TI50/TO50/P32 Match 8-bit timer...
Page 122: Configuration Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 consist of the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Configuration 8 bits × 2 (TM50 and TM51) Timer register Compare register: 8 bits ×...
Page 123: 8-Bit Timer/Event Counters 50 And 51 Control Registers
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8-Bit Timer/Event Counters 50 and 51 Control Registers The following three registers are used to control 8-bit timer/event counters 50 and 51. • 8-bit timer clock select register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 124 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-4. Format of 8-Bit Timer Clock Select Register 51 Address: FF7AH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 TM51 count clock selection TI51 falling edge TI51 rising edge (131 kHz) (32.768 kHz) (2.048 kHz)
Page 125 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) This register is used to control the following five settings. <1> Control of 8-bit timer counter 5n (TM5n) count operation <2> Selection of 8-bit timer counter 5n (TM5n) operation mode <3>...
Page 126 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Cautions 1. Be sure to clear bits 4 and 5 to 0. 2. Bits 2 and 3 are write only. 3. Timer operation must be stopped before changing the operation mode by using bit 6. 4.
Page 127: 8-Bit Timer/Event Counters 50 And 51 Operations
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8-Bit Timer/Event Counters 50 and 51 Operations 7.4.1 Interval timer (8-bit) operation The 8-bit timer can operate as an interval timer by setting 8-bit timer mode control register 5n (TMC5n) as shown in Figure 7-7.
Page 128 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Timing of Interval Timer Operation (1/2) (a) Basic operation Count clock TM5n count value Clear Clear CR5n TCE5n Count starts INTTM5n Interrupt request Interrupt request acknowledged acknowledged TO5n Interval time Interval time Interval time (b) When CR5n = 00H...
Page 129 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Timing of Interval Timer Operation (2/2) (c) When CR5n = FFH Count clock TM5n CR5n TCE5n INTTM5n Interrupt request Interrupt request acknowledged acknowledged TO5n Interval time (d) Operation according to change of CR5n (M < N) Count clock TM5n N 00H...
Page 130 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Table 7-2. Interval Time of 8-Bit Timer/Event Counter 50 Minimum Interval Time Maximum Interval Time Resolution µ × 1/f µ 1/4f (7.62 (1.95 ms) 1/4f (7.62 µ µ × 1/f (30.5 (7.81 ms) (30.5 ×...
Page 131: External Event Counter Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5n by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified with 8-bit timer clock select register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 132: Square-Wave Output (8-Bit Resolution) Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output (8-bit resolution) operation The 8-bit timer operates as a square-wave output of any frequency using a count value preset in 8-bit compare register 5n (CR5n) as the interval. When bit 1 (TMC5n1) and bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) are set to 1, the output status of the TO5n pin is inverted at the interval time specified by the count value preset in CR5n.
Page 133 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Timing of Square-Wave Output Operation Count clock N − 1 N − 1 TM5n count value Count starts CR5n Note TO5n Note The initial value of the TO5n output can be specified by setting bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 134: 8-Bit Pwm Output Operations
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.4 8-bit PWM output operations The PWM output operation can be performed by setting 8-bit timer mode control register 5n (TMC5n) as shown in Figure 7-12. A pulse with a duty factor determined by the value preset in 8-bit compare register 5n (CR5n) is output from the TO5n pin.
Page 135 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Timing of PWM Output Operation (When Active Level = H) CR5n change (M → N) Count clock TM5n count value N + 2 N + 3 00 N + 1 CR5n TCE5n INTTM5n...
Page 136 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-15. Timing of PWM Output Operation (When CR5n = FFH, Active Level = H) Count clock 02 00 TM5n count value CR5n TCE5n INTTM5n OVF5n TO5n Inactive level Active level Active level Inactive level Inactive level Remark...
Page 137: Cautions For 8-Bit Timer/Event Counters 50 And 51 Operation
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Cautions for 8-Bit Timer/Event Counters 50 and 51 Operation (1) Timer start errors An error of a maximum of one clock may occur in the time required for a match signal to be generated after timer start.
Page 138: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM) (the watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer The watchdog timer is used to detect a program runaway.
Page 139: Watchdog Timer Configuration
CHAPTER 8 WATCHDOG TIMER Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer Clock Divider Divider...
Page 140: Watchdog Timer Control Registers
CHAPTER 8 WATCHDOG TIMER Watchdog Timer Control Registers The watchdog timer is controlled by the following two registers. • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) (1) Watchdog timer clock select register (WDCS) This register sets the watchdog timer count clock. WDCS can be set by an 8-bit memory manipulation instruction.
Page 141 CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 8-3.
Page 142: Watchdog Timer Operation
CHAPTER 8 WATCHDOG TIMER Watchdog Timer Operation 8.4.1 Operation as watchdog timer The watchdog timer detects a program runaway when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The runaway detection time interval of the watchdog timer can be selected by bits 0 to 2 (WDCS0 to WDCS2) of watchdog timer clock select register (WDCS).
Page 143: Operation As Interval Timer
CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a preset count value.
Page 144: Chapter 9 Serial Interface Uart0
CHAPTER 9 SERIAL INTERFACE UART0 Functions of Serial Interface UART0 The serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial transfer is not performed to reduce power consumption. For details, see 9.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode In this mode, one byte of data starting with the start bit is transmitted/received, and full-duplex operation is possible.
Page 145: Configuration Of Serial Interface Uart0
CHAPTER 9 SERIAL INTERFACE UART0 Configuration of Serial Interface UART0 The serial interface UART0 consists of the following hardware. Table 9-1. Configuration of Serial Interface UART0 Item Configuration Registers Transmit shift register 0 (TXS0) Receive shift register 0 (RXS0) Receive buffer register 0 (RXB0) Control registers Asynchronous serial interface mode register 0 (ASIM0) Asynchronous serial interface status register 0 (ASIS0)
Page 146: Registers Controlling Serial Interface Uart0
CHAPTER 9 SERIAL INTERFACE UART0 Registers Controlling Serial Interface UART0 The serial interface UART0 is controlled by the following three registers. • Asynchronous serial interface mode register 0 (ASIM0) • Asynchronous serial interface status register 0 (ASIS0) • Baud rate generator control register 0 (BRGC0) (1) Asynchronous serial interface mode register 0 (ASIM0) This is an 8-bit register that sets UART operation enable/disable and controls the serial transfer operation of the UART interface.
Page 147 CHAPTER 9 SERIAL INTERFACE UART0 Figure 9-2. Format of Asynchronous Serial Interface Mode Register 0 Address: FF90H After reset: 01H Symbol <7> <6> <5> ASIM0 POWER ISRM POWER Specifies operation mode Operation disabled (internal circuit reset asynchronously) Operation enabled Operation mode Function of RxD0/P22 pin Function of TxD0/P21 pin Operation stops...
Page 148 CHAPTER 9 SERIAL INTERFACE UART0 (2) Asynchronous serial interface status register 0 (ASIS0) This register indicates the error contents when a receive error occurs in the UART mode. ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input clears ASIS0 to 00H. Figure 9-3.
Page 149 CHAPTER 9 SERIAL INTERFACE UART0 Figure 9-4. Format of Baud Rate Generator Control Register 0 Address: FF91H After reset: 1FH Symbol BRGC0 TPS1 TPS0 MDL4 MDL3 MDL2 MDL1 MDL0 TPS1 TPS0 Selects input clock (f XCLK (131 kHz) (32.768 kHz) /2 (16.4 kHz) (8.2 kHz) MDL4...
Page 150: Operation Of Serial Interface Uart0
CHAPTER 9 SERIAL INTERFACE UART0 Operation of Serial Interface UART0 The two serial interface UART0 modes are described below. 9.4.1 Operation stop mode Since serial transfer is not performed in this mode, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. (1) Register setting The operation stop mode can be set by asynchronous serial interface mode register 0 (ASIM0).
Page 151: Asynchronous Serial Interface (Uart) Mode
CHAPTER 9 SERIAL INTERFACE UART0 9.4.2 Asynchronous serial interface (UART) mode In this mode, one byte of data starting with the start bit is transmitted/received, and full-duplex operation is possible. A UART-dedicated baud rate generator is incorporated, allowing communication over a wide range of baud rates. (1) Register setting The UART mode is set by using asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and baud rate generator control register 0 (BRGC0).
Page 152 CHAPTER 9 SERIAL INTERFACE UART0 Address: FF90H After reset: 01H Symbol <7> <6> <5> ASIM0 POWER ISRM POWER Specifies operation mode Operation disabled (internal circuit reset asynchronously) Operation enabled Operation mode Function of RxD0/P22 pin Function of TxD0/P21 pin Operation stops Port function (P22) Port function (P21) UART mode (receive only)
Page 153 CHAPTER 9 SERIAL INTERFACE UART0 (b) Asynchronous serial interface status register 0 (ASIS0) ASIS0 can be read by an 8-bit memory manipulation instruction. RESET input clears ASIS0 to 00H. Address: FF93H After reset: 00H Symbol ASIS0 Parity error flag Parity error does not occur. Parity error occurs (specified parity of transmit data does not match receive data parity).
Page 154 CHAPTER 9 SERIAL INTERFACE UART0 (c) Baud rate generator control register 0 (BRGC0) BRGC0 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets BRGC0 to 1FH. Address: FF91H After reset: 1FH Symbol BRGC0 TPS1 TPS0 MDL4 MDL3 MDL2...
Page 155 CHAPTER 9 SERIAL INTERFACE UART0 (2) Baud rate setting The transmit/receive clock for the baud rate to be generated is obtained by dividing the subsystem clock. (a) Generating transmit/receive clock for baud rate from subsystem clock The transmit/receive clock is generated by dividing the subsystem clock. The baud rate generated from the subsystem clock can be calculated from the following expression.
Page 156 CHAPTER 9 SERIAL INTERFACE UART0 (c) Error torelance range for baud rate The tolerance range for the baud rate depends on the number of bits per frame and the counter’s division ratio (k). Transmission/reception can be performed normally if the difference between the baud rate error at the reception side and the baud rate error at the transmission side is within this tolerance range.
Page 157 CHAPTER 9 SERIAL INTERFACE UART0 (3) Communication operation (a) Data format Figure 9-6 shows the transmit/receive data format. Figure 9-6. Asynchronous Serial Interface Transmit/Receive Data Format 1 data frame Start Parity Stop bit Character bit One data frame consists of the following bits. •...
Page 158 CHAPTER 9 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 159 CHAPTER 9 SERIAL INTERFACE UART0 (c) Transmission Transmit operation is enabled when bit 7 (TXE0) of asynchronous serial interface mode register 0 (ASIM0) is set to 1, and is started when transmit data is written to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit(s) are added automatically.
Page 160 CHAPTER 9 SERIAL INTERFACE UART0 (d) Reception When bit 5 (RXE) of asynchronous serial interface mode register 0 (ASIM0) is set to 1, a receive operation is enabled and sampling of the RxD0 pin input is performed. RxD0 pin input sampling is performed using the serial clock specified by ASIM0. When the RxD0 pin input becomes low, the 5-bit counter of the baud rate generator starts counting, and at the time when the half time determined by the specified baud rate has passed, the data sampling start timing signal is output.
Page 161 CHAPTER 9 SERIAL INTERFACE UART0 (e) Receive errors Three types of errors can be generated during a receive operation: a parity error, a framing error, and an overrun error. If, as the result of data receive, an error flag is set in asynchronous serial interface status register 0 (ASIS0), a receive error interrupt request (INTSRE0) is generated.
Page 162: Chapter 10 Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.1 LCD Controller/Driver Functions µ The functions of the LCD controller/driver of the PD789881 Subseries are as follows. (1) Automatic output of segment and common signals based on automatic display data memory read (2) Two different display modes: •...
Page 163 CHAPTER 10 LCD CONTROLLER/DRIVER The correspondence with the LCD display RAM is shown in Figure 10-1 below. Figure 10-1. Correspondence with LCD Display RAM Address Segment → S25 Note FA19H → S24 Note FA18H → S23 Note FA17H → S22 Note FA16H →...
Page 164 Figure 10-2. Block Diagram of LCD Controller/Driver Internal bus LCD display mode LCD clock control Display data register 0 (LCDC0) register 0 (LCDM0) memory P9× P8× F×××H F×××H F×××H LCDC01 LCDC00 LCDON0 LIPS0 LCDM0 output latch output latch 3 2 1 0 3 2 1 0 3 2 1 0 Port function...
Page 165 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-3. Connection Example of LCD Drive Pin (a) 1/4 duty, 1/3 bias, etc. CAPH2 µ 0.47 F CAPL2 µ 0.47 F µ 0.47 F (b) Static mode CAPH2 Open CAPL2 Open User’s Manual U15172EJ2V1UD...
Page 166: Registers Controlling Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.3 Registers Controlling LCD Controller/Driver • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • Port function registers 8 and 9 (PF8 and PF9) (1) LCD display mode register 0 (LCDM0) This register specifies whether to enable display operation.
Page 167 CHAPTER 10 LCD CONTROLLER/DRIVER (2) LCD clock control register 0 (LCDC0) This register specifies the LCD clock. The frame frequency is determined depending on the LCD clock and number of time divisions. LCDC0 can be set by an 8-bit memory manipulation instruction. RESET input clears LCDC0 to 00H.
Page 168 CHAPTER 10 LCD CONTROLLER/DRIVER (3) Port function registers (PF8, PF9) These registers set in 1-bit units whether to use port 8 and port 9 as port or segment pins. PF8 and PF9 can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 169: Setting Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set the LCD display data memory (FA00H to FA19H) to the default value. <2> Set the pins used for segment output by using the port function registers (PF8 and PF9). <3>...
Page 170: Common And Segment Signals
CHAPTER 10 LCD CONTROLLER/DRIVER 10.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V ). It turns off when the potential difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it.
Page 171 CHAPTER 10 LCD CONTROLLER/DRIVER (3) Output waveforms of common and segment signals Voltages listed in Table 10-5 are output as common and segment signals. When both common and segment signals are at the select voltage, a display-on voltage of ±V is obtained.
Page 172: Static Display Example
CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-9. Voltages and Phases of Common and Segment Signals (a) Static display mode Select Deselect Common signal Segment signal T: One LCD clock period (b) 1/3 bias mode Select Deselect Common signal Segment signal T: One LCD clock period User’s Manual U15172EJ2V1UD...
Page 173: Display Modes
CHAPTER 10 LCD CONTROLLER/DRIVER 10.7 Display Modes 10.7.1 Static display example Figure 10-11 shows how the three-digit LCD panel having the display pattern shown in Figure 10-10 is connected µ to the segment signals (S0 to S23) and the common signal (COM0) of the PD789881 Subseries chip.
Page 174 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-11. Example of Connecting Static LCD Panel COM 3 COM 2 Can be connected together COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 S 15 S 16 FA10H S 17 S 18 S 19...
Page 175 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-12. Static LCD Drive Waveform Examples COM0 COM0-S11 −V COM0-S12 −V User’s Manual U15172EJ2V1UD...
Page 176: Four-Time Slot Display Example
CHAPTER 10 LCD CONTROLLER/DRIVER 10.7.2 Four-time slot display example Figure 10-14 shows how the 13-digit LCD panel having the display pattern shown in Figure 10-13 is connected to µ the segment signals (S0 to S25) and the common signals (COM0 to COM3) of the PD789881 Subseries chip.
Page 177 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-14. Example of Connecting Four-Time Slot LCD Panel COM 3 COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 S 15 S 16 FA10H S 17 S 18 S 19 S 20 S 21...
Page 178 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-15. Four-Time Slot LCD Drive Waveform Examples (1/3 Bias Mode) COM0 COM1 COM2 COM3 +1/3V COM0-S14 −1/3V −V +1/3V COM1-S14 −1/3V −V Remark The waveforms of COM2-S14 and COM3-S14 are omitted. User’s Manual U15172EJ2V1UD...
Page 179: Chapter 11 Multiplier
CHAPTER 11 MULTIPLIER 11.1 Multiplier Function The multiplier has the following function. • Calculation of 8 bits × 8 bits = 16 bits 11.2 Multiplier Configuration (1) 16-bit multiplication result storage register 0 (MUL0) This register stores the 16-bit result of multiplication. This register holds the result of multiplication after 16 CPU clocks have elapsed.
Page 180 CHAPTER 11 MULTIPLIER Figure 11-1. Block Diagram of Multiplier Internal bus Multiplication data Multiplication data register A (MRA0) register B (MRB0) Counter value CPU clock Selector 3-bit counter Start Clear 16-bit adder 16-bit multiplication result storage register 0 (Master) (MUL0) 16-bit multiplication result storage register 0 (Slave) Reset...
Page 181: Multiplier Control Register
CHAPTER 11 MULTIPLIER 11.3 Multiplier Control Register The multiplier is controlled by the following register. • Multiplier control register 0 (MULC0) (1) Multiplier control register 0 (MULC0) This register indicates the operating status of the multiplier after operation, as well as controls the multiplier. MULC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 182: Multiplier Operation
CHAPTER 11 MULTIPLIER 11.4 Multiplier Operation The multiplier of the µPD789881 Subseries can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 11-3 shows the operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H. <1>...
Page 183: Chapter 12 Voltage Halver Circuit And Regulator Circuit
CHAPTER 12 VOLTAGE HALVER CIRCUIT AND REGULATOR CIRCUIT µ Note PD789881 Subseries has a voltage halver circuit and a regulator circuit in its power supply block. These circuits allow the device to operate on an internal voltage lower than V and to realize ultra-low power consumption.
Page 184 CHAPTER 12 VOLTAGE HALVER CIRCUIT AND REGULATOR CIRCUIT µ Connect 0.47 F capacitors to the pins of the power supply block (CAPL1, CAPH1, HV , and VR pins). Figure 12-2 illustrates how to connect the capacitors. Figure 12-2. Connecting Capacitors CAPL1 µ...
Page 185: Chapter 13 Interrupt Functions
CHAPTER 13 INTERRUPT FUNCTIONS 13.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated.
Page 186 CHAPTER 13 INTERRUPT FUNCTIONS Table 13-1. Interrupt Source Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Table Basic External Address Configuration Name Trigger Note 2 Type − Note 3 Non-maskable INTWDT Watchdog timer overflow (with Internal 0004H watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow (with...
Page 187 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus INTM0, INTM1...
Page 188: Registers Controlling Interrupt Function
CHAPTER 13 INTERRUPT FUNCTIONS 13.3 Registers Controlling Interrupt Function The following four types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0 and IF1) • Interrupt mask flag registers (MK0 and MK1) • External interrupt mode registers (INTM0 and INTM1) •...
Page 189 CHAPTER 13 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0, IF1) An interrupt request flag is set to 1 when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared to 0 when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed.
Page 190 CHAPTER 13 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0, MK1) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 and MK1 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. Figure 13-3.
Page 191 CHAPTER 13 INTERRUPT FUNCTIONS (3) External interrupt mode registers (INTM0, INTM1) These registers are used to specify the valid edge for INTP0 to INTP3. INTM0 and INTM1 can be set by an 8-bit memory manipulation instruction. RESET input clears these registers to 00H. Figure 13-4.
Page 192 CHAPTER 13 INTERRUPT FUNCTIONS (4) Program status word (PSW) The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. PSW can be read and written in 8-bit units, and can be manipulated by using bit manipulation instructions and dedicated instructions (EI and DI).
Page 193: Interrupt Servicing Operation
CHAPTER 13 INTERRUPT FUNCTIONS 13.4 Interrupt Servicing Operation 13.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to PC, and then program execution branches.
Page 194 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-6. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT:...
Page 195: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 13 INTERRUPT FUNCTIONS 13.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 196 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13-10. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Saving PSW and PC, and MOV A, r Interrupt servicing program jump to interrupt servicing Interrupt If the interrupt request has generated an interrupt request flag (××IF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n −...
Page 197: Multiple Interrupt Servicing
CHAPTER 13 INTERRUPT FUNCTIONS 13.4.3 Multiple interrupt servicing Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to Table 13-1).
Page 198: Putting Interrupt Requests On Hold
CHAPTER 13 INTERRUPT FUNCTIONS 13.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
Page 199: Chapter 14 Standby Function
CHAPTER 14 STANDBY FUNCTION 14.1 Standby Function and Configuration µ The standby function is to reduce the power consumption of the system and the PD789881 Subseries supports only the HALT mode. (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 200: Releasing Halt Mode
CHAPTER 14 STANDBY FUNCTION 14.2.2 Releasing HALT mode The HALT mode can be released by the following three types of sources. (1) Releasing by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If the interrupt is enabled to be acknowledged, vectored interrupt servicing is performed.
Page 201 CHAPTER 14 STANDBY FUNCTION (3) Releasing by RESET input When the RESET signal is input, the HALT mode is released, and then, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 14-2.
Page 202: Chapter 15 Reset Function
CHAPTER 15 RESET FUNCTION 15.1 Reset Types The following two operations are available to generate reset signals. (1) External reset input by RESET pin (2) Internal reset by watchdog timer program loop time detection Figure 15-1. Block Diagram of Reset Function RESET Reset signal Reset controller...
Page 203: Reset Processing Operation
CHAPTER 15 RESET FUNCTION 15.2 Reset Processing Operation There is no functional difference between an external reset and an internal reset. Both the reset operations start execution of the program from the address written to addresses 0000H and 0001H when the reset signal is input. Upon reset, each hardware is in the status shown in Table 15-1.
Page 204 CHAPTER 15 RESET FUNCTION Figure 15-2. Timing of Reset by RESET Input Note Main oscillation stops Main system clock Subsystem clock Internal reset Reset Normal operation Wait period During normal operation wait period (reset processing) period (approx. 0.5 s) (see Table 5-3) RESET Internal reset signal Delay...
Page 205 CHAPTER 15 RESET FUNCTION Figure 15-3. Timing of Reset by Overflow of Watchdog Timer Note Main system clock Subsystem clock Internal reset Normal operation Reset Wait period During normal operation wait period (reset processing) period (approx. 0.5 s) (see Table 5-3) Overflow of watchdog timer Internal reset signal...
Page 206 CHAPTER 15 RESET FUNCTION Figure 15-4. Timing of Reset by RESET Input on Power Application Power application Main oscillation stops Main system clock Driven on V voltage Driven on regulator voltage until reset is released after reset has been released Subsystem clock Internal reset wait period Normal operation...
Page 207 CHAPTER 15 RESET FUNCTION Table 15-1. Status of Hardware After Reset Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose registers...
Page 208: Chapter 16 Μ Pd78F9882
µ CHAPTER 16 PD78F9882 µ µ PD78F9882 is provided as the flash memory version of the PD789881 Subseries. µ The differences between the PD78F9882 and the mask ROM version are shown in Table 16-1. µ Table 16-1. Differences Between PD78F9882 and Mask ROM Version Item Flash Memory Version Mask ROM Version...
Page 209: Flash Memory Characteristics
µ CHAPTER 16 PD78F9882 16.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- µ PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the PD78F9882 mounted on the target system (on-board).
Page 210: Communication Mode
µ CHAPTER 16 PD78F9882 16.1.2 Communication mode Use the communication mode shown in Table 16-2 to perform communication between the dedicated flash µ programmer and the PD78F9882. Table 16-2. Communication Mode List Note 1 Communication TYPE Setting Pins Used Number of Mode Pulses COMM PORT...
Page 211 µ CHAPTER 16 PD78F9882 If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash µ programmer, the following signals are generated for the PD78F9882. For details, refer to the manual of Flashpro III/Flashpro IV.
Page 212: On-Board Pin Processing
µ CHAPTER 16 PD78F9882 16.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases.
Page 213 µ CHAPTER 16 PD78F9882 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 214 µ CHAPTER 16 PD78F9882 <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed.
Page 215: Connection Of Adapter For Flash Writing
µ CHAPTER 16 PD78F9882 16.1.4 Connection of adapter for flash writing The following figure shows an example of recommended connection when the adapter for flash writing is used. Figure 16-8. Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O VDD (3.0 to 3.6 V) VDD2 (LVDD) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49...
Page 216: Chapter 17 Mask Options
CHAPTER 17 MASK OPTIONS µ PD789881 has the following mask options. • Pull-up resistor The connection of on-chip pull-up resistors for port 5 (I/O port) can be switched in 1-bit units. <1> Pull-up resistor is connected <2> Pull-up resistor is not connected µ...
Page 217: Chapter 18 Instruction Set
CHAPTER 18 INSTRUCTION SET µ This chapter lists the instruction set of the PD789881 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E). 18.1 Operation 18.1.1 Operand identifiers and description methods Operands are described in “Operand”...
Page 218: Description Of "Operation" Column
CHAPTER 18 INSTRUCTION SET 18.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 219: Operation List
CHAPTER 18 INSTRUCTION SET 18.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 220 CHAPTER 18 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 221 CHAPTER 18 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A, CY ← A − byte − CY × × × SUBC A, #byte (saddr), CY ← (saddr) − byte − CY × × × saddr, #byte A, CY ←...
Page 222 CHAPTER 18 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A − byte × × × A, #byte (saddr) − byte × × × saddr, #byte A − r × × × A, r A − (saddr) ×...
Page 223 CHAPTER 18 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY (SP − 1) ← (PC + 1) , (SP − 2) ← (PC + 1) CALLT [addr5] ← (00000000, addr5 + 1), ← (00000000, addr5), SP ← SP − 2 ←...
Page 224: Instructions Listed By Addressing Type
CHAPTER 18 INSTRUCTION SET 18.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr !addr16 [DE] [HL] [HL+byte] $addr16 None 1st Operand Note...
Page 225 CHAPTER 18 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL.
Page 226 CHAPTER 18 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ (5) Other instructions RET, RETI, NOP, EI, DI, HALT, STOP User’s Manual U15172EJ2V1UD...
Page 227: Chapter 19 Electrical Specifications
CHAPTER 19 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Power supply voltage –0.3 to +4.6 µ PD78F9882 only Note 1 –0.3 to +8.5 Note 3 Input voltage P00 to P03, P10, P11, P20 to P22, P30 to P33, –0.3 to V + 0.3 Note 2...
Page 228 CHAPTER 19 ELECTRICAL SPECIFICATIONS Main System Clock Oscillator Characteristics µ = –40 to +85°C, V = 2.7 to 3.6 V (Mask ROM Version), V = 3.0 to 3.6 V ( PD78F9882)) Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit Circuit −...
Page 229 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (1/3) µ = –40 to +85°C, V = 2.7 to 3.6 V (Mask ROM Version), V = 3.0 to 3.6 V ( PD78F9882)) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin All pins Output current, high Per pin...
Page 230 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (2/3) = –40 to +85°C, V = 2.7 to 3.6 V (Mask ROM Version)) Note 5 Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Power supply 0.5 MHz main = –40 to +60°C Note 1 current clock operation 3.6 V...
Page 231 CHAPTER 19 ELECTRICAL SPECIFICATIONS DC Characteristics (3/3) µ = –40 to +85°C, V = 3.0 to 3.6 V ( PD78F9882)) Note 5 Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply 0.5 MHz main = –40 to +60°C Note 1 current clock operation 3.6 V...
Page 232 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Characteristics (1) Basic operation µ = –40 to +85°C, V = 2.7 to 3.6 V (mask ROM version), V = 3.0 to 3.6 V ( PD78F9882)) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ Cycle time (minimum instruction Operating with main system clock 1.81 execution time)
Page 233 CHAPTER 19 ELECTRICAL SPECIFICATIONS AC Timing Test Points (Excluding X1 and XT1 Inputs) 0.8V 0.8V Test points 0.2V 0.2V Clock Timing XT1 input Timer Input Timing TIH0 TIL0 TI00, TI01 TIL5 TIH5 TI50, TI51 Interrupt Input Timing INTL INTH INTP0 to INTP3 RESET Input Timing RESET User’s Manual U15172EJ2V1UD...
Page 234 CHAPTER 19 ELECTRICAL SPECIFICATIONS LCD Characteristics µ = –40 to +85°C, V = 2.7 to 3.6 V (Mask ROM Version), V = 3.0 to 3.6 V ( PD78F9882)) Parameter Symbol Conditions MIN. TYP. MAX. Unit LCD drive voltage Mask ROM version µ...
Page 235: Chapter 20 Package Drawing
CHAPTER 20 PACKAGE DRAWING 64-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.) NOTE 1.0±0.2 Each lead centerline is located within 0.08 mm of 0.17 +0.03 its true position (T.P.) at maximum material condition. −0.07 0.08 0.1±0.05...
Page 236: Chapter 21 Recommended Soldering Conditions
CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS µ PD789881 Subseries should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 21-1.
Page 237 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS Table 21-1. Surface Mounting Type Soldering Conditions (2/2) µ PD789881GB-×××-8EU-A: 64-pin plastic LQFP (10 × 10) µ 64-pin plastic LQFP (10 × 10) PD789882GB-8EU-A: Soldering Method Soldering Conditions Recommended Condition Symbol Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C Infrared reflow IR60-207-3 Note...
Page 238: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS µ The following development tools are available for development of systems using the PD789881 Subseries. Figure A-1 shows development tools. • Support to PC98-NX Series Unless specified otherwise, the products supported by IBM PC/AT compatibles can be used in PC98-NX Series.
Page 239 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package • Software package Language processing software Debugging software • Assembler package • Integrated debugger • C compiler package • System simulator • Device file • C compiler source file Note 1 Control software •...
Page 240: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software tools for development of the 78K/0S Series are combined in this package. Software package The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, and device files µ Part number: S××××SP78K0S ×××× in the part number differs depending on the operating systems to be used. Remark µ...
Page 241: Control Software
APPENDIX A DEVELOPMENT TOOLS ×××× in the part number differs depending on the host machines and operating systems to be used. Remark µ S××××RA78K0S µ S××××CC78K0S ×××× Host Machine Supply Media AB13 PC-9800 series, Japanese Windows 3.5” 2HD FD IBM PC/AT compatible BB13 English Windows AB17...
Page 242: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A The IE-78K0S-NS-A provides a coverage function in addition to the IE-78K0S-NS functions, thus In-circuit emulator...
Page 243: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS This debugger supports the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A for the Integrated debugger 78K/0S Series. The ID78K0S-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result.
Page 244: Appendix B Register Index
APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) Asynchronous serial interface mode register 0 (ASIM0) .................... 144 Asynchronous serial interface status register 0 (ASIS0) .................... 146 Baud rate generator control register 0 (BRGC0) ......................146 8-bit compare register 50 (CR50)..........................120 8-bit compare register 51 (CR51)..........................
Page 245 APPENDIX B REGISTER INDEX Port function register 9 (PF9) ..........................78, 166 Port mode register 0 (PM0)............................75 Port mode register 1 (PM1)............................75 Port mode register 2 (PM2)...........................75, 124 Port mode register 3 (PM3)..........................75, 99, 124 Port mode register 5 (PM5)............................75 Port mode register 8 (PM8)............................75 Port mode register 9 (PM9)............................75 Processor clock control register (PCC) .........................82 Pull-up resistor option register 0 (PUB0)........................77...
Page 246 APPENDIX B REGISTER INDEX B.2 Register Index (Alphabetic Order of Register Symbol) ASIM0: Asynchronous serial interface mode register 0..................144 ASIS0: Asynchronous serial interface status register 0 ..................146 BRGC0: Baud rate generator control register 0....................... 146 CR00: 16-bit capture/compare register 00......................93 CR01: 16-bit capture/compare register 01......................
Page 247: Register Index (Alphabetic Order Of Register Symbol)
APPENDIX B REGISTER INDEX PM1: Port mode register 1.............................75 PM2: Port mode register 2..........................75, 124 PM3: Port mode register 3........................75, 99, 124 PM5: Port mode register 5.............................75 PM8: Port mode register 8.............................75 PM9: Port mode register 9.............................75 PRM0: 16-bit timer prescaler mode register 0......................98 PUB0: Pull-up resistor option register 0 ........................77 PUB1:...

This manual is also suitable for:

Upd78f9882 Upd789881a

Renesas uPD789881 User Manual

Chapter 1 General

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Port Functions

Chapter 5 Clock Generator

Chapter 6 16-Bit Timer/Event Counter 0

Chapter 7 8-Bit Timer/Event Counters 50 and 51

Chapter 8 Watchdog Timer

Chapter 9 Serial Interface Uart0

Chapter 10 Lcd Controller/Driver

Chapter 11 Multiplier

Chapter 12 Voltage Halver Circuit and Regulator Circuit

Chapter 13 Interrupt Functions

Chapter 14 Standby Function

Chapter 15 Reset Function

CHAPTER 16 Μ PD78F9882

Chapter 17 Mask Options

Chapter 18 Instruction Set

Chapter 19 Electrical Specifications

Chapter 20 Package Drawing

Chapter 21 Recommended Soldering Conditions

Appendix A Development Tools

Appendix B Register Index

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Renesas uPD789881

Summary of Contents for Renesas uPD789881

This manual is also suitable for:

Table of Contents