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Renesas RA2L1 R7FA2L1AB3CFP User Manual

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Renesas RA2L1 Group

32

32-bit MCU

Renesas Advanced (RA) Family

Renesas RA2 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.00 Jul 2020

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Summary of Contents for Renesas RA2L1 R7FA2L1AB3CFP

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2: Corporate Headquarters
Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.
Page 3: General Precautions In The Handling Of Microprocessing Unit And Microcontroller Unit Products
Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 4: About This Document
Audience This manual is written for system designers who are designing and programming applications using the Renesas Microcontroller. The user is expected to have basic knowledge of electrical circuits, logic circuits, and the MCU.
Page 5: Typographic Notation
Numbering Notation The following numbering notation is used throughout this manual: Example Description 011b Binary number. For example, the binary equivalent of the number 3 is 011b. 0x1F Hexadecimal number. For example, the hexadecimal equivalent of the number 31 is described 0x1F. In some cases, a hexadecimal number is shown with the suffix "h".
Page 6: Register Description
Register Description Each register description includes both a register diagram that shows the bit assignments and a register bit table that describes the content of each bit. The example of symbols used in these tables are described in the sections that follow. The following is an example of a register description and associated bit field definition.
Page 7 Abbreviations Abbreviations used in this document are shown in the following table. Abbreviation Description Advanced Encryption Standard Advanced High-performance Bus AHB-AP AHB Access Port Advanced Peripheral Bus Alleged RC Advanced Trace Bus Binary Coded Decimal BSDL Boundary Scan Description Language Data Encryption Standard Digital Signature Algorithm Embedded Trace Buffer...
Page 8: Proprietary Notice
All text, graphics, photographs, trademarks, logos, artwork and computer code, collectively known as content, contained in this document is owned, controlled or licensed by or to Renesas, and is protected by trade dress, copyright, patent and trademark laws, and other intellectual property rights and unfair competition laws. Except as expressly provided herein, no...
Page 9: Table Of Contents
Contents Features ................................39 Overview..............................40 Function Outline ..........................40 Block Diagram ............................ 44 Part Numbering ..........................44 Function Comparison ......................... 47 Pin Functions............................48 Pin Assignments..........................51 Pin Lists .............................. 54 CPU ................................58 Overview............................. 58 2.1.1 CPU ............................58 2.1.2 Debug ............................
Page 10 3.2.1 Single-Chip Mode ........................71 3.2.2 SCI Boot Mode ......................... 71 Operating Modes Transitions......................71 3.3.1 Operating Mode Transitions as Determined by the Mode-Setting Pin........71 Address Space............................72 Address Space ........................... 72 Resets................................. 73 Overview............................. 73 Register Descriptions ......................... 78 5.2.1 RSTSR0 : Reset Status Register 0...................
Page 11 Register Descriptions ......................... 99 7.2.1 LVCMPCR : Voltage Monitor Circuit Control Register .............. 99 7.2.2 LVDLVLR : Voltage Detection Level Select Register .............. 100 7.2.3 LVD1CR0 : Voltage Monitor 1 Circuit Control Register 0............100 7.2.4 LVD2CR0 : Voltage Monitor 2 Circuit Control Register 0............101 7.2.5 LVD1CR1 : Voltage Monitor 1 Circuit Control Register............
Page 12 8.2.18 LOCOUTCR : LOCO User Trimming Control Register ............129 8.2.19 MOCOUTCR : MOCO User Trimming Control Register ............129 8.2.20 HOCOUTCR : HOCO User Trimming Control Register............130 Main Clock Oscillator........................130 8.3.1 Connecting a Crystal Resonator..................... 130 8.3.2 External Clock Input........................
Page 13 9.3.1 Measuring Clock Frequency ....................145 9.3.2 Digital Filtering of Signals on CACREF Pin ................147 Interrupt Requests ..........................147 Usage Notes............................. 147 9.5.1 Settings for the Module-Stop Function ................... 147 10. Low Power Modes ........................... 148 10.1 Overview............................148 10.2 Register Descriptions ........................
Page 14 10.8.4 Snooze Operation Example....................176 10.9 Usage Notes............................. 180 10.9.1 Register Access........................180 10.9.2 I/O Port pin states ........................181 10.9.3 Module-Stop State of DTC...................... 181 10.9.4 Internal Interrupt Sources ....................... 181 10.9.5 Transitioning to Low Power Modes..................181 10.9.6 Timing of WFI Instruction ......................
Page 15 12.5 Interrupt setting procedure ....................... 211 12.5.1 Enabling Interrupt Requests ....................211 12.5.2 Disabling Interrupt Requests ....................211 12.5.3 Polling for interrupts........................ 211 12.5.4 Selecting Interrupt Request Destinations ................212 12.5.5 Digital Filter..........................212 12.5.6 External Pin Interrupts ......................213 12.6 Non-Maskable Interrupt Operation ....................
Page 16 14.4.2 Operation ..........................234 14.5 Bus Slave MPU ..........................236 14.5.1 Register Descriptions......................237 14.5.2 Functions ..........................242 14.6 Security MPU............................ 243 14.6.1 Register Descriptions (Option-Setting Memory) ..............243 14.6.2 Memory Protection........................248 14.7 Usage Notes............................. 249 14.7.1 Notes on the Use of a Debugger .................... 249 14.8 References ............................
Page 17 15.7 Interrupt ............................275 15.7.1 Interrupt Sources ........................275 15.8 Event Link............................275 15.9 Low Power Consumption Function....................275 15.10 Usage Notes............................. 276 15.10.1 Transfer Information Start Address..................276 16. Event Link Controller (ELC)........................277 16.1 Overview............................277 16.2 Register Descriptions ........................278 16.2.1 ELCR : Event Link Controller Register ...................
Page 18 17.5.2 Procedure for Using Port Group Input ..................298 17.5.3 Port Output Data Register (PODR) Summary ................ 298 17.5.4 Notes on Using Analog Functions ..................299 17.6 Peripheral Select Settings for Each Product ..................299 18. Key Interrupt Function (KINT) ........................ 304 18.1 Overview............................
Page 19 20.2.8 GTUPSR : General PWM Timer Up Count Source Select Register ........328 20.2.9 GTDNSR : General PWM Timer Down Count Source Select Register ........330 20.2.10 GTICASR : General PWM Timer Input Capture Source Select Register A ......333 20.2.11 GTICBSR : General PWM Timer Input Capture Source Select Register B ......
Page 20 20.8 Initialization Method of Output Pins ....................424 20.8.1 Pin Settings after Reset ......................424 20.8.2 Pin Initialization Due to Error during Operation ..............425 20.9 Usage Notes............................. 425 20.9.1 Module-Stop Function Setting ....................425 20.9.2 GTCCRn Settings during Compare Match Operation (n = A to F).......... 425 20.9.3 Setting Range for GTCNT Counter..................
Page 21 21.4.5 Digital Filter..........................450 21.4.6 How to Calculate Event Number, Pulse Width, and Pulse Period .......... 451 21.4.7 When Count is Forcibly Stopped by TSTOP Bit ..............451 21.4.8 When Selecting AGT0 Underflow as the Count Source ............451 21.4.9 Module-stop function ......................
Page 22 22.3.4 30-Second Adjustment ......................474 22.3.5 Reading 64-Hz Counter and Time ..................475 22.3.6 Alarm Function........................477 22.3.7 Procedure for Disabling Alarm Interrupt ................. 478 22.3.8 Time Error Adjustment Function ..................... 478 22.4 Interrupt Sources ..........................481 22.5 Event Link Output ..........................482 22.5.1 Interrupt Handling and Event Linking..................
Page 23 24.2 Register Descriptions ........................501 24.2.1 IWDTRR : IWDT Refresh Register ..................501 24.2.2 IWDTSR : IWDT Status Register .................... 502 24.2.3 OFS0 : Option Function Select Register 0................503 24.3 Operation............................505 24.3.1 Auto Start Mode........................505 24.3.2 Refresh Operation ........................506 24.3.3 Status Flags..........................
Page 24 25.2.20 SNFR : Noise Filter Setting Register ..................541 25.2.21 SIMR1 : IIC Mode Register 1....................542 25.2.22 SIMR2 : IIC Mode Register 2....................543 25.2.23 SIMR3 : IIC Mode Register 3....................543 25.2.24 SISR : IIC Status Register ...................... 545 25.2.25 SPMR : SPI Mode Register ....................
Page 25 25.6.8 Clock Output Control ......................611 25.7 Operation in Simple IIC Mode ......................612 25.7.1 Generation of Start, Restart, and Stop Conditions ..............613 25.7.2 Clock Synchronization ......................614 25.7.3 SDAn Output Delay ........................ 615 25.7.4 SCI Initialization in Simple IIC Mode..................615 25.7.5 Operation in Master Transmission in Simple IIC Mode............
Page 26 25.14.1 Note on Stopping Reception When Using the RTS Function in Asynchronous Mode.... 638 26. I2C Bus Interface (IIC) ..........................639 26.1 Overview............................639 26.2 Register Descriptions ........................641 26.2.1 ICCR1 : I C Bus Control Register 1..................641 26.2.2 ICCR2 : I C Bus Control Register 2..................
Page 27 26.7.4 Host Address Detection ......................688 26.8 Wakeup Function..........................689 26.8.1 Normal Wakeup Mode 1 ......................690 26.8.2 Normal Wakeup Mode 2 ......................693 26.8.3 Command Recovery Mode and EEP Response Mode (Special Wakeup Modes)....695 26.9 Automatic Low-Hold Function for SCL ..................... 698 26.9.1 Function to Prevent Wrong Transmission of Transmit Data ...........
Page 28 27.2.5 MKIVLR : Mask Invalid Register ..................... 723 27.2.6 Mailbox Registers ........................723 27.2.7 MIER : Mailbox Interrupt Enable Register ................727 27.2.8 MIER_FIFO : Mailbox Interrupt Enable Register for FIFO Mailbox Mode ......727 27.2.9 MCTL_TX[j] : Message Control Register for Transmit (j = 0 to 31)......... 728 27.2.10 MCTL_RX[j] : Message Control Register for Receive (j = 0 to 31) .........
Page 29 27.9.2 Settings for the Operating Clock..................... 762 28. Serial Peripheral Interface (SPI) ......................763 28.1 Overview............................763 28.2 Register Descriptions ........................765 28.2.1 SPCR : SPI Control Register ....................765 28.2.2 SSLP : SPI Slave Select Polarity Register ................767 28.2.3 SPPCR : SPI Pin Control Register ..................
Page 30 28.5.3 Constraints on Starting Transfer ..................... 824 28.5.4 Constraints on Mode-Fault, Underrun, Overrun, or Parity Error Event Output ....... 824 28.5.5 Constraints on the SPSR.SPRF and SPSR.SPTEF Flags ............. 824 29. Cyclic Redundancy Check (CRC) Calculator..................825 29.1 Overview............................825 29.2 Register Descriptions ........................
Page 31 30.2.20 ADDISCR : A/D Disconnection Detection Control Register............ 860 30.2.21 ADACSR : A/D Conversion Operation Mode Select Register ..........861 30.2.22 ADGSPCR : A/D Group Scan Priority Control Register............861 30.2.23 ADCMPCR : A/D Compare Function Control Register ............862 30.2.24 ADCMPANSR0 : A/D Compare Function Window A Channel Select Register 0....
Page 32 30.7 A/D Conversion Procedure when Selecting Internal Reference Voltage as High-Potential Reference Voltage ..........................905 30.8 Usage Notes............................. 905 30.8.1 Constraints on Setting the Registers ..................905 30.8.2 Constraints on Reading the Data Registers ................905 30.8.3 Constraints on Stopping A/D Conversion ................906 30.8.4 A/D Conversion Restart and Termination Timing..............
Page 33 32.3 Using the Temperature Sensor......................919 32.3.1 Preparation for Using the Temperature Sensor ..............919 32.3.2 Procedures for Using the Temperature Sensor ..............920 33. Low Power Analog Comparator (ACMPLP) ..................921 33.1 Overview............................921 33.2 Register Descriptions ........................923 33.2.1 COMPMDR : ACMPLP Mode Setting Register ..............
Page 34 34.2.15 CTSUTRIMA : CTSU Trimming Register A ................955 34.2.16 CTSUTRIMB : CTSU Trimming Register B ................956 35. Data Operation Circuit (DOC) ......................... 957 35.1 Overview............................957 35.2 DOC Register Descriptions ......................957 35.2.1 DOCR : DOC Control Register ....................957 35.2.2 DODIR : DOC Data Input Register ..................
Page 35 36.4 Usage Notes............................. 972 36.4.1 Instruction Fetch from the SRAM Area ................... 972 36.4.2 SRAM Store Buffer ......................... 972 37. Flash Memory ............................973 37.1 Overview............................973 37.2 Memory Structure ..........................974 37.3 Register Descriptions ........................975 37.3.1 DFLCTL : Data Flash Control Register................... 975 37.3.2 PFBER : Prefetch Buffer Enable Register ................
Page 36 37.6.3 Protection by Access Window ....................997 37.7 Programming Commands......................... 998 37.8 Suspend Operation........................... 998 37.9 Protection ............................998 37.9.1 Startup Program Protection ....................998 37.9.2 Area Protection ........................999 37.10 Serial Programming Mode......................1000 37.10.1 SCI Boot Mode ........................1000 37.11 Using a Serial Programmer ......................
Page 37 41. Electrical Characteristics........................1027 41.1 Absolute Maximum Ratings......................1027 41.2 DC Characteristics.......................... 1028 41.2.1 Tj/Ta Definition ........................1028 41.2.2 I/O VIH, VIL........................... 1029 41.2.3 I/O IOH, IOL .......................... 1029 41.2.4 I/O VOH, VOL, and Other Characteristics ................1035 41.2.5 Operating and Standby Current.................... 1036 41.2.6 VCC Rise and Fall Gradient and Ripple Frequency .............
Page 38 Revision History ............................1115...
Page 39: Features
Renesas RA2L1 Group User’s Manual ® ® Ultra low power 48 MHz Arm Cortex -M23 core, up to 256-KB code flash memory, 32 KB SRAM, Capacitive Touch Sensing Unit, 12-bit A/D Converter, 12-bit D/A Converter, Security and Safety features. Features ●...
Page 40: Overview
® The MCU integrates multiple series of software- and pin-compatible Arm -based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability. ® The MCU in this series incorporates an energy-efficient Arm Cortex -M23 32-bit core, that is particularly well suited for cost-sensitive and low-power applications, with the following features: ●...
Page 41 RA2L1 User's Manual 1. Overview Table 1.3 System (2 of 2) Feature Functional description Clocks ● Main clock oscillator (MOSC) ● Sub-clock oscillator (SOSC) ● High-speed on-chip oscillator (HOCO) ● Middle-speed on-chip oscillator (MOCO) ● Low-speed on-chip oscillator (LOCO) ● IWDT-dedicated on-chip oscillator (IWDTLOCO) ●...
Page 42 RA2L1 User's Manual 1. Overview Table 1.6 Timers Feature Functional description General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down- counter, or the up- and down-counter.
Page 43 RA2L1 User's Manual 1. Overview Table 1.8 Analog (2 of 2) Feature Functional description Temperature Sensor (TSN) The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is fairly linear.
Page 44: Block Diagram
RA2L1 User's Manual 1. Overview Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory Arm Cortex-M23 System 256-KB code flash Clocks POR/LVD MOSC/SOSC 8-KB data flash Reset NVIC (H/M/L) OCO...
Page 45 9: 128 KB Feature set A: Standard and security Group name L1: Low Power group Core 2: Arm Cortex-M23 RA Family (Renesas Advanced) Flash memory Renesas microcontroller unit Renesas Figure 1.2 Part numbering scheme Table 1.12 Product list (1 of 2)
Page 46 RA2L1 User's Manual 1. Overview Table 1.12 Product list (2 of 2) Data Operating Product part number Package code Code flash flash SRAM temperature R7FA2L1A93CFP PLQP0100KB-B 128 KB 8 KB 32 KB -40 to +105°C R7FA2L1A93CFN PLQP0080KB-B R7FA2L1A93CFM PLQP0064KB-C R7FA2L1A93CFL PLQP0048KB-B R7FA2L1A93CNE R7FA2L1A92DFP...
Page 47: Function Comparison
RA2L1 User's Manual 1. Overview Function Comparison Table 1.13 Function Comparison R7FA2L1A R7FA2L1A B3CFL 93CFL R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A R7FA2L1A Parts number B3CFP 93CFP B3CFN 93CFN B3CFM 93CFM B3CNE 93CNE Pin count Package LQFP LQFP LQFP LQFP LQFP LQFP LQFP/QFN...
Page 48: Pin Functions
RA2L1 User's Manual 1. Overview Pin Functions Table 1.14 Pin functions (1 of 3) Function Signal Description Power supply Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS by a 0.1-µF capacitor. The capacitor should be placed close to the pin.
Page 49 RA2L1 User's Manual 1. Overview Table 1.14 Pin functions (2 of 3) Function Signal Description RTCOUT Output Output pin for 1-Hz or 64-Hz clock SCKn (n = 0 to 3, 9) Input/output pins for the clock (clock synchronous mode) RXDn (n = 0 to 3, 9) Input Input pins for received data (asynchronous mode/clock synchronous mode)
Page 50 RA2L1 User's Manual 1. Overview Table 1.14 Pin functions (3 of 3) Function Signal Description I/O ports P000 to P008, P010 to General-purpose input/output pins P015 P100 to P115 General-purpose input/output pins P200 Input General-purpose input pin P201 to P208, P212, General-purpose input/output pins P213 P214, P215...
Page 51: Pin Assignments
RA2L1 User's Manual 1. Overview Pin Assignments Figure 1.3 Figure 1.4 show the pin assignments from the top view. P500 P300/SWCLK P301 P501 P502 P302 P503 P303 P504 P809 P505 P808 P304 P305 P015 P306 P014 P307 P013 P200 P012 P201/MD R7FA2L1AB3CFP AVCC0...
Page 52 RA2L1 User's Manual 1. Overview P500 P300/SWCLK P501 P301 P502 P302 P503 P303 P504 P809 P015 P808 P014 P304 P013 P305 P012 P306 R7FA2L1AB3CFN AVCC0 P200 AVSS0 P201/MD P011/VREFL0 P010/VREFH0 P204 P006 P205 P005 P206 P004 P207 P003 P208 P002 VCC_DCDC P001 P000...
Page 53 RA2L1 User's Manual 1. Overview P300/SWCLK P500 P301 P015 P302 P014 P200 P013 P201/MD P012 R7FA2L1AB3CFL AVCC0 P206 AVSS0 P207 P011/VREFL0 P208 P010/VREFH0 VCC_DCDC P002 P001 VSS_DCDC P000 Figure 1.6 Pin assignment for LQFP 48-pin (top view) P500 P300/SWCLK P015 P301 P014 P302...
Page 54: Pin Lists
RA2L1 User's Manual 1. Overview Pin Lists Table 1.15 Pin list (1 of 4) Num. Timers Communication interfaces Analogs CACREF P400 AGTIO1_ — GTIOC6A — — SCK0_B/ SCL0_A — — — — — IRQ0_A SCK1_B — P401 — GTETRG GTIOC6B —...
Page 55 RA2L1 User's Manual 1. Overview Table 1.15 Pin list (2 of 4) Num. Timers Communication interfaces Analogs VSS_DC — — — — — — — — — — — — — — — — — — — — — — —...
Page 56 RA2L1 User's Manual 1. Overview Table 1.15 Pin list (3 of 4) Num. Timers Communication interfaces Analogs — P112 AGTOB0 — GTIOC3B — — SCK1_D/ — SSLB0_C — — — TSCAP-C — TXD2_B/ MOSI2_B/ SDA2_B — — P113 — — GTIOC2A —...
Page 57 RA2L1 User's Manual 1. Overview Table 1.15 Pin list (4 of 4) Num. Timers Communication interfaces Analogs — — — — — — — — — — — — — — — — — — P015 — — — — —...
Page 58: Cpu
RA2L1 User's Manual 2. CPU ® ® The MCU is based on the Arm Cortex -M23 core. Overview 2.1.1 ● Arm Cortex-M23 – Revision: r1p0-00rel0 – Armv8-M architecture profile – Single-cycle integer multiplier – 19-cycle integer divider ● Memory Protection Unit (MPU) –...
Page 59: Implementation Options
RA2L1 User's Manual 2. CPU OCD Access Trace/debug data From: OCD Emulator (SWD) From: System bus Cortex ® -M23 integration Cortex-M23 SWJ-DP CM23 core DAP IC NVIC SRAM APB-AP DBGREG OCDREG To: System control AHB-AP ROM Table Bus matrix To: System bus Figure 2.1 Cortex-M23 block diagram Implementation Options...
Page 60: Swd Interface
RA2L1 User's Manual 2. CPU Table 2.1 Implementation options (2 of 2) Option Implementation SysTick Included SYST_CALIB register (0x4000_0147) Bit [31] = 0 Reference clock provided Bit [30] = 1 TENMS value is inexact Bits [29:24] = 0x00 Reserved Bits [23:0] = 0x000147 TENMS: (32768 ×...
Page 61: Programmers Model
RA2L1 User's Manual 2. CPU 2.4.2.2 Reset In OCD mode, some resets depend on the CPU status and the DBGSTOPCR register setting. Table 2.4 Reset or interrupt and mode setting Control in On-Chip Debug (OCD) mode Reset or interrupt name OCD break mode OCD run mode RES pin reset...
Page 62: Cortex-M23 Peripheral Address Map
RA2L1 User's Manual 2. CPU located in the OCD address space and can only be accessed from the OCD tool. The CPU and other bus masters cannot access OCDREG. 2.5.2 Cortex-M23 Peripheral Address Map In the system address space, the Cortex-M23 core has a Private Peripheral Bus (PPB) that can only be accessed from the CPU and OCD emulator.
Page 63: Dbgreg Module
RA2L1 User's Manual 2. CPU Table 2.8 CoreSight component registers in the CoreSight ROM Table (2 of 2) Name Address Access size Initial value PID5 0xE00F_FFD4 32 bits 0x00000000 PID6 0xE00F_FFD8 32 bits 0x00000000 PID7 0xE00F_FFDC 32 bits 0x00000000 PID0 0xE00F_FFE0 32 bits 0x0000001B...
Page 64 RA2L1 User's Manual 2. CPU 2.5.5.2 DBGSTOPCR : Debug Stop Control Register Base address: DBG = 0x4001_B000 Offset address: 0x10 Bit position: DBGS DBGS DBGS DBGS DBGS TOP_ Bit field: — — — — — — TOP_ — — — —...
Page 65: Ocdreg Module
RA2L1 User's Manual 2. CPU Table 2.10 DBGREG CoreSight component registers (2 of 2) Name Address Access size Initial value PID5 0x4001_BFD4 32 bits 0x00000000 PID6 0x4001_BFD8 32 bits 0x00000000 PID7 0x4001_BFDC 32 bits 0x00000000 PID0 0x4001_BFE0 32 bits 0x00000005 PID1 0x4001_BFE4 32 bits...
Page 66 RA2L1 User's Manual 2. CPU 2.5.6.2 MCUSTAT : MCU Status Register Base address: CPU_OCD = 0x8000_0000 Offset address: 0x400 Bit position: Bit field: — — — — — — — — — — — — — — — — Value after reset: Bit position: CPUS CPUS...
Page 67: Systick Timer
RA2L1 User's Manual 2. CPU Symbol Function 31:9 — These bits are read as 0. The write value should be 0. Note: Set DBIRQ and EDBGRQ to the same value. 2.5.6.4 OCDREG CoreSight component registers The OCDREG module provides the CoreSight component registers defined in the Arm CoreSight architecture. Table 2.12 shows the registers.
Page 68: Unlock Id Code
RA2L1 User's Manual 2. CPU Emulator host PC To: CPU bus To: CPU debug SWJ-DP AHB-AP emulator APB-AP OCDREG comparator Option-setting memory IAUTH output Unlock ID Compare result (debug enable) Figure 2.3 SWD Authentication mechanism block diagram An ID comparator is available in the MCU for authentication. The comparator compares the 128-bit IAUTH output from the OCDREG and the 128-bit unlock ID code from the option-setting memory.
Page 69 RA2L1 User's Manual 2. CPU Table 2.13 Restrictions by mode Start OCD emulator Change low power Access AHB-AP and Access APB-AP and Active mode connection mode system bus OCDREG Normal Sleep Software Standby Snooze If system bus access is required in Software Standby or Snooze mode, set the MCUCTRL.DBIRQ bit in OCDREG to wake up the MCU from the low power modes.
Page 70: References
RA2L1 User's Manual 2. CPU ● When the DbgStatus bit is 1, the 128-bit ID code is a match with the OSIS value. AHB transfers are permitted. ● When the DbgStatus bit is 0, the 128-bit ID code is not a match with the OSIS value. AHB transfers are not permitted.
Page 71: Operating Modes
RA2L1 User's Manual 3. Operating Modes Operating Modes Operating Mode Types and Selection Table 3.1 shows the selection of operating modes by the mode-setting pin. For details on each of the operating modes, see section 3.2. Details of Operating Modes. Operation starts when the on-chip flash memory is enabled, regardless of the mode in which operation started.
Page 72: Address Space
RA2L1 User's Manual 4. Address Space Address Space Address Space The MCU supports a 4-GB linear address space ranging from 0x0000_0000 to 0xFFFF_FFFF that can contain both program and data. Figure 4.1 shows the memory map of a 256-KB/128-KB flash product. 0xFFFF_FFFF ®...
Page 73: Resets
RA2L1 User's Manual 5. Resets Resets Overview The MCU provides 13 resets. Table 5.1 lists the reset names and sources. Table 5.1 Reset names and sources Reset name Source RES pin reset Voltage input to the RES pin is driven low Power-on reset VCC rise (voltage detection V Independent watchdog timer reset...
Page 74 RA2L1 User's Manual 5. Resets Table 5.2 Reset detect flags initialized by each reset source (2 of 5) Reset source Voltage Independent Power-on monitor 0 watchdog Watchdog Flags to be initialized RES pin reset reset reset timer reset timer reset Bus Master MPU Error Reset Detect Flag —...
Page 75 RA2L1 User's Manual 5. Resets Table 5.2 Reset detect flags initialized by each reset source (5 of 5) Reset source Bus master Bus slave CPU stack MPU error MPU error pointer error Flags to be initialized reset reset reset Voltage Monitor 2 Reset Detect Flag (RSTSR0.LVD2RF) —...
Page 76 RA2L1 User's Manual 5. Resets Table 5.3 Module-related registers initialized by each reset source (2 of 4) Reset source Voltage Voltage monitor 1 monitor 2 SRAM parity SRAM ECC Registers to be initialized reset reset Software reset error reset error reset Registers related to the WDTRR, WDTCR, ✓...
Page 77 RA2L1 User's Manual 5. Resets Table 5.3 Module-related registers initialized by each reset source (4 of 4) Reset source Bus master Bus slave CPU stack MPU error MPU error pointer error Registers to be initialized reset reset reset Register related to the LOCO LOCOCR ✓...
Page 78: Register Descriptions
RA2L1 User's Manual 5. Resets Register Descriptions 5.2.1 RSTSR0 : Reset Status Register 0 Base address: SYSC = 0x4001_E000 Offset address: 0x410 Bit position: LVD2R LVD1R LVD0R Bit field: — — — — PORF Value after reset: Symbol Function PORF Power-On Reset Detect Flag 0: Power-on reset not detected 1: Power-on reset detected...
Page 79: Rstsr1 : Reset Status Register 1
RA2L1 User's Manual 5. Resets [Clearing conditions] ● When a reset listed in section 5.1. Overview occurs ● When LVD1RF is read as 1 and then 0 is written to LVD1RF LVD2RF flag (Voltage Monitor 2 Reset Detect Flag) The LVD2RF flag indicates that the VCC voltage fell below V det2 [Setting condition] ●...
Page 80 RA2L1 User's Manual 5. Resets IWDTRF flag (Independent Watchdog Timer Reset Detect Flag) The IWDTRF flag indicates that an independent watchdog timer reset occurs. [Setting condition] ● When an independent watchdog timer reset occurs. [Clearing conditions] ● When a reset listed in section 5.1.
Page 81: Rstsr2 : Reset Status Register 2
RA2L1 User's Manual 5. Resets [Clearing conditions] ● When a reset listed in section 5.1. Overview occurs ● When 1 is read and then 0 is written to BUSSRF. BUSMRF flag (Bus Master MPU Error Reset Detect Flag) The BUSMRF flag indicates that a bus master MPU error reset occurs. [Setting condition] ●...
Page 82: Operation
RA2L1 User's Manual 5. Resets Operation 5.3.1 RES Pin Reset The RES pin generates this reset. When the RES pin is driven low, all the processing in progress is aborted and the MCU enters a reset state. To successfully reset the MCU, the RES pin must be held low for the power supply stabilization time specified at power-on.
Page 83: Voltage Monitor Reset
RA2L1 User's Manual 5. Resets det0 VCCmin. Power-on reset state Voltage monitor 0 reset state Voltage monitor 0 reset state RES pin POR monitor (active-low) Set by OFS1.LVDAS LVD0 enable/disable signal (active-low) Voltage detection 0 signal (active-low) LVD0 LVD0 Internal reset signal (active-low) RES pin reset RSTSR0.PORF...
Page 84: Independent Watchdog Timer Reset
RA2L1 User's Manual 5. Resets above V . When the LVD1CR0.RN bit is 1 and VCC falls to or below V , the CPU is released from the internal reset det1 det1 state and starts reset exception handling when the LVD1 reset time (t ) elapses.
Page 85: Software Reset
RA2L1 User's Manual 5. Resets When output of the watchdog timer reset is selected, a watchdog timer reset is generated if the WDT underflows, or if data is written when refresh operation is disabled. When the internal reset time (t ) elapses after the watchdog timer reset is RESW2 generated, the internal reset is canceled and the CPU starts the reset exception handling.
Page 86: Usage Notes
RA2L1 User's Manual 5. Resets Reset exception handling RSTSR1 ≠ 0x00 RSTSR0.LVD1RF = 1 RSTSR0.LVD2RF = 1 RSTSR0. LVD0RF = 1 RSTSR0. PORF = 1 Reset associated with Voltage Power-on RES pin reset each bit of RSTSR1, monitor 0 reset RSTSR0.LVD1RF, or reset RSTSR0.LVD2RF...
Page 87: Option-Setting Memory
RA2L1 User's Manual 6. Option-Setting Memory Option-Setting Memory Overview The option-setting memory determines the state of the MCU after a reset. The Option-setting memory is allocated to the configuration setting area and the program flash area of the flash memory. The available methods of setting are different for the two areas.
Page 88 RA2L1 User's Manual 6. Option-Setting Memory Symbol Function IWDTTOPS[1:0] IWDT Timeout Period Select 0 0: 128 cycles (0x007F) 0 1: 512 cycles (0x01FF) 1 0: 1024 cycles (0x03FF) 1 1: 2048 cycles (0x07FF) IWDTCKS[3:0] IWDT-Dedicated Clock Frequency Division Ratio Select 0x0: ×...
Page 89 RA2L1 User's Manual 6. Option-Setting Memory Symbol Function WDTRSTIRQS WDT Reset Interrupt Request Select 0: Enable interrupt request or non-maskable interrupt request 1: Enable reset — When read, these bits return the written value. The write value should be 1. WDTSTPCTL WDT Stop Control 0: Continue counting...
Page 90 RA2L1 User's Manual 6. Option-Setting Memory Table 6.1 Count Stop Control by the IWDTSTPCTL Bit IWDTSTPCTL Mode Counting of IWDT Sleep / snooze/ software standby mode Continue counting Sleep / snooze / software standby mode Stop counting For details, see section 24, Independent Watchdog Timer (IWDT).
Page 91: Ofs1 : Option Function Select Register 1
RA2L1 User's Manual 6. Option-Setting Memory 6.2.2 OFS1 : Option Function Select Register 1 Address: 0x0000_0404 and 0x0000_2404 Bit position: ICSAT Bit field: — — — — — — — — — — — — — — — Value after reset: The value set by the user Bit position: HOCO...
Page 92: Mpu Registers
RA2L1 User's Manual 6. Option-Setting Memory Note: When the HOCOEN bit is set to 0, the system clock source is not switched to HOCO. The system clock source is only switched to HOCO by setting the Clock Source Select bits (SCKSCR.CKSEL[2:0]). To use the HOCO clock, set the OFS1.HOCOFRQ bit to an optimum value.
Page 93: Aws : Access Window Setting Register
RA2L1 User's Manual 6. Option-Setting Memory Table 6.2 MPU registers (2 of 2) Size Register name Symbol Function Address (byte) Security MPU Region 2 Start Address SECMPUS2 Specifies the secure data of security 0x0000_0428 Register function. Security MPU Region 2 End Address SECMPUE2 Specifies the secure data of security 0x0000_042C...
Page 94: Osis : Ocd/Serial Programmer Id Setting Register
RA2L1 User's Manual 6. Option-Setting Memory Symbol Function BTFLG Startup Area Select Flag This bit specifies whether the address of the startup area is exchanged for the boot swap function. 0: First 8-KB area (0x0000_0000 to 0x0000_1FFF) and second 8-KB area (0x0000_2000 to 0x0000_3FFF) are exchanged 1: First 8-KB area (0x0000_0000 to 0x0000_1FFF) and second 8-KB area (0x0000_2000 to 0x0000_3FFF) are not exchanged...
Page 95: Setting Option-Setting Memory
Bit [127] = 0 Protection enabled The ID code is not checked, the ID code is always mismatching, the connection to the serial programmer or the on-chip debugger is prohibited, and Renesas cannot access the test mode. Setting Option-Setting Memory 6.3.1...
Page 96: Usage Notes
RA2L1 User's Manual 6. Option-Setting Memory For details of the programming command, the configuration setting command, and the startup area select function, see section 37, Flash Memory. Debugging through an OCD or programming by a flash writer This procedure depends on the tool in use, see the tool manual for details. The MCU provides two setting procedures: ●...
Page 97: Low Voltage Detection (Lvd)
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Low Voltage Detection (LVD) Overview The Low Voltage Detection (LVD) module monitors the voltage level input to the VCC pin. The detection level can be selected by register settings. The LVD module consists of three separate voltage level detectors (LVD0, LVD1, LVD2). LVD0, LVD1, and LVD2 measure the voltage level input to the VCC pin.
Page 98 RA2L1 User's Manual 7. Low Voltage Detection (LVD) Voltage detection 0 circuit Voltage monitor 0 reset generation circuit LVDAS Voltage detection Level selection 0 signal Voltage detection circuit Internal reference 0 reset signal voltage VDSEL1[2:0] (active-low) (for detecting V det0 LVDAS Voltage detection 0 signal is high when the LVDAS bit is 1 (LVD0 disabled).
Page 99: Register Descriptions
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Voltage monitor 2 The setting of the LVD2SR.DET bit is 0 if 0 (undetected) is written by the program Voltage detection 2 LVD2SR.MON LVCMPCR.LVD2E LVD2CR0.RIE LVD2CR0.CMPE LVD2CR0.RI LVD2CR0.RN = 0 Voltage monitor 2 Fixed Voltage period...
Page 100: Lvdlvlr : Voltage Detection Level Select Register
RA2L1 User's Manual 7. Low Voltage Detection (LVD) 7.2.2 LVDLVLR : Voltage Detection Level Select Register Base address: SYSC = 0x4001_E000 Offset address: 0x418 Bit position: Bit field: LVD2LVL[2:0] LVD1LVL[4:0] Value after reset: Symbol Function LVD1LVL[4:0] Voltage Detection 1 Level Select (Standard voltage during fall in voltage) 0x00: V det1_0 0x01: V...
Page 101: Lvd2Cr0 : Voltage Monitor 2 Circuit Control Register 0
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Symbol Function CMPE Voltage Monitor 1 Circuit Comparison Result Output Enable 0: Disable voltage monitor 1 circuit comparison result output 1: Enable voltage monitor 1 circuit comparison result output — The read value is undefined. The write value should be 1. —...
Page 102: Lvd1Cr1 : Voltage Monitor 1 Circuit Control Register
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Symbol Function Voltage Monitor 2 Reset Negate Select 0: Negate after a stabilization time (t ) when VCC > V is detected LVD2 det2 1: Negate after a stabilization time (t ) on assertion of the LVD2 reset LVD2 Note: Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Page 103: Lvd2Cr1 : Voltage Monitor 2 Circuit Control Register 1
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Symbol Function Voltage Monitor 1 Voltage Variation Detection Flag 0: Not detected 1: V crossing is detected det1 Voltage Monitor 1 Signal Monitor Flag 0: VCC < V det1 1: VCC ≥ V or MON is disabled det1 —...
Page 104: Vcc Input Voltage Monitor
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Symbol Function Voltage Monitor 2 Voltage Variation Detection Flag 0: Not detected 1: V crossing is detected det2 Voltage Monitor 2 Signal Monitor Flag 0: VCC < V det2 1: VCC ≥ V or MON is disabled det2 —...
Page 105: Reset From Voltage Monitor 0
RA2L1 User's Manual 7. Low Voltage Detection (LVD) Table 7.3 Procedures to set up monitoring against V (2 of 2) det2 Step Monitoring the results of comparison by voltage monitor 2 Enabling output Set LVD2CR0.CMPE = 1 to enable output of the comparison results from voltage monitor 2. Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the OFS1.LVDAS bit to 0 to enable the voltage monitor 0 reset after a reset.
Page 106 RA2L1 User's Manual 7. Low Voltage Detection (LVD) When using the voltage monitor 1 circuit in Software Standby mode, set up the circuit using the procedures in this section. Setting in Software Standby mode ● When VCC > V is detected, negate the voltage monitor 1 reset signal (LVD1CR0.RN = 0) following a stabilization det1 time.
Page 107: Interrupt And Reset From Voltage Monitor 2
RA2L1 User's Manual 7. Low Voltage Detection (LVD) det1 Lower limit on VCC voltage (VCCmin)* LVD1SR.MON Set to 0 by software LVD1SR.DET bit LVD1CR1.IDTSEL[1:0] bits are set to 10b (when fall and rise are detected) Voltage monitor 1 interrupt request Set to 0 by software LVD1SR.DET bit LVD1CR1.IDTSEL[1:0] bits are...
Page 108 RA2L1 User's Manual 7. Low Voltage Detection (LVD) Table 7.6 Procedures for setting bits related to voltage monitor 2 interrupt and voltage monitor 2 reset so that voltage monitoring occurs (2 of 2) Voltage monitor 2 interrupt (voltage monitor 2 Step ELC event output) Voltage monitor 2 reset...
Page 109: Event Link Controller (Elc) Output
RA2L1 User's Manual 7. Low Voltage Detection (LVD) det2 Lower limit on VCC voltage (VCCmin) LVD2SR.MON bit Set to 0 by software LVD2SR.DET bit LVD2CR1.IDTSEL[1:0] bits are set to 10b (when fall and rise are detected) Voltage monitor 2 interrupt request Set to 0 by software LVD2SR.DET bit LVD2CR1.IDTSEL[1:0] bits are...
Page 110: Usage Notes
RA2L1 User's Manual 7. Low Voltage Detection (LVD) are saved, when the clock supply resumes after returning from Software Standby mode, the event signals for the ELC are output based on the state of the V and V detection flags. det1 det2 Usage Notes...
Page 111: Clock Generation Circuit
RA2L1 User's Manual 8. Clock Generation Circuit Clock Generation Circuit Overview The MCU provides a clock generation circuit. Table 8.1 Table 8.2 list the clock generation circuit specifications. Figure Figure 8.2 show a block diagram, and Table 8.3 lists the I/O pins. Table 8.1 Clock generation circuit specifications for the clock sources Clock source...
Page 112 RA2L1 User's Manual 8. Clock Generation Circuit Table 8.2 Clock generation circuit specifications for the internal clocks (2 of 2) Item Clock source Clock supply Specification CAC HOCO clock HOCO 24/32/48/64 MHz (CACHCLK) CAC IWDTLOCO clock IWDTLOCO 15 kHz (CACILCLK) RTC clock (RTCSCLK/ SOSC/LOCO 32.768 kHz / 128 Hz...
Page 113: Register Descriptions
RA2L1 User's Manual 8. Clock Generation Circuit SCKDIVCR ICK[2:0] CKSEL[2:0] SCKSCR System clock (ICLK) Frequency To CPU, FLASH, Oscillation divider SRAM, and FlashIF stop detection circuit Peripheral module clock 1/16 PCLKB (Peripheral bus) 1/32 1/64 XTAL PCLKD (GPT, ADC) Main clock Main clock oscillator EXTAL...
Page 114: Sckdivcr : System Clock Division Control Register
RA2L1 User's Manual 8. Clock Generation Circuit 8.2.1 SCKDIVCR : System Clock Division Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x020 Bit position: Bit field: — — — — — ICK[2:0] — — — — — — — —...
Page 115: Sckscr : System Clock Source Control Register
RA2L1 User's Manual 8. Clock Generation Circuit 8.2.2 SCKSCR : System Clock Source Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x026 Bit position: Bit field: — — — — — CKSEL[2:0] Value after reset: Symbol Function CKSEL[2:0] Clock Source Select 0 0 0: HOCO 0 0 1: MOCO 0 1 0: LOCO...
Page 116: Fldwaitr : Memory Wait Cycle Control Register For Data Flash
RA2L1 User's Manual 8. Clock Generation Circuit Symbol Function MEMWAIT Memory Wait Cycle Select for Code Flash 0: No wait 1: Wait — These bits are read as 0. The write value should be 0. R/(W) Note: Writing 0 to the MEMWAIT bit is prohibited when SCKDIVCR.ICK bit selects division by 1 and SCKSCR.CKSEL[2:0] bits select the system clock source that is faster than 32 MHz (ICLK >...
Page 117 RA2L1 User's Manual 8. Clock Generation Circuit Note: For Internal Clock Supply Architecture Type B selected by OFS1.ICSATS bit, setting FLDWAIT1 is prohibited. Note: There is no need to set FLDWAIT1 if data flash is not used. The FLDWAITR register controls the wait cycle of data flash read access. FLDWAIT1 bit (Memory Wait Cycle Select for Data Flash) This bit selects the wait cycle of data flash read access.
Page 118 RA2L1 User's Manual 8. Clock Generation Circuit Start ICLK ≤ 32 MHz, MEMWAIT = 0, FLDWAIT1 = 0 Operation mode Set operation mode to = High-speed mode High-speed mode Set MEMWAIT bit to 1 Set FLDWAIT1 bit to 1 Set ICLK > 32 MHz Figure 8.3 When setting ICLK >...
Page 119: Mosccr : Main Clock Oscillator Control Register
RA2L1 User's Manual 8. Clock Generation Circuit ICLK > 32 MHz, MEMWAIT = 1, Start FLDWAIT1 = 1, High-speed mode Set ICLK ≤ 32 MHz Clear MEMWAIT bit to 0 Clear FLDWAIT1 bit to 0 Change the operation mode from High-speed mode Change the operation mode Figure 8.4...
Page 120: Sosccr : Sub-Clock Oscillator Control Register
RA2L1 User's Manual 8. Clock Generation Circuit The main clock oscillator can be started by setting the MOSTP bit to operate. When changing the value of the MOSTP bit, execute subsequent instructions only after reading the bit to check that the value is updated. When using the main clock, the Main Clock Oscillator Mode Oscillation Control Register (MOMCR) and the Main Clock Oscillator Wait Control Register (MOSCWTCR) must be set before setting MOSTP to 0.
Page 121: Lococr : Low-Speed On-Chip Oscillator Control Register
RA2L1 User's Manual 8. Clock Generation Circuit ● When a transition to Software Standby mode is to follow the setting to stop the sub-clock oscillator, wait for at least 3 SOSC clock cycles before executing the WFI instruction. Writing 1 to SOSTP is prohibited under the following condition: ●...
Page 122: Mococr : Middle-Speed On-Chip Oscillator Control Register
RA2L1 User's Manual 8. Clock Generation Circuit Symbol Function HCSTP HOCO Stop 0: Operate the HOCO clock 1: Stop the HOCO clock — These bits are read as 0. The write value should be 0. Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register. Note: Writing to OPCCR.OPCM[1:0] is prohibited while HOCOCR.HCSTP = 0 and OSCSF.HOCOSF = 0 (HOCO is in stabilization wait counting).
Page 123: Oscsf : Oscillation Stabilization Flag Register
RA2L1 User's Manual 8. Clock Generation Circuit After setting MCSTP to 0, use the MOCO clock only after the MOCO clock oscillation stabilization time (t MOCOWT elapses. A fixed stabilization wait time is required after setting the MOCO clock to start operation. A fixed wait time is also required for oscillation to stop after setting the MOCO clock to stop operation.
Page 124: Ostdcr : Oscillation Stop Detection Control Register
RA2L1 User's Manual 8. Clock Generation Circuit ● When the HOCO clock is stopped and the HOCOCR.HCSTP bit is set to 0, and then the HOCO oscillation stabilization time is counted by the MOCO clock and supply of the HOCO clock within the MCU is started. For the HOCO oscillation stabilization time, see section 41, Electrical Characteristics.
Page 125: Ostdsr : Oscillation Stop Detection Status Register
RA2L1 User's Manual 8. Clock Generation Circuit The OSTDE bit must be set to 0 before transitioning to Software Standby mode. To transition to Software Standby mode, first set the OSTDE bit to 0, then execute the WFI instruction. The following restrictions apply when using the oscillation stop detection function: In low-speed mode, selecting division by 1, 2 for ICLK, PCLKB, and PCLKD is prohibited 8.2.12 OSTDSR : Oscillation Stop Detection Status Register...
Page 126: Momcr : Main Clock Oscillator Mode Oscillation Control Register
RA2L1 User's Manual 8. Clock Generation Circuit Symbol Function MSTS[3:0] Main Clock Oscillator Wait Time Setting 0x0: Wait time = 2 cycles (0.25 µs) 0x1: Wait time = 1024 cycles (128 µs) 0x2: Wait time = 2048 cycles (256 µs) 0x3: Wait time = 4096 cycles (512 µs) 0x4: Wait time = 8192 cycles (1024 µs) 0x5: Wait time = 16384 cycles (2048 µs)
Page 127: Somcr : Sub-Clock Oscillator Mode Control Register
RA2L1 User's Manual 8. Clock Generation Circuit MOSEL bit (Main Clock Oscillator Switching) The MOSEL bit switches the source for the main clock oscillator. 8.2.15 SOMCR : Sub-Clock Oscillator Mode Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x481 Bit position: Bit field: —...
Page 128: Ckocr : Clock Out Control Register
RA2L1 User's Manual 8. Clock Generation Circuit 8.2.17 CKOCR : Clock Out Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x03E Bit position: CKOE Bit field: CKODIV[2:0] — CKOSEL[2:0] Value after reset: Symbol Function CKOSEL[2:0] Clock Out Source Select 0 0 0: HOCO 0 0 1: MOCO 0 1 0: LOCO...
Page 129: Locoutcr : Loco User Trimming Control Register
RA2L1 User's Manual 8. Clock Generation Circuit 8.2.18 LOCOUTCR : LOCO User Trimming Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x492 Bit position: Bit field: LOCOUTRM[7:0] Value after reset: Symbol Function LOCOUTRM[7:0] LOCO User Trimming 0x80: -128 0x81: -127 ⋮...
Page 130: Hocoutcr : Hoco User Trimming Control Register
RA2L1 User's Manual 8. Clock Generation Circuit 8.2.20 HOCOUTCR : HOCO User Trimming Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x062 Bit position: Bit field: HOCOUTRM[7:0] Value after reset: Symbol Function HOCOUTRM[7:0] HOCO User Trimming 0x80: -128 0x81: -127 ⋮...
Page 131: External Clock Input
RA2L1 User's Manual 8. Clock Generation Circuit EXTAL XTAL Figure 8.5 Example of crystal resonator connection Figure 8.6 shows an equivalent circuit of the crystal resonator. XTAL EXTAL Figure 8.6 Equivalent circuit of the crystal resonator 8.3.2 External Clock Input Figure 8.7 shows an example of connecting an external clock input.
Page 132: Connecting A 32.768-Khz Crystal Resonator
RA2L1 User's Manual 8. Clock Generation Circuit 8.4.1 Connecting a 32.768-kHz Crystal Resonator To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal resonator as shown in Figure 8.8. A damping resistor (Rd) can be added, if necessary. Because the resistor values vary according to the resonator and the oscillation drive capability, use values recommended by the resonator manufacturer.
Page 133: Oscillation Stop Detection Function
RA2L1 User's Manual 8. Clock Generation Circuit Oscillation Stop Detection Function 8.5.1 Oscillation Stop Detection and Operation after Detection The oscillation stop detection function detects the main clock oscillator stop. When oscillation stop is detected, the system clock switches as follows: ●...
Page 134: Oscillation Stop Detection Interrupts
RA2L1 User's Manual 8. Clock Generation Circuit Example of returning when CKSEL[2:0] = 011b (selecting the main clock oscillator) after an oscillation stop is detected Start (oscillation stop is detected) Switch to clock sources other than MOSC Example: Switch to SCKSCR.CKSEL[2:0] = 001b (selecting the MOCO) Set OSTDCR.OSTDIE = 0 Read OSTDSR.OSTDF = 1...
Page 135: Internal Clock
RA2L1 User's Manual 8. Clock Generation Circuit The oscillation stop detection interrupt is a non-maskable interrupt. Because non-maskable interrupts are disabled in the initial state after a reset release, enable non-maskable interrupts through software before using oscillation stop detection interrupts. For details, see section 12, Interrupt Controller Unit (ICU).
Page 136: Peripheral Module Clock (Pclkb, Pclkd)
RA2L1 User's Manual 8. Clock Generation Circuit ICK[2:0] SCKDIVCR SCKSCR CKSEL[2:0] PCKx[2:0] Frequency divider Main clock oscillator Sub-clock oscillator ICLK Selected clock HOCO PCLKx 1/16 1/32 MOCO 1/64 LOCO Figure 8.12 Block diagram of clock source selector Source A SCKSCR.CKSEL[2:0] Source B ICLK (SCKDIVCR.ICK[2:0] = 000b)
Page 137: Rtc-Dedicated Clock (Rtcsclk, Rtcs128Clk, Rtclclk)
RA2L1 User's Manual 8. Clock Generation Circuit The CAC clock, CACCLK, is the operating clock for the CAC. CACCLK is generated by the following oscillators: ● Main clock oscillator ● Sub-clock oscillator ● High-speed clock oscillator (HOCO) ● Middle-speed clock oscillator (MOCO) ●...
Page 138: Notes On Resonator
RA2L1 User's Manual 8. Clock Generation Circuit 8.7.2 Notes on Resonator Because various resonator characteristics relate closely to your board design, adequate evaluation is required before use. See the resonator connection example in Figure 8.8. The circuit constants for the resonator depend on the resonator to be used and the stray capacitance of the mounting circuit.
Page 139: Clock Frequency Accuracy Measurement Circuit (Cac)
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) Clock Frequency Accuracy Measurement Circuit (CAC) Overview The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock selected as the measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.When measurement is complete or the number of pulses within the time generated by the measurement reference clock is not within the allowable range, an interrupt request is generated.
Page 140: Register Descriptions
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) DFS[1:0] CACREFE DFS[1:0] CACREF pin Digital filter RSCS[2:0] RCDS[1:0] EDGES[1:0] 1/32 Reference 1/128 Edge detection signal circuit generation 1/1024 clock select 1/8192 circuit Valid edge signal FMCS[2:0] TCSS[1:0] Frequency measurement clock MOSC CFME...
Page 141: Cacr1 : Cac Control Register 1
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) 9.2.2 CACR1 : CAC Control Register 1 Base address: CAC = 0x4004_4600 Offset address: 0x01 Bit position: CACR Bit field: EDGES[1:0] TCSS[1:0] FMCS[2:0] Value after reset: Symbol Function CACREFE CACREF Pin Input Enable 0: Disable 1: Enable FMCS[2:0]...
Page 142: Caicr : Cac Interrupt Control Register
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) Symbol Function Reference Signal Select 0: CACREF pin input 1: Internal clock (internally generated signal) RSCS[2:0] Measurement Reference Clock Select 0 0 0: Main clock oscillator 0 0 1: Sub-clock oscillator 0 1 0: HOCO clock 0 1 1: MOCO 1 0 0: LOCO clock...
Page 143: Castr : Cac Status Register
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) Symbol Function MENDIE Measurement End Interrupt Request Enable 0: Disable 1: Enable OVFIE Overflow Interrupt Request Enable 0: Disable 1: Enable — This bit is read as 0. The write value should be 0. FERRFCL FERRF Clear 0: No effect...
Page 144: Caulvr : Cac Upper-Limit Value Setting Register
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) Symbol Function OVFF Overflow Flag 0: Counter has not overflowed 1: Counter overflowed — These bits are read as 0. FERRF flag (Frequency Error Flag) The FERRF flag indicates a deviation of the clock frequency from the set value (frequency error). [Setting condition] ●...
Page 145: Callvr : Cac Lower-Limit Value Setting Register
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) 9.2.7 CALLVR : CAC Lower-Limit Value Setting Register Base address: CAC = 0x4004_4600 Offset address: 0x08 Bit position: Bit field: Value after reset: Symbol Function 15:0 The Lower Value of the Allowable Range The CALLVR register is a 16-bit read/write register that specifies the lower value of the allowable range.
Page 146 RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) CACREF pin or internal clock CFME bit in CACR0 0 is written to 1 is written to CFME bit. Counter value CFME bit. 0xFFFF Counter is After 1 is written to CFME bit, counting cleared by writing starts on the first valid edge.
Page 147: Digital Filtering Of Signals On Cacref Pin
RA2L1 User's Manual 9. Clock Frequency Accuracy Measurement Circuit (CAC) 9.3.2 Digital Filtering of Signals on CACREF Pin The CACREF pin has a digital filter, and levels on the CACREF pin are transmitted to the internal circuitry after three consecutive matches in the selected sampling interval. The same level continues to be transmitted internally until the level on the pin has three consecutive matches again.
Page 148: Low Power Modes
RA2L1 User's Manual 10. Low Power Modes Low Power Modes 10.1 Overview The MCU provides several functions for reducing power consumption, such as setting clock dividers, stopping modules, selecting power control mode in normal mode, and transitioning to low power modes. Table 10.1 lists the specifications of the low power mode functions.
Page 149 RA2L1 User's Manual 10. Low Power Modes Table 10.2 Operating conditions of each low power mode (2 of 2) Item Sleep mode Software Standby mode Snooze mode Independent Watchdog Timer (IWDT) Selectable Selectable Selectable Realtime clock (RTC) Selectable Selectable Selectable Low Power Asynchronous General Purpose Selectable Selectable...
Page 150 RA2L1 User's Manual 10. Low Power Modes Table 10.3 Available interrupt sources to transition to Normal mode from Snooze mode and Software Standby mode (2 of 2) Interrupt source Name Software Standby mode Snooze mode LVD_LVD1 LVD_LVD2 IWDT IWDT_NMIUNDF RTC_ALM RTC_PRD KINT KEY_INTKR...
Page 151: Register Descriptions
RA2L1 User's Manual 10. Low Power Modes SBYCR.SSBY = 0 Reset state Sleep mode WFI instruction RES pin = High SNZCR.SNZE = 1 All interrupts Snooze mode Interrupt Snooze request Snooze end condition Normal mode (program execution state) WFI instruction SBYCR.SSBY = 1 Interrupt Software Standby mode...
Page 152: Mstpcra : Module Stop Control Register A
RA2L1 User's Manual 10. Low Power Modes While the FENTRYR.FENTRY0 bit is 1 setting of the SSBY bit is ignored. Even if SSBY bit is 1, the MCU enters Sleep mode on execution of a WFI instruction. While the DCDCCTL.PD bit is 0, DCDCCLT.FST bit is 0 and DCDCCTL.DCDCON bit is 1, setting of the SSBY bit is ignored.
Page 153: Mstpcrc : Module Stop Control Register C
RA2L1 User's Manual 10. Low Power Modes Symbol Function MSTPB9 C Bus Interface 0 Module Stop Target module: IIC0 0: Cancel the module-stop state 1: Enter the module-stop state 17:10 — These bits are read as 1. The write value should be 1. MSTPB18 Serial Peripheral Interface 1 Module Stop Target module: SPI1...
Page 154: Mstpcrd : Module Stop Control Register D
RA2L1 User's Manual 10. Low Power Modes Symbol Function MSTPC1 Cyclic Redundancy Check Calculator Module Stop Target module: CRC 0: Cancel the module-stop state 1: Enter the module-stop state — These bits are read as 1. The write value should be 1. MSTPC3 Capacitive Touch Sensing Unit Module Stop Target module: CTSU...
Page 155: Opccr : Operating Power Control Register
RA2L1 User's Manual 10. Low Power Modes Symbol Function MSTPD3 Low Power Asynchronous General Purpose Timer 0 Module Stop Target module: AGT0 0: Cancel the module-stop state 1: Enter the module-stop state — This bit is read as 1. The write value should be 1. MSTPD5 General PWM Timer 32n Module Stop Target module: GPT32n (n = 0 to 3)
Page 156: Sopccr : Sub Operating Power Control Register
RA2L1 User's Manual 10. Low Power Modes Symbol Function — These bits are read as 0. The write value should be 0. OPCMTSF Operating Power Control Mode Transition Status Flag 0: Transition completed 1: During transition — These bits are read as 0. The write value should be 0. The OPCCR register is used to reduce power consumption in Normal mode, Sleep mode and Snooze mode.
Page 157: Snzcr : Snooze Control Register
RA2L1 User's Manual 10. Low Power Modes For the procedure to change operating power control modes, see section 10.5. Function for Lower Operating Power Consumption. SOPCM bit (Sub Operating Power Control Mode Select) The SOPCM bit selects the operating power control mode in Normal mode, Sleep mode, and Snooze mode. Setting this bit to 1 allows transition to Subosc-speed mode.
Page 158: Snzedcr0 : Snooze End Control Register 0
RA2L1 User's Manual 10. Low Power Modes Symbol Function SNZE Snooze mode Enable 0: Disable Snooze mode 1: Enable Snooze mode Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. RXDREQEN bit (RXD0 Snooze Request Enable) The RXDREQEN bit specifies whether to detect a falling edge of the RXD0 pin in Software Standby mode.
Page 159: Snzreqcr0 : Snooze Request Control Register 0
RA2L1 User's Manual 10. Low Power Modes The SNZEDCR0 register controls the condition of switching from Snooze mode to Software Standby mode. In order to use a trigger shown in Table 10.7 as a condition to switch from Snooze mode to Software Standby mode, the corresponding bitin the SNZEDCR0 register must be set to 1.
Page 160 RA2L1 User's Manual 10. Low Power Modes Symbol Function SNZREQEN0 Enable IRQ0 pin snooze request 0: Disable the snooze request 1: Enable the snooze request SNZREQEN1 Enable IRQ1 pin snooze request 0: Disable the snooze request 1: Enable the snooze request SNZREQEN2 Enable IRQ2 pin snooze request 0: Disable the snooze request...
Page 161: Psmcr : Power Save Memory Control Register
RA2L1 User's Manual 10. Low Power Modes 10.2.11 PSMCR : Power Save Memory Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x09F Bit position: Bit field: — — — — — — PSMC[1:0] Value after reset: Symbol Function PSMC[1:0] Power Save Memory Control 0 0: All SRAMs are on in Software Standby mode 0 1: 8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in Software Standby mode...
Page 162: Dcdcctl : Dcdc/Ldo Control Register
RA2L1 User's Manual 10. Low Power Modes 10.2.13 DCDCCTL : DCDC/LDO Control Register Base address: SYSC = 0x4001_E000 Offset address: 0x440 Bit position: LCBO STOP OCPE DCDC Bit field: — — Value after reset: Symbol Function DCDCON LDO/DCDC on/off Control bit 0: LDO is on and DCDC is off 1: LDO is off and DCDC is on OCPEN...
Page 163: Lsmrwdis : Low Speed Module R/W Disable Control Register
RA2L1 User's Manual 10. Low Power Modes Symbol Function VCCSEL[1:0] DCDC Working Voltage Level Selection Set VCCSEL[1:0] to the following voltage when the VCC level is detected in DCDC Power mode. 0 0: 2.7 V ≤ VCC < 3.6 V 0 1: 3.6 V ≤...
Page 164: Lpopt : Lower Power Operation Control Register
RA2L1 User's Manual 10. Low Power Modes ● Do not set this bit to 1 when WDT is in auto start mode (OFS0.WDTSTRT = 0). ● Do not set this bit to 1 when WDT is operating. ● Set this bit to 1 to disable register start mode for WDT. IWDTIDS bit (IWDT Register Clock Control) [Setting condition] ●...
Page 165: Reducing Power Consumption By Switching Clock Signals
RA2L1 User's Manual 10. Low Power Modes ● Do not set this bit to 1 when operating code flash or data flash through the Flash register. ● Do not set this bit to 1 when operating data flash. ● Do not set this bit to 1 when system transfers power control mode (for example, transfer High-speed mode to Middle- speed mode or transfer High-speed mode to Low-speed mode).
Page 166 RA2L1 User's Manual 10. Low Power Modes 3. Confirm that the OPCCR.OPCMTSF flag is 0 (indicates transition completed). 4. Set the OPCCR.OPCM[1:0] bits to 11b (Low-speed mode). 5. Confirm that OPCCR.OPCMTSF flag is 0 (indicates transition completed). (Operation is now in Low-speed mode) Example 2: From High-speed mode to Subosc-speed mode (Operation begins in High-speed mode) 1.
Page 167: Low Power Modes
RA2L1 User's Manual 10. Low Power Modes 1. Set the VCCSEL.VCCSEL[1:0] bits according to expected range of power supply voltage. 2. Monitor the voltage level of VCC, confirm the VCC voltage is more than 2.40 V. 3. Set one of the LVD 0/1/2 detection voltage to more than 2.40 V with LVDLVLR or OFS1.VDSEL. 4.
Page 168: Operating Range
RA2L1 User's Manual 10. Low Power Modes Switching from High-speed/Middle-speed mode in DCDC power mode to Subosc-speed mode or Software Standby mode In DCDC power mode, the MCU cannot transfer to Subosc-speed mode (LDO power mode) or Software Standby mode (LDO power mode) directly.
Page 169 RA2L1 User's Manual 10. Low Power Modes Figure 10.4 shows the operating voltages and frequencies in High-speed mode. VCC[V] VCC[V] Except P/E 0.032768 ICLK[MHz] 0.032768 ICLK[MHz] Figure 10.4 Operating voltages and frequencies in High-speed mode Middle-speed mode The power consumption of this mode is lower than that of High-speed mode under the same conditions. The maximum operating frequency during a flash read is 24 MHz for ICLK.
Page 170: Sleep Mode
RA2L1 User's Manual 10. Low Power Modes VCC[V] VCC[V] Except P/E 0.032768 ICLK[MHz] 0.032768 ICLK[MHz] Figure 10.6 Operating voltages and frequencies in Low-speed mode Subosc-speed mode The maximum operating frequency during a flash read is 37.6832 kHz for ICLK. The operating voltage range during a flash read is 1.6 to 5.5 V.
Page 171: Canceling Sleep Mode
RA2L1 User's Manual 10. Low Power Modes Counting by IWDT continues when the MCU enters Sleep mode while the IWDT is in auto start mode and the OFS0.IWDTSTPCTL bit is 0 (IWDT does not stop in Sleep mode, Software Standby mode or Snooze mode). Counting by WDT stops when the MCU enters Sleep mode while the WDT is in auto start mode and the OFS0.WDTSTPCTL bit is 1 (WDT stops in Sleep mode).
Page 172: Software Standby Mode
RA2L1 User's Manual 10. Low Power Modes 10.7 Software Standby Mode 10.7.1 Transition to Software Standby Mode When a WFI instruction is executed while SBYCR.SSBY bit is 1, the MCU enters Software Standby mode. In this mode, the CPU, most of the on-chip peripheral functions and oscillators stop. However, the contents of the CPU internal registers and SRAM data, the states of on-chip peripheral functions and the I/O ports are retained.
Page 173: Example Of Software Standby Mode Application
RA2L1 User's Manual 10. Low Power Modes 5. Canceling by IWDT reset Software Standby mode is canceled by an internal reset generated by an IWDT underflow and the MCU starts the reset exception handling. However, IWDT stops in Software Standby mode and an internal reset for canceling Software Standby mode is not generated in the following condition: ●...
Page 174: Canceling Snooze Mode
RA2L1 User's Manual 10. Low Power Modes Snooze Control Circuit ELSRx WUPEN.bn SNZCR.b7 SYSTEM_SNZREQ Wakeup request Event control (Snooze entry) SNZREQCR.bn Control Interrupt request Snooze request n = 0 to 7, 17, 23 to 25, 28 to 30 Noise filter SNZCR.b0 Edge detect SCI0...
Page 175: Returning From Snooze Mode To Software Standby Mode
RA2L1 User's Manual 10. Low Power Modes Trigger Interrupt instruction detection request High Standby cancel signal Snooze end signal Software Normal Standby Operating Low power mode mode Snooze mode Normal mode mode(OPE) Oscillation Oscillator Oscillates stopped Oscillates for system clock Wait for oscillation accuracy stabilization Note 1.
Page 176: Snooze Operation Example
RA2L1 User's Manual 10. Low Power Modes Table 10.8 Snooze end conditions Operating module when a snooze end request occurs Snooze end request The MCU transfers to the Software Standby mode after all of the modules listed in this table complete operation.
Page 177 RA2L1 User's Manual 10. Low Power Modes Start Snooze mode setting Setting for ELC in Snooze mode MSTPCRC.MSTPC14 = 0 Cancel module-stop state of ELC Snooze entry (SYSTEM_SNZREQ) ELSRx.ELS = 0x3C signal is linked to modules ELCR.ELCON = 1 ELC function enabled Setting for snooze cancel Select event number as the source of...
Page 178 RA2L1 User's Manual 10. Low Power Modes The MCU can transmit and receive data in SCI0 asynchronous mode without CPU intervention. When using the SCI0 in Snooze mode, use one of the following operating modes: ● High-speed mode ● Middle-speed mode ●...
Page 179 RA2L1 User's Manual 10. Low Power Modes Start Snooze mode setting Setting for SCI0 in Snooze mode MSTPCRB.MSTPB31 = 0 Cancel module-stop state of SCI0 Set SCI0 With SCI0, set as asynchronous UART receive mode SCKSCR.CKSEL = 0 The clock source must be HOCO MOCOCR.MCSTP = 1 Stop MOCO and the main clock oscillator MOSCCR.MOSTP =1...
Page 180: Usage Notes
RA2L1 User's Manual 10. Low Power Modes 10.9 Usage Notes 10.9.1 Register Access Do not write to registers listed in this section in any of the following conditions: [Registers] ● All registers with a peripheral name of SYSTEM. [Conditions] ● OPCCR.OPCMTSF = 1 or SOPCCR.SOPCMTSF = 1 (during transition of the operating power control mode) ●...
Page 181: I/O Port Pin States
RA2L1 User's Manual 10. Low Power Modes Do not write to registers listed in this section by DTC: [Registers] ● MSTPCRA, MSTPCRB, MSTPCRC, MSTPCRD. Do not write to registers listed in this section in Snooze mode. They must be set before entering Software Standby mode: [Registers] ●...
Page 182: Using Uart Of Sci0 In Snooze Mode
RA2L1 User's Manual 10. Low Power Modes MCU to transfer from Software Standby mode to Snooze mode unexpectedly. In this case if the MCU does not receive RXD0 data after the noise, an interrupt such as SCI0_ERI or SCI0_RXI, or an address mismatch event is not generated and the MCU stays in Snooze mode.
Page 183 RA2L1 User's Manual 10. Low Power Modes Turn the power on Release the protection of the Protect Register PRCR.PRC1 = 1 Release from the module-stop state MSTPCRC.MSTPC28 = 0 Wait for 3 PCLKB cycles for example: dummy = PORT1.PODR.BYTE; while (dummy != PORT1.PODR.BYTE) { } Transition to the module-stop state MSTPCRC.MSTPC28 = 1 Set the Protect Register...
Page 184: Register Write Protection
RA2L1 User's Manual 11. Register Write Protection Register Write Protection 11.1 Overview The register write protection function protects important registers from being overwritten due to software errors. The registers to be protected are set with the Protect Register (PRCR). Table 11.1 lists the association between the bits in the PRCR register and the registers to be protected.
Page 185: Interrupt Controller Unit (Icu)
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Interrupt Controller Unit (ICU) 12.1 Overview The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC), and the Data Transfer Controller (DTC) modules. The ICU also controls non-maskable interrupts. Table 12.1 lists the ICU specifications, Figure 12.1...
Page 186: Register Descriptions
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Interrupt Controller CPU Stack pointer monitor error MPU Bus Master error MPU Bus Slave error SRAM ECC error SRAM Parity error Clock IWDT underflow/refresh error Clock recovery request generation WDT underflow/refresh error Oscillation stop detection interrupt circuit Voltage monitor 2 interrupt...
Page 187: Nmisr : Non-Maskable Interrupt Status Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Symbol Function — These bits are read as 0. The write value should be 0. FCLKSEL[1:0] IRQi Digital Filter Sampling Clock Select 0 0: PCLKB 0 1: PCLKB/8 1 0: PCLKB/32 1 1: PCLKB/64 —...
Page 188 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Symbol Function WDTST WDT Underflow/Refresh Error Status Flag 0: Interrupt not requested 1: Interrupt requested LVD1ST Voltage Monitor 1 Interrupt Status Flag 0: Interrupt not requested 1: Interrupt requested LVD2ST Voltage Monitor 2 Interrupt Status Flag 0: Interrupt not requested 1: Interrupt requested —...
Page 189 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) When 1 is written to the NMICLR.WDTCLR bit. LVD1ST flag (Voltage Monitor 1 Interrupt Status Flag) The LVD1ST flag indicates a request for voltage monitor 1 interrupt. It is read-only and cleared by the NMICLR.LVD1CLR bit.
Page 190: Nmier : Non-Maskable Interrupt Enable Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) BUSSST flag (MPU Bus Slave Error Interrupt Status Flag) The BUSSST flag indicates a bus slave error interrupt request. [Setting condition] When an interrupt is generated in response to a bus slave error. [Clearing condition] When 1 is written to the NMICLR.BUSSCLR bit.
Page 191 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Symbol Function RPEEN SRAM Parity Error Interrupt Enable 0: Disabled 1: Enabled RECCEN SRAM ECC Error Interrupt Enable 0: Disabled 1: Enabled BUSSEN MPU Bus Slave Error Interrupt Enable 0: Disabled 1: Enabled BUSMEN MPU Bus Master Error Interrupt Enable 0: Disabled...
Page 192: Nmiclr : Non-Maskable Interrupt Status Clear Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) 12.2.4 NMICLR : Non-Maskable Interrupt Status Clear Register Base address: ICU = 0x4000_6000 Offset address: 0x130 Bit position: SPEC BUSM BUSS RECC RPEC NMICL OSTC LVD2C LVD1C WDTC IWDT Bit field: — —...
Page 193: Nmicr : Nmi Pin Interrupt Control Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) LVD1CLR bit (LVD1 Clear) Writing 1 to the LVD1CLR bit clears the NMISR.LVD1ST flag. This bit is read as 0. LVD2CLR bit (LVD2 Clear) Writing 1 to the LVD2CLR bit clears the NMISR.LVD2ST flag. This bit is read as 0. OSTCLR bit (OST Clear) Writing 1 to the OSTCLR bit clears the NMISR.OSTST flag.
Page 194: Ielsrn : Icu Event Link Setting Register N (N = 0 To 31)
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) NFCLKSEL[1:0] bits (NMI Digital Filter Sampling Clock Select) The NFCLKSEL[1:0] bits select the digital filter sampling clock for the NMI pin interrupts, selectable to: ● PCLKB (every cycle) ● PCLKB/8 (once every eight cycles) ●...
Page 195: Selsr0 : Sys Event Link Setting Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) IR flag (Interrupt Status Flag) The IR status flag indicates an individual interrupt request from the event specified in IELS[4:0]. [Setting condition] When an interrupt request is received from the associated peripheral module or IRQi pin. [Clearing condition] When 0 is written to the IR flag.
Page 196: Wupen : Wake Up Interrupt Enable Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) 12.2.8 WUPEN : Wake Up Interrupt Enable Register Base address: ICU = 0x4000_6000 Offset address: 0x1A0 Bit position: AGT1 AGT1 AGT1 RTCP RTCA ACMP LVD2 LVD1 IWDT IIC0W KEYW Bit field: CBWU CAWU UDWU —...
Page 197 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Symbol Function IIC0WUPEN IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable 0: Software Standby/Snooze Mode returns by IIC0 address match interrupt disabled 1: Software Standby/Snooze Mode returns by IIC0 address match interrupt enabled The bits in this register control whether the associated interrupt can wake up the CPU from Software Standby/Snooze Mode mode.
Page 198: Ielen : Icu Event Enable Register
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) 12.2.9 IELEN : ICU event Enable Register Base address: ICU = 0x4000_6000 Offset address: 0x1C0 Bit position: RTCIN Bit field: — — — — — — IELEN Value after reset: Symbol Function RTCINTEN RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit = 1) 0: Disable...
Page 199: Event Number
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.3 Interrupt vector table (2 of 2) Exception Vector number IRQ number offset Source Description — 0x030 Reserved — 0x034 Reserved — 0x038 Pendable request for system service (PendableSrvReq) — 0x03C System Tick Timer (SysTick) 0x040 ICU.IELSR0...
Page 200 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Heading Description Interrupt request source Name of the source generating the interrupt request Name Name of the interrupt Connect to NVIC “ ✓” indicates the interrupt can be used as a CPU interrupt Invoke DTC “...
Page 201 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.4 Event table (2 of 5) IELSRn Interrupt Canceling Event request Connect to Canceling Software number source Name NVIC Invoke DTC Snooze Standby 0x1C ADC12 ADC120_ADI — — ✓ ✓ 0x1D ADC120_GBADI —...
Page 202 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.4 Event table (3 of 5) IELSRn Interrupt Canceling Event request Connect to Canceling Software number source Name NVIC Invoke DTC Snooze Standby 0x49 GPT0_CMPD — — ✓ ✓ 0x4A GPT0_OVF —...
Page 203 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.4 Event table (4 of 5) IELSRn Interrupt Canceling Event request Connect to Canceling Software number source Name NVIC Invoke DTC Snooze Standby 0x71 SCI0 SCI0_RXI — — ✓ ✓ 0x72 SCI0_TXI —...
Page 204: Icu And Dtc Event Number
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.4 Event table (5 of 5) IELSRn Interrupt Canceling Event request Connect to Canceling Software number source Name NVIC Invoke DTC Snooze Standby 0x98 GPT167 GPT7_CCMPA — — ✓ ✓ 0x99 GPT7_CCMPB —...
Page 205 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.5 ICU input link select (1) (2 of 2) group0 (interrupt ch group1 (interrupt ch group2 (interrupt ch group3 (interrupt ch IELS[4:0] IELSR0/8/16/24) IELSR1/9/17/25) IELSR2/10/18/26) IELSR3/11/19/27) 0x0B IIC0_WUI CAC_FERRI POEG_GROUP0 POEG_GROUP1 0x0C CAN0_ERS CAN0_RXF...
Page 206 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.6 ICU input link select (2) (2 of 2) group4 (interrupt ch group5 (interrupt ch group6 (interrupt ch group7 (interrupt ch IELSR IELS[4:0] IELSR4/12/20/28) IELSR5/13/21/29) IELSR6/14/22/30) 7/15/23/31) 0x11 GPT_UVWEDGE SPI0_SPTI SPI0_SPTEND PORT_IRQ7 0x12 SCI0_RXI...
Page 207 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.7 Register setting for event (2 of 5) IELSRn.IELS[4:0] Group 0 (n = Group 1 (n = Group 2 (n = Group 3 (n = Group 4 (n = Group 5 (n = Group 6 (n = Group 7 (n = Name...
Page 208 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.7 Register setting for event (3 of 5) IELSRn.IELS[4:0] Group 0 (n = Group 1 (n = Group 2 (n = Group 3 (n = Group 4 (n = Group 5 (n = Group 6 (n = Group 7 (n = Name...
Page 209 RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.7 Register setting for event (4 of 5) IELSRn.IELS[4:0] Group 0 (n = Group 1 (n = Group 2 (n = Group 3 (n = Group 4 (n = Group 5 (n = Group 6 (n = Group 7 (n = Name...
Page 210: Interrupt Operation
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Table 12.7 Register setting for event (5 of 5) IELSRn.IELS[4:0] Group 0 (n = Group 1 (n = Group 2 (n = Group 3 (n = Group 4 (n = Group 5 (n = Group 6 (n = Group 7 (n = Name...
Page 211: Interrupt Setting Procedure
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Set the IRQCRi.IRQMD[1:0] bits to select the detection mode for the IRQi pins. For interrupt sources associated with peripheral modules, see Table 12.3 Table 12.4. Events must be accepted by the NVIC before an interrupt occurs and is accepted by the CPU.
Page 212: Selecting Interrupt Request Destinations
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) 12.5.4 Selecting Interrupt Request Destinations The available destinations are fixed for each interrupt, as described in Table 12.3, Table 12.4 Table 12.6. The interrupt output destination, CPU, or DTC can be independently selected for each interrupt source. Use an interrupt request destination setting that is indicated by a “✓”...
Page 213: External Pin Interrupts
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) Sampling clock for digital filter IRQCRi.FLTEN bit Pulses removed The level matches three times IRQi pin The level matches three times IRQi_d (internal F/F) Digital filter enabled Disabled Enabled Operation example with IRQCRi.IRQMD[1:0] = 11b (low-level detection) Note 1.
Page 214: Return From Low Power Modes
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) ● MPU bus slave error interrupt ● CPU stack pointer monitor interrupt Non-maskable interrupts can only be used with the CPU, not to activate the DTC. Non-maskable interrupts take precedence over all other interrupts. The non-maskable interrupt states can be verified in the Non-Maskable Interrupt Status Register (NMISR).
Page 215: Using The Wfi Instruction With Non-Maskable Interrupts
RA2L1 User's Manual 12. Interrupt Controller Unit (ICU) 3. Select the CPU as the interrupt request destination. 4. Enable the interrupt in the NVIC. Note: In Snooze mode, a clock is supplied to the ICU. If an event selected in IELSRn is detected, the CPU acknowledges the interrupt after returning to Normal mode from Software Standby mode.
Page 216: Buses
RA2L1 User's Manual 13. Buses Buses 13.1 Overview Table 13.1 lists the bus specifications, Figure 13.1 shows the bus configuration, and Table 13.2 lists the addresses assigned for each bus. Table 13.1 Bus specifications Bus type Description Main bus System bus (CPU) ●...
Page 217: Description Of Buses
RA2L1 User's Manual 13. Buses Table 13.2 Addresses assigned for each bus (2 of 2) Address Area 0x4001_9000 to 0x4001_9FFF Memory bus 4 MTB I/O registers 0x4001_A000 to 0x4001_FFFF Internal peripheral bus 1 Peripheral I/O registers 0x4004_0000 to 0x400B_FFFF Internal peripheral bus 3 0x400C_0000 to 0x400D_FFFF Internal peripheral bus 7 Peripheral I/O registers(AES,TRNG)
Page 218: Register Descriptions
RA2L1 User's Manual 13. Buses 13.3 Register Descriptions 13.3.1 BUSMCNTx : Master Bus Control Register x (x = SYS, DMA) Base address: BUS = 0x4000_3000 Offset address: 0x1008 (BUSMCNTSYS) 0x100C (BUSMCNTDMA) Bit position: Bit field: IERES — — — — —...
Page 219: Busnerrstat : Bus Error Status Register N (N = 3, 4)
RA2L1 User's Manual 13. Buses 13.3.3 BUSnERRSTAT : BUS Error Status Register n (n = 3, 4) Base address: BUS = 0x4000_3000 Offset address: 0x1824 (n = 3) 0x1834 (n = 4) Bit position: ERRS ACCS Bit field: — — —...
Page 220: Conditions For Issuing Illegal Address Access Errors
RA2L1 User's Manual 13. Buses cleared by reset only. For more information, see section 13.3.2. BUSnERRADD : Bus Error Address Register n (n = 3, 4) section 13.3.3. BUSnERRSTAT : BUS Error Status Register n (n = 3, Note: DTC does not receive bus errors. If the DTC accesses the bus, the transfer continues. 13.4.3 Conditions for issuing illegal Address Access Errors Table 13.4...
Page 221: Memory Protection Unit (Mpu)
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Memory Protection Unit (MPU) 14.1 Overview The MCU has four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided. Table 14.1 lists the MPU specifications, and Table 14.2 shows the behavior on detection of each MPU error.
Page 222 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Table 14.3 CPU stack pointer monitor specifications (2 of 2) Parameter Description Number of regions 2 regions: ● Main Stack Pointer (MSP) ● Process Stack Pointer (PSP). Address specification for individual regions Specifying start and end addresses for individual regions Stack pointer monitor enable or disable setting for Enabling or disabling stack pointer monitor for individual regions...
Page 223 RA2L1 User's Manual 14. Memory Protection Unit (MPU) CPU processer register set Process Stack Main Stack R13 (SP) Pointer (PSP) Pointer (MSP) R14 (LR) R15 (PC) xPSR CPU stack pointer monitor Main stack pointer monitor ENABLE Start address address Reset Compare Non-maskable (within)
Page 224: Protecting The Registers
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Start Write to MSPMPUSA and MSPMPUEA registers Write to PSPMPUSA and PSPMPUEA registers Write to MSPMPUCTL and PSPMPUCTL registers Write to MSPMPUOAD and PSPMPUOAD registers Write to MSPMPUPT and PSPMPUPT register Figure 14.2 CPU stack pointer monitor register setting flow 14.2.1 Protecting the Registers...
Page 225 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function 31:0 MSPMPUSA[31:0] Region Start Address Address where the region starts, for use in region determination. The lower 2 bits should be 0. The value range is from 0x1FF0_0000 to 0x200F_FFFC, excluding reserved areas.
Page 226 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function 31:0 PSPMPUEA[31:0] Region End Address Address where the region ends, for use in region determination. The lower 2 bits should be 1. The value range is from 0x1FF0_0003 to 0x200F_FFFF, excluding reserved areas.
Page 227 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function ENABLE Stack Pointer Monitor Enable 0: Stack pointer monitor is disabled 1: Stack pointer monitor is enabled — These bits are read as 0. The write value should be 0. ERROR Stack Pointer Monitor Error Flag 0: Stack pointer has not overflowed or underflowed...
Page 228: Arm Mpu
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function PROTECT Protection of Register 0: Stack pointer monitor register writes are permitted. 1: Stack pointer monitor register writes are protected. Reads are permitted — These bits are read as 0. The write value should be 0. 15:8 KEY[7:0] Key Code...
Page 229 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Table 14.4 Bus master MPU specifications Parameter Description Protected master groups ● Bus master MPU group A: DMA bus Protected regions 0x0000_0000 to 0xFFFF_FFFF Number of regions ● Bus master MPU group A: 4 regions Address specification for individual regions ●...
Page 230: Register Descriptions
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Bus master MPU group A Start Write Read Enable Enable address address protect protect Region Compare control (within) circuit Master control Region 0 circuit Region 1 Region 2 Region 3 Error status Group A address Group A write access Reset...
Page 231 RA2L1 User's Manual 14. Memory Protection Unit (MPU) 14.4.1.3 MMPUACAn : Group A Region n access control register (n = 0 to 3) Base address: MPU = 0x4000_0000 Offset address: 0x200 + 0x010 × n Bit position: ENAB Bit field: —...
Page 232 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Table 14.5 Function of region control circuit (2 of 2) MMPUACAn.ENABLE MMPUACAn.RP MMPUACAn.WP Access Region Output of group A region n Read Inside Permitted region Outside Outside of region Write Inside Permitted region Outside Outside of region Read...
Page 233 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function ENABLE Master Group Enable 0: Master group A disabled 1: Master group A enabled Operation After Detection 0: Non-maskable interrupt 1: Reset — These bits are read as 0. The write value should be 0. 15:8 KEY[7:0] Key Code...
Page 234: Operation
RA2L1 User's Manual 14. Memory Protection Unit (MPU) ● MMPUCTLA. When the PROTECT bit is set simultaneously, write 0xA5 to the KEY[7:0] bits using halfword access. KEY[7:0] bits (Key Code) The KEY[7:0] bits enable or disable writes to the PROTECT bit. When writing to the PROTECT bit simultaneously, write 0xA5 to the KEY[7:0] bits.
Page 235 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Read/write protected region Protected region (output of every single region unit is ”region where permission has not been set”) Region 0 R/W Read/write permitted region Region 1 read-only Read permitted/write protected region (write protection) Region 2 write-only Read/write protected region...
Page 236: Bus Slave Mpu
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Figure 14.8 shows the register setting flow for adding regions. During this register setting, stop all masters except the CPU. Start Clear MMPUPTA.PROTECT bit Write to MMPUSAn and MMPUEAn registers Write to MMPUACAn register Set MMPUPTA.PROTECT bit Figure 14.8 Register setting flow for region addition...
Page 237: Register Descriptions
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Table 14.7 Specifications of bus slave MPU (2 of 2) Specifications Description Internal peripheral bus 3: Connected to peripheral modules (CAC, ELC, I/O Ports, POEG, RTC, WDT, IWDT, IIC, CAN, ADC12, DOC, GPT, SCI, SPI, CRC,KINT, AGT, DAC12, ACMPLP, CTSU, and MSTP) Internal peripheral bus 7: Connected to peripheral modules (AES and TRNG)
Page 238 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function WPGRPA Master MPU Group A Write Protection 0: Memory protection write for master MPU group A disabled 1: Memory protection write for master MPU group A enabled 15:4 — These bits are read as 0. The write value should be 0. RPGRPA bit (Master MPU Group A Read Protection) The RPGRPA bit enables or disables memory protection for master MPU group A reads on memory bus 1.
Page 239 RA2L1 User's Manual 14. Memory Protection Unit (MPU) 14.5.1.3 SMPUP0BIU : Access Control Register for Internal Peripheral Bus 1 Base address: MPU = 0x4000_0000 Offset address: 0xC20 Bit position: WPGR RPGR WPCP RPCP Bit field: — — — — — —...
Page 240 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function RPGRPA Master MPU Group A Read Protection 0: Memory protection for master MPU group A read disabled 1: Memory protection for master MPU group A read enabled WPGRPA Master MPU Group A Write Protection 0: Memory protection for master MPU group A write disabled 1: Memory protection for master MPU group A write enabled 15:4...
Page 241 RA2L1 User's Manual 14. Memory Protection Unit (MPU) WPGRPA bit (Master MPU Group A Write Protection) The WPGRPA bit enables or disables memory protection for master MPU group A write on internal peripheral bus 7. 14.5.1.6 SMPUFBIU : Access Control Register for Internal Peripheral Bus 9 Base address: MPU = 0x4000_0000 Offset address: 0xC14 Bit position:...
Page 242: Functions
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function PROTECT Protection of Register 0: All bus slave register writes are permitted 1: All bus slave register writes are protected. Reads are permitted — These bits are read as 0. The write value should be 0. 15:8 KEY[7:0] Key Code...
Page 243: Security Mpu
RA2L1 User's Manual 14. Memory Protection Unit (MPU) 14.6 Security MPU The MCU incorporates a security MPU with four secure regions that include the code flash, SRAM, and two security functions. The secure regions can be protected from non-secure program accesses. A non-secure program cannot access a protected region.
Page 244 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Note 1. The address of these registers will be changed when the boot swap is set. Symbol Function 31:0 SECMPUPCS[31:0] Region Start Address Address where the region starts, for use in region determination. The value range is from 0x0000_0000 to 0x000F_FFFC or 0x1FF0_0000 to 0x200F_FFFC, excluding reserved areas.
Page 245 RA2L1 User's Manual 14. Memory Protection Unit (MPU) 14.6.1.4 SECMPUE0 : Security MPU Region 0 End Address Register Address: 0x0000_041C/0x0000_241C Bit position: 31 Bit field: — — — — — — — — SECMPUE[23:0] Value after reset: The value set by user Note 1.
Page 246 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function 31:0 SECMPUE[31:0] Region End Address Address where the region ends, for use in region determination. The value range is from 0x1FF0_0003 to 0x200F_FFFF, excluding reserved areas. The lower 2 bits are read as 1. When programming to the code flash, the lower 2 bits write value should be 1.
Page 247 RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function 31:0 SECMPUS[31:0] Region Start Address Address where the region starts, for use in region determination. The value range is from 0x400C_0000 to 0x400D_FFFC and 0x4010_0000 to 0x407F_FFFC. The lower 2 bits are read as 0. When programming to the code flash, the lower 2 bits write value should be 0.
Page 248: Memory Protection
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Symbol Function — These bits are read as 1. When programming to the code flash, the write value should be 1. R/W DISPC0 PC Region 0 Disable 0: Security MPU PC region 0 enabled 1: Security MPU PC region 0 disabled DISPC1 PC Region 1 Disable...
Page 249: Usage Notes
RA2L1 User's Manual 14. Memory Protection Unit (MPU) Code flash or SRAM region within the limits set up by SECMPUPCS0 and SECMPUPCE0. Code flash or SRAM region within the limits set up by SECMPUPCS1 and SECMPUPCE1. Non-secure program: All regions without the secure program. Secure data: Code flash region within the limits set up by SECMPUS0 and SECMPUE0.
Page 250 RA2L1 User's Manual 14. Memory Protection Unit (MPU) ® ® 2. ARM Cortex -M23 Processor Technical Reference Manual (ARM DDI 0550C) ® ® 3. ARM Cortex -M23 Processor User Guide (ARM DUI 0963B) R01UH0853EJ0100 Rev.1.00 Page 250 of 1117 Jul 31, 2020...
Page 251: Data Transfer Controller (Dtc)
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Data Transfer Controller (DTC) 15.1 Overview A Data Transfer Controller (DTC) module is provided for transferring data when activated by an interrupt request. Table 15.1 lists the DTC specifications and Figure 15.1 shows DTC block diagram.
Page 252: Register Descriptions
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Non-maskable interrupt request NVIC interrupt request Interrupt controller Register Vector number control Activation Activation request control DTC response Bus interface DTCCR Snooze control DTCVBR response signals control DTCST DTC_ DTCEND DTCSTS System Internal peripheral bus 1 DMA bus System bus...
Page 253: Mrb : Dtc Mode Register B
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Symbol Function — The read values are undefined. The write value should be 0. — SM[1:0] Transfer Source Address Addressing Mode — 0 0: Address in the SAR register is fixed (write-back to SAR is skipped.) 0 1: Address in the SAR register is fixed (write-back to SAR is skipped.) 1 0: SAR value is incremented after data transfer: +1 when SZ[1:0] = 00b...
Page 254: Sar : Dtc Transfer Source Register
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Symbol Function CHNS DTC Chain Transfer Select — 0: Chain transfer is continuous 1: Chain transfer occurs only when the transfer counter changes from 1 to 0 or 1 to CRAH CHNE DTC Chain Transfer Enable —...
Page 255: Dar : Dtc Transfer Destination Register
RA2L1 User's Manual 15. Data Transfer Controller (DTC) 15.2.4 DAR : DTC Transfer Destination Register Base address: DTCVBR Offset address: 0x08 + 0x4 × Vector number (Inaccessible directly from the CPU. See section 15.3.1. Allocating Transfer Information and DTC Vector Table) Bit position: 31 Bit field:...
Page 256: Crb : Dtc Transfer Count Register B
RA2L1 User's Manual 15. Data Transfer Controller (DTC) 15.2.6 CRB : DTC Transfer Count Register B Base address: DTCVBR Offset address: 0x0C + 0x4 × Vector number (Inaccessible directly from the CPU. See section 15.3.1. Allocating Transfer Information and DTC Vector Table) Bit position: Bit field:...
Page 257: Dtcst : Dtc Module Start Register
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Symbol Function 31:0 DTC Vector Base Address Set the DTC vector base address. The lower 10 bits should be 0. The DTCVBR sets the base address for calculating the DTC vector table address, which can be set in the range of 0x0000_0000 to 0xFFFF_FFFF (4 GB) in 1-KB units.
Page 258: Activation Sources
RA2L1 User's Manual 15. Data Transfer Controller (DTC) VECN[7:0] bits (DTC-Activating Vector Number Monitoring) While transfer by the DTC is in progress, the VECN[7:0] bits indicate the vector number associated with the activation source for the transfer. The value read from the VECN[7:0] bits is valid if the ACT flag is 1, indicating a DTC transfer in progress, and invalid if the ACT flag is 0, indicating no DTC transfer is in progress.
Page 259 RA2L1 User's Manual 15. Data Transfer Controller (DTC) Upper: DTCVBR DTC vector table Lower: Vector number × 4 Transfer information (1) DTC vector address Transfer information (1) start address Transfer information (2) start address Transfer information (2) +4(n - 1) Transfer information (n) start address 4 bytes...
Page 260: Operation
RA2L1 User's Manual 15. Data Transfer Controller (DTC) 15.4 Operation The DTC transfers data according to the transfer information. Storage of the transfer information in the SRAM area is required before a DTC operation. When the DTC is activated, it reads the DTC vector associated with the vector number. The DTC reads the transfer information from the transfer information store address referenced by the DTC vector and transfers the data.
Page 261 RA2L1 User's Manual 15. Data Transfer Controller (DTC) Start Match and DTCCR.RRS = 1 Compare vector numbers. Match? Mismatch or DTCCR.RRS = 0 Read DTC vector Next transfer Read transfer information Update transfer information start address MRB.CHNE = 1 MRB.CHNS = 0 MRA.MD[1:0] = 01b (repeat transfer mode) Last data transfer...
Page 262: Transfer Information Read Skip Function
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Table 15.3 Chain transfer conditions First transfer Second transfer CHNE CHNS DISEL CHNE CHNS DISEL *1 *2 *1 *2 Transfer counter Transfer counter DTC transfer — Other than (1 → 0) — —...
Page 263: Normal Transfer Mode
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Table 15.4 Transfer information write-back skip conditions and applicable registers MRA.SM[1:0] bits MRB.DM[1:0] bits SAR register DAR register Skip Skip Skip Write-back Write-back Skip Write-back Write-back 15.4.3 Normal Transfer Mode The normal transfer mode allows a 1-byte (8 bit), 1-halfword (16 bit), 1-word (32 bit) data transfer on a single activation source.
Page 264: Repeat Transfer Mode
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area Transfer 6 times Data 1 Data 1 (transfer 1 data unit per event) Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 5 Data 5 Data 6...
Page 265: Block Transfer Mode
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to repeat area) Transfer 8 times Data 1 Data 1 (transfer 1 data unit per event) Data 2 Data 2 Data 3 Data 3 Data 4 Data 4 Data 1...
Page 266: Chain Transfer
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to block area) First block Transfer Block area nth block Figure 15.7 Memory map of block transfer mode 15.4.6 Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single activation source. If the MRB.CHNE is set to 1 and CHNS to 0, an interrupt request to the CPU is not generated on completion of the specified number of rounds of transfer or by setting the MRB.DISEL bit to 1.
Page 267: Operation Timing
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Data area Transfer source data (1) Transfer information DTC vector table allocated in the SRAM Transfer destination data (1) DTC vector Transfer information address CHNE = 1 Transfer information start address Transfer information CHNE = 0 Transfer source data (2) Transfer destination data (2)
Page 268 RA2L1 User's Manual 15. Data Transfer Controller (DTC) System clock ICU.IELSRn.IR DTC activation request DTC access Vector read Transfer Data Transfer information read transfer information write Figure 15.9 Example 1 of DTC operation timing in normal transfer and repeat transfer modes System clock ICU.IELSRn.IR DTC activation request...
Page 269: Execution Cycles Of Dtc
RA2L1 User's Manual 15. Data Transfer Controller (DTC) System clock ICU.IELSRn.IR DTC activation request DTC access Data Transfer Data Transfer Transfer Transfer Vector read transfer transfer information read information information information write read write Figure 15.11 Example 3 of DTC operation timing for chain transfer System clock ICU.IELSRn.IR DTC activation request...
Page 270: Dtc Bus Mastership Release Timing
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Table 15.8 Execution cycles of DTC P: Block size (initial settings of CRAH and CRAL) Cv: Cycles for access to vector transfer information storage destination Ci: Cycles for access to transfer information storage destination address Cr: Cycles for access to data read destination Cw: Cycles for access to data write destination The unit is for system clocks (ICLK) + 1 in the Vector read, Transfer information read, and Data transfer read columns and 2 in the Internal...
Page 271: Examples Of Dtc Usage
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Table 15.9 DTC setting procedure (2 of 2) Step Name Description Set the DTCST.DTCST bit to 1 Set the DTC Module Start bit (DTCST.DTCST) to 1. Note: The DTCST.DTCST bit can be set even if the setting for each activation source is not completed. 15.6 Examples of DTC Usage 15.6.1...
Page 272 RA2L1 User's Manual 15. Data Transfer Controller (DTC) First transfer information setting Set up transfer to the GPT320.GTCCRC register. 1. In the MRA register, select incrementation of the source address (MRA.SM[1:0] = 10b). 2. Set the transfer to normal transfer mode (MRA.MD[1:0] = 00b) and word-sized transfer (MRA.SZ[1:0] = 10b). 3.
Page 273: Interrupt Handling
RA2L1 User's Manual 15. Data Transfer Controller (DTC) 2. Set the default PWM timer compare values in the GPT320.GTCCRA and GPT320.GTCCRB registers and the next PWM timer compare values in the GPT320.GTCCRC and GPT320.GTCCRE registers. 3. Set the default PWM timer period values in the GPT320.GTPR register and the next PWM timer period values in the GPT320.GTPBR register.
Page 274 RA2L1 User's Manual 15. Data Transfer Controller (DTC) (d) Set the MRB.DISEL bit = 0 (an interrupt request to the CPU is generated when the specified data transfer completes). (e) When setting the input buffer to 0x8000 to 0x83FF, also set the transfer counter to 2. 5.
Page 275: Interrupt
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Source(1) (Fixed) Input circuit Normal Transfer information allocated in (0x8000) Destination(1) the on-chip memory space Transfer (0x81FF) Input buffer (0x8200) (0x83FF) First data transfer Transfer Information (TI) Destination(3) upper 8bits of DAR Destination(2) CRA = 0x0200 Chain transfer...
Page 276: Usage Notes
RA2L1 User's Manual 15. Data Transfer Controller (DTC) Module-stop function Writing 1 to the MSTPCRA.MSTPA22 bit enables the module-stop function of the DTC. If the DTC transfer is in progress at the time, 1 is written to the MSTPCRA.MSTPA22 bit. The transition to the module-stop state proceeds after DTC transfer ends.
Page 277: Event Link Controller (Elc)
RA2L1 User's Manual 16. Event Link Controller (ELC) Event Link Controller (ELC) 16.1 Overview The Event Link Controller (ELC) uses the event requests generated by various peripheral modules as source signals to connect them to different modules, allowing direct link between the modules without CPU intervention. Table 16.1 lists the ELC specifications, and Figure 16.1...
Page 278: Register Descriptions
RA2L1 User's Manual 16. Event Link Controller (ELC) 16.2 Register Descriptions 16.2.1 ELCR : Event Link Controller Register Base address: ELC = 0x4004_1000 Offset address: 0x00 Bit position: ELCO Bit field: — — — — — — — Value after reset: Symbol Function —...
Page 279: Elsrn : Event Link Setting Register N (N = 0 To 3, 8, 9, 12, 14, 15, 18)
RA2L1 User's Manual 16. Event Link Controller (ELC) ● If 0 is written to this bit while the WI bit is 0, this bit becomes 0. WI bit (ELSEGR Register Write Disable) The ELSEGR register can only be written to when the write value to the WI bit is 0. This bit is read as 1. Before setting the WE or SEG bit, the WI bit must be set to 0.
Page 280: Event Link Controller (Elc)
RA2L1 User's Manual 16. Event Link Controller (ELC) Table 16.3 Association between event signal names set in ELSRn.ELS[7:0] bits and signal numbers (1 of 4) Event number Interrupt request source Name Description 0x01 Port External pin interrupt 0 PORT_IRQ0 0x02 External pin interrupt 1 PORT_IRQ1 0x03...
Page 281 RA2L1 User's Manual 16. Event Link Controller (ELC) Table 16.3 Association between event signal names set in ELSRn.ELS[7:0] bits and signal numbers (2 of 4) Event number Interrupt request source Name Description 0x46 GPT320 GPT0_CCMPA Compare match A 0x47 GPT0_CCMPB Compare match B 0x48 GPT0_CMPC...
Page 282 RA2L1 User's Manual 16. Event Link Controller (ELC) Table 16.3 Association between event signal names set in ELSRn.ELS[7:0] bits and signal numbers (3 of 4) Event number Interrupt request source Name Description 0x6A GPT166 GPT6_CCMPA Compare match A 0x6B GPT6_CCMPB Compare match B 0x6C GPT6_CMPC...
Page 283: Operation
RA2L1 User's Manual 16. Event Link Controller (ELC) Table 16.3 Association between event signal names set in ELSRn.ELS[7:0] bits and signal numbers (4 of 4) Event number Interrupt request source Name Description 0x93 SCI3 SCI3_RXI Receive data full 0x94 SCI3_TXI Transmit data empty 0x95 SCI3_TEI...
Page 284: Example Of Procedure For Linking Events
RA2L1 User's Manual 16. Event Link Controller (ELC) Table 16.4 Module operations when event occurs Module Operations When Event is Input ● Start counting ● Stop counting ● Clear counting ● Up counting ● Down counting ● Input capture DAC12 Start D/A conversion CTSU Start measurement operation...
Page 285 RA2L1 User's Manual 16. Event Link Controller (ELC) Delay time Event source Event destination Module A Module B Clock = clock_A Clock = clock_B Figure 16.2 ELC delay time Table 16.5 ELC delay time Clock domain Clock frequency ELC delay time clock_A = clock_B clock_A = clock_B 0 cycle...
Page 286: I/O Ports
RA2L1 User's Manual 17. I/O Ports I/O Ports 17.1 Overview The I/O port pins operate as general I/O port pins, I/O pins for peripheral modules, interrupt input pins, analog I/O, port group function for the ELC. All pins operate as input pins immediately after a reset, and pin functions are switched by register settings. The I/O ports and peripheral modules for each pin are specified in the associated registers.
Page 287 RA2L1 User's Manual 17. I/O Ports Table 17.1 I/O port specifications (2 of 2) Package Package Package Package Numb Numb Numb Numb er of er of er of er of Port 100 pins pins 80 pins pins 64 pins pins 48 pins pins Port 2...
Page 288: Register Descriptions
RA2L1 User's Manual 17. I/O Ports Table 17.2 I/O port functions (2 of 2) Input mode Port Port name Input pull-up switching Open drain output 5V tolerant Port 7 P708, P714 — — Input / ✓ ✓ Output Port 8 P808, P809 —...
Page 289: Pcntr2/Eidr/Pidr : Port Control Register 2
RA2L1 User's Manual 17. I/O Ports 17.2.2 PCNTR2/EIDR/PIDR : Port Control Register 2 Base address: PORTm = 0x4004_0000 + 0x0020 × m (m = 0 to 8) Offset address: 0x004 (PCNTR2/EIDR) 0x006 (PIDR) Bit position: EIDR1 EIDR1 EIDR1 EIDR1 EIDR1 EIDR1 EIDR0 EIDR0...
Page 290: Pcntr3/Porr/Posr : Port Control Register 3
RA2L1 User's Manual 17. I/O Ports 17.2.3 PCNTR3/PORR/POSR : Port Control Register 3 Base address: PORTm = 0x4004_0000 + 0x0020 × m (m = 0 to 8) Offset address: 0x008 (PCNTR3/PORR) 0x00A (POSR) Bit position: PORR PORR PORR PORR PORR PORR PORR PORR...
Page 291: Pcntr4/Eorr/Eosr : Port Control Register 4
RA2L1 User's Manual 17. I/O Ports 17.2.4 PCNTR4/EORR/EOSR : Port Control Register 4 Base address: PORTm = 0x4004_0000 + 0x0020 × m (m = 1, 2) Offset address: 0x00C (PCNTR4/EORR) 0x00E (EOSR) Bit position: EORR EORR EORR EORR EORR EORR EORR EORR EORR...
Page 292: Pmnpfs/Pmnpfs_Ha/Pmnpfs_By : Port Mn Pin Function Select Register (M = 0 To 8, N = 00 To 15)
RA2L1 User's Manual 17. I/O Ports 17.2.5 PmnPFS/PmnPFS_HA/PmnPFS_BY : Port mn Pin Function Select Register (m = 0 to 8, n = 00 to 15) Base address: PFS = 0x4004_0800 Offset address: 0x000 + 0x040 × m + 0x004 × n (PmnPFS) 0x002 + 0x040 ×...
Page 293 RA2L1 User's Manual 17. I/O Ports Note: Be sure to set registers and bits that are not mounted in a product to their initial values. Note 1. The initial value of P108, P201, and P300 is not 0x00000000. The initial value of P108 is 0x00010010, P201 is 0x00000010, and P300 is 0x00010010.
Page 294: Pwpr : Write-Protect Register
RA2L1 User's Manual 17. I/O Ports 17.2.6 PWPR : Write-Protect Register Base address: PFS = 0x4004_0800 Offset address: 0x503 Bit position: PFSW Bit field: B0WI — — — — — — Value after reset: Symbol Function — These bits are read as 0. The write value should be 0. PFSWE PmnPFS Register Write Enable 0: Writing to the PmnPFS register is disabled...
Page 295: Port Function Select
RA2L1 User's Manual 17. I/O Ports ● Port Direction bit (PDRn), which selects input or output direction ● Port Output Data bit (PODRn), which holds data for output ● Port Input Data bit (PIDRn), which indicates the pin states ● Event Input Data bit (EIDRn), which indicates the pin state when an ELC_PORTn (n = 1 or 2) signal occurs ●...
Page 296 RA2L1 User's Manual 17. I/O Ports ELC_PORTn EIDR Note: n = 1 or 2 Figure 17.2 Event ports input data Output from PODR by EOSR and EORR When an ELC_PORTn (n = 1 or 2) signal occurs, the data is output from the PODR to the external pin based on the settings in the EOSR and EORR registers.
Page 297: Wait Function For Port Read
RA2L1 User's Manual 17. I/O Ports Event pulse Edge detect From other PADs Figure 17.4 Generation of event pulse 17.3.4 Wait Function for Port Read Wait cycles for reading the port input data can be set in the PRWCNTR.WAIT[1:0] bits as follows: ●...
Page 298: Usage Notes
RA2L1 User's Manual 17. I/O Ports Table 17.4 Handling of unused pins (2 of 2) Pin name Description P213/XTAL When the main clock oscillator is not used, set the MOSCCR.MOSTP bit to 1 (general port P213). When this pin is not used as port P213, it is configured in the same way as ports 0 to 8. When the external clock is input to the EXTAL pin, leave this pin open.
Page 299: Notes On Using Analog Functions
RA2L1 User's Manual 17. I/O Ports 3. Outputs 0 if PCNTR3.PORR is set to 1. 4. Outputs 1 if PCNTR3.POSR is set to 1. 5. Outputs 0 or 1 because PCNTR1.PODRn is set. 6. Outputs 0 or 1 because PmnPFS.PODRn is set. Numbers in this list correspond to the priority for writing to the PODRn.
Page 300 RA2L1 User's Manual 17. I/O Ports Table 17.6 Register settings for input/output pin function (PORT1) (2 of 2) PSEL[4:0] settings Function P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 00110b MISOA MOSIA RSPCK SSLA0 SSLA1...
Page 301 RA2L1 User's Manual 17. I/O Ports Table 17.7 Register settings for input/output pin function (PORT2) (2 of 2) PSEL[4:0] settings Function P200 P201 P202 P203 P204 P205 P206 P207 P208 P212 P213 P214 P215 48-pin product ✓ ✓ — — —...
Page 302 RA2L1 User's Manual 17. I/O Ports Table 17.9 Register settings for input/output pin function (PORT4) (2 of 2) PSEL[4:0] settings Function P400 P401 P402 P403 P404 P405 P406 P407 P408 P409 P410 P411 P412 P413 P414 P415 01010b CAC/ CACRE —...
Page 303 RA2L1 User's Manual 17. I/O Ports Table 17.12 Register settings for input/output pin function (PORT7) PSEL[4:0] settings Function P708 P714 00000b (initial) Hi-Z 00101b RXD1_D/MISO1_D/SCL1_D — 00110b SSLA3_B — NCODR bit ✓ ✓ PCR bit ✓ ✓ 100-pin product ✓ ✓...
Page 304: Key Interrupt Function (Kint)
RA2L1 User's Manual 18. Key Interrupt Function (KINT) Key Interrupt Function (KINT) 18.1 Overview The key interrupt function (KINT) is generated a key interrupt by detecting a valid edge on the key interrupt input pin. Figure 18.1 shows a block diagram and Table 18.1 lists the input pins.
Page 305: Krf : Key Return Flag Register
RA2L1 User's Manual 18. Key Interrupt Function (KINT) 18.2.2 KRF : Key Return Flag Register Base address: KINT = 0x4008_0000 Offset address: 0x04 Bit position: Bit field: KIF7 KIF6 KIF5 KIF4 KIF3 KIF2 KIF1 KIF0 Value after reset: Symbol Function KIF0 to KIF7 Key Interrupt Flag n 0: No interrupt detected...
Page 306: Operation When Using The Key Interrupt Flags (Krctl.krmd = 1)
RA2L1 User's Manual 18. Key Interrupt Function (KINT) KR0n pin KEY_INTKR Key interrupt When KRCTL.KRMD = 0 and KRCTL.KREG = 0 Note: n = 00 to 07 Figure 18.2 Operation of KEY_INTKR signal when a key interrupt is input to a single channel Figure 18.3 shows the operation when a valid edge is input to multiple KR0n pins.
Page 307 RA2L1 User's Manual 18. Key Interrupt Function (KINT) (a) When KRF.KIF0 flag is cleared after a rising edge is input to the KR00 pin KR00 pin KRF.KIF0 Cleared by software KEY_INTKR Key interrupt (b) When KRF.KIF0 flag is cleared before a rising edge is input to the KR00 pin KR00 pin KRF.KIF0 Cleared by...
Page 308: Usage Notes
RA2L1 User's Manual 18. Key Interrupt Function (KINT) KR00 pin KR01 pin KR05 pin KRF.KIF0 Cleared by software KRF.KIF1 Cleared by software KRF.KIF5 Cleared by software KEY_INTKR Key interrupt Key interrupt Key interrupt When KRCTL.KRMD = 1 and KRCTL.KREG = 0 Figure 18.5 Operation of KEY_INTKR signal when key interrupts are input to multiple channels 18.4...
Page 309: Port Output Enable For Gpt (Poeg)
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) Port Output Enable for GPT (POEG) 19.1 Overview The Port Output Enable (POEG) function can place the General PWM Timer (GPT) output pins in the output disable state in one of the following ways: ●...
Page 310: Register Descriptions
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) Group B POEG Group A IOCE GPT Ch 0 GTINTAD.GRPABL Group A Ch 0 GTINTAD.GRPABH Group B Ch 9 IOCF Ch 1 Ch 9 POEG_GROUP0 POEG_GROUP1 OPSCR. GTOUUP GRP[1:0] GTOULO GTOVUP OPSCR.
Page 311: Output-Disable Control Operation
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) Symbol Function PIDF Port Input Detection Flag 0: No output-disable request from the GTETRGn pin occurred 1: Output-disable request from the GTETRGn pin occurred. IOCF Detection Flag for GPT Output-Disable Request 0: No output-disable request from GPT occurred.
Page 312: Pin Input Level Detection Operation
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) ● Oscillation stop detection for the clock generation circuit While POEGGn.OSTPE is 1, the halt status of the main clock oscillator is detected and the POEGGn. OSTPF flag is set to 1.
Page 313: Release From Output-Disable
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) 19.3.5 Release from Output-Disable To release the GPT output pins placed in the output-disable state, either return them to their initial state with a reset or clear all of the following flags: ●...
Page 314: External Trigger Output To The Gpt
RA2L1 User's Manual 19. Port Output Enable for GPT (POEG) Table 19.3 Interrupt sources and conditions (2 of 2) Interrupt source Symbol Associated flag Trigger conditions POEG group B interrupt POEG_GROUPB POEGGB.IOCF An output-disable request from a GPT disable request occurred POEGGB.PIDF An output-disable request from the GTETRGB pin occurred 19.5...
Page 315: General Pwm Timer (Gpt)
RA2L1 User's Manual 20. General PWM Timer (GPT) General PWM Timer (GPT) 20.1 Overview The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 4 channels and a 16-bit timer with GPT16 × 6 channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In addition, PWM waveforms can be generated for controlling brushless DC motors.
Page 316 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.2 GPT functions (2 of 2) Parameter Description Counter clear sources GTPR register compare match, input capture, input pin status, ELC event input, and GTETRGn (n = A, B) pin input Compare match output Low output Available...
Page 317 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320 Control registers Interrupt request signals GPT321 GPT0_CCMPA GTWP GTICASR GTDTCR … GPT0_CCMPB GTSTR GTICBSR GTDVU Clock source GPT0_CMPC GTSTP GTCR … PCLKD CPT0_CMPD GTCLR GTUDDTYC PCLKD/4 Cycle setting/ … GPT0_UDF GTSSR GTIOR PCLKD/16 Cycle setting buffer registers...
Page 318: Register Descriptions
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.3 GPT I/O pins (2 of 2) Channel Pin name Function GPT16m GTIOCmA GTCCRA register input capture input/output compare output/PWM output pin GTIOCmB GTCCRB register input capture input/output compare output/PWM output pin GPT_OPS GTIU Input...
Page 319: Gtstr : General Pwm Timer Software Start Register
RA2L1 User's Manual 20. General PWM Timer (GPT) PRKEY[7:0] bit (GTWP Key Code) This bit controls whether the WP bit can be overwritten. 20.2.2 GTSTR : General PWM Timer Software Start Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 ×...
Page 320: Gtclr : General Pwm Timer Software Clear Register
RA2L1 User's Manual 20. General PWM Timer (GPT) CSTOPn bits (Channel n GTCNT Count Stop (n = 0 to 9)) The CSTOPn bits stop channel n of the GTCNT counter operation. Writing to the GTSTP.CSTOPn bit (n = 0 to 9) has no effect unless the GTPSR.CSTOPn bit is set to 1.
Page 321 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function SSGTRGBR GTETRGB Pin Rising Input Source Counter Start Enable 0: Counter start disabled on the rising edge of GTETRGB input 1: Counter start enabled on the rising edge of GTETRGB input SSGTRGBF GTETRGB Pin Falling Input Source Counter Start Enable 0: Counter start disabled on the falling edge of GTETRGB input...
Page 322 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function SSELCD ELC_GPTD Event Source Counter Start Enable 0: Counter start disabled at the ELC_GPTD input 1: Counter start enabled at the ELC_GPTD input 30:20 — These bits are read as 0. The write value should be 0. CSTRT Software Source Counter Start Enable 0: Counter start disabled by the GTSTR register...
Page 323: Gtpsr : General Pwm Timer Stop Source Select Register
RA2L1 User's Manual 20. General PWM Timer (GPT) SSELCm bit (ELC_GPTm Event Source Counter Start Enable) (m = A to D) The SSELCm bit enables or disables the GTCNT counter start at the ELC_GPTm event input. CSTRT bit (Software Source Counter Start Enable) The CSTRT bit enables or disables the GTCNT counter start by GTSTR register.
Page 324 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function PSCBRAL GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable 0: Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 1: Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0 PSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable...
Page 325: Gtcsr : General Pwm Timer Clear Source Select Register
RA2L1 User's Manual 20. General PWM Timer (GPT) PSCARBH bit (GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable) This bit enables or disables the GTCNT counter stop on the rising edge of the GTIOCnA pin input, when GTIOCnB input is PSCAFBL bit (GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable) The PSCAFBL bit enables or disables the GTCNT counter stop on the falling edge of the GTIOCnA pin input, when GTIOCnB input is 0.
Page 326 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function CSGTRGAF GTETRGA Pin Falling Input Source Counter Clear Enable 0: Counter clear disabled on the falling edge of GTETRGA input 1: Counter clear enabled on the falling edge of GTETRGA input CSGTRGBR GTETRGB Pin Rising Input Source Counter Clear Enable 0: Disable counter clear on the rising edge of GTETRGB input...
Page 327 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function CSELCC ELC_GPTC Event Source Counter Clear Enable 0: Counter clear disabled at the ELC_GPTC input 1: Counter clear enabled at the ELC_GPTC input CSELCD ELC_GPTD Event Source Counter Clear Enable 0: Counter clear disabled at the ELC_GPTD input 1: Counter clear enabled at the ELC_GPTD input 30:20...
Page 328: Gtupsr : General Pwm Timer Up Count Source Select Register
RA2L1 User's Manual 20. General PWM Timer (GPT) CSCBFAH bit (GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable) The CSCBFAH bit enables or disables the GTCNT counter clear on the falling edge of the GTIOCnB pin input, when GTIOCnA input is 1.
Page 329 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function USCAFBH GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable 0: Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 1: Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1 USCBRAL...
Page 330: Gtdnsr : General Pwm Timer Down Count Source Select Register
RA2L1 User's Manual 20. General PWM Timer (GPT) USCARBL bit (GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable) The USCARBL bit enables or disables GTCNT counter count up on the rising edge of GTIOCnA pin input, when GTIOCnB input is 0.
Page 331 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function DSGTRGAF GTETRGA Pin Falling Input Source Counter Count Down Enable 0: Counter count down disabled on the falling edge of GTETRGA input 1: Counter count down enabled on the falling edge of GTETRGA input DSGTRGBR GTETRGB Pin Rising Input Source Counter Count Down Enable 0: Counter count down disabled on the rising edge of GTETRGB input...
Page 332 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function DSELCA ELC_GPTA Event Source Counter Count Down Enable 0: Counter count down disabled at the ELC_GPTA input 1: Counter count down enabled at the ELC_GPTA input DSELCB ELC_GPTB Event Source Counter Count Down Enable 0: Counter count down disabled at the ELC_GPTB input 1: Counter count down enabled at the ELC_GPTB input DSELCC...
Page 333: Gticasr : General Pwm Timer Input Capture Source Select Register A
RA2L1 User's Manual 20. General PWM Timer (GPT) DSCBRAH bit (GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable) The DSCBRAH bit enables or disables the GTCNT counter count down on the rising edge of GTIOCnB pin input, when GTIOCnA input is 1.
Page 334 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function ASCARBH GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable 0: GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 1: GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1 ASCAFBL...
Page 335: Gticbsr : General Pwm Timer Input Capture Source Select Register B
RA2L1 User's Manual 20. General PWM Timer (GPT) ASGTRGAF bit (GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable) The ASGTRGAF bit enables or disables the input capture for GTCCRA on the falling edge of the GTETRGA pin input. ASGTRGBR bit (GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable) The ASGTRGBR bit enables or disables the input capture for GTCCRA on the rising edge of the GTETRGB pin input.
Page 336 RA2L1 User's Manual 20. General PWM Timer (GPT) Offset address: 0x28 Bit position: BSEL BSEL BSEL BSEL Bit field: — — — — — — — — — — — — Value after reset: Bit position: BSCB BSCB BSCB BSCB BSCA BSCA BSCA...
Page 337 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function BSCBRAH GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable 0: GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 1: GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1 BSCBFAL...
Page 338: Gtcr : General Pwm Timer Control Register
RA2L1 User's Manual 20. General PWM Timer (GPT) BSCAFBL bit (GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable) The BSCAFBL bit enables or disables the input capture for GTCCRB on the falling edge of the GTIOCnA pin input, whenGTIOCnB input is 0.
Page 339 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function 18:16 MD[2:0] Mode Select 0 0 0: Saw-wave PWM mode (single buffer or double buffer possible) 0 0 1: Saw-wave one-shot pulse mode (fixed buffer operation) 0 1 0: Setting prohibited 0 1 1: Setting prohibited 1 0 0: Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)
Page 340: Gtuddtyc : General Pwm Timer Count Direction And Duty Setting Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.13 GTUDDTYC : General PWM Timer Count Direction and Duty Setting Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x30 Bit position: OBDT...
Page 341 RA2L1 User's Manual 20. General PWM Timer (GPT) When the UD value is set to 0 during up-counting, the count direction changes at an overflow (the timing synchronous with count clock after the GTCNT value becomes the GTPR value). When the UD value is set to 1 during down- counting, the count direction changes at an underflow (the timing synchronous with count clock after the GTCNT value becomes 0).
Page 342: Gtior : General Pwm Timer I/O Control Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.14 GTIOR : General PWM Timer I/O Control Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x34 Bit position: NFBE...
Page 343 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function 26:25 OBDF[1:0] GTIOCnB Pin Disable Value Setting 0 0: Output disable is prohibited 0 1: GTIOCnB pin is set to Hi-Z on output disable 1 0: GTIOCnB pin is set to 0 on output disable 1 1: GTIOCnB pin is set to 1 on output disable 28:27 —...
Page 344 RA2L1 User's Manual 20. General PWM Timer (GPT) OBDFLT bit (GTIOCnB Pin Output Value Setting at the Count Stop) The OBDFLT bit sets whether the GTIOCnB pin outputs high or low when counting stops. OBHLD bit (GTIOCnB Pin Output Setting at the Start/Stop Count) The OBHLD bit specifies whether theGTIOCnB pin output level is retained or the level at the start or stop of counting depends on the register setting.
Page 345 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.4 Settings of GTIOA[4:0] and GTIOB[4:0] bits GTIOA/GTIOB[4:0] bits Function *1 *2 *3 b3, b2 b1, b0 Initial output is Output retained at Output retained at GTCCRA/GTCCRB compare match cycle end Low output at GTCCRA/GTCCRB compare match High output at GTCCRA/GTCCRB compare match Output toggled at GTCCRA/GTCCRB compare match...
Page 346: Gtintad : General Pwm Timer Interrupt Output Setting Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.15 GTINTAD : General PWM Timer Interrupt Output Setting Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x38 Bit position: GRPA...
Page 347: Gtst : General Pwm Timer Status Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.16 GTST : General PWM Timer Status Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x3C Bit position: OABL...
Page 348 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function — This bit is read as 0. The write value should be 0. Note 1. Only 0 can be written to this bit. Do not write 1. The GTST indicates the status of the GPT. TCFA flag (Input Capture/Compare Match Flag A) The TCFA flag indicates the status for the input capture or compare match of GTCCRA.
Page 349 RA2L1 User's Manual 20. General PWM Timer (GPT) ● GTBER.CCRA[1:0] = 10b, 11b (GTCCRD performs buffer operation). TCFE flag (Input Compare Match Flag E) The TCFE flag indicates the status for the compare match of GTCCRE. [Setting condition] ● GTCNT = GTCCRE. [Clearing condition] ●...
Page 350 RA2L1 User's Manual 20. General PWM Timer (GPT) TUCF flag (Count Direction Flag) The TUCF flag indicates the count direction of GTCNT. In event count operation, this flag is set to 1 in up-counting and to 0 in down-counting. ODF flag (Output Disable Flag) The ODF flag shows the request of the output disable source group that is selected in the GRP[1:0] bits.
Page 351: Gtber : General Pwm Timer Buffer Enable Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.17 GTBER : General PWM Timer Buffer Enable Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x40 Bit position: CCRS...
Page 352: Gtcnt : General Pwm Timer Counter
RA2L1 User's Manual 20. General PWM Timer (GPT) CCRB[1:0] bits (GTCCRB Buffer Operation) The CCRB[1:0] bits set the buffer operation using GTCCRB, GTCCRE, and GTCCRF combined. When the buffer operation is restricted by the operating mode set in GTCR, the GTCR setting is given priority. The buffer operation mode is fixed in saw-wave one-shot pulse mode or triangle-wave PWM mode 3 (64-bit transfer at trough).
Page 353: Gtpr : General Pwm Timer Cycle Setting Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.20 GTPR : General PWM Timer Cycle Setting Register Base address: GPT32n = 0x4007_8000 + 0x0100 × n (n = 0 to 3) GPT16m = 0x4007_8000 + 0x0100 × m (m = 4 to 9) Offset address: 0x64 Bit position: 31 Bit field:...
Page 354: Gtdvu : General Pwm Timer Dead Time Value Register U
RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function Negative-Phase Waveform Setting 0: GTCCRB is set without using GTDVU 1: GTDVU sets the compare match value for negative-phase waveform with automatic dead time in GTCCRB 31:1 — These bits are read as 0. The write value should be 0. GTDTCR enables automatic setting of a compare match value for negative-phase waveform with dead time.
Page 355: Opscr : Output Phase Switching Control Register
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.2.24 OPSCR : Output Phase Switching Control Register Base address: GPT_OPS = 0x4007_8FF0 Offset address: 0x00 Bit position: Bit field: NFCS[1:0] NFEN — — GODF GRP[1:0] — — ALIGN Value after reset: Bit position: Bit field: —...
Page 356 RA2L1 User's Manual 20. General PWM Timer (GPT) Symbol Function 23:22 — These bits are read as 0. The write value should be 0. 25:24 GRP[1:0] Output Disabled Source Selection 0 0: Select group A output disable source 0 1: Select group B output disable source Others: Setting prohibited GODF Group Output Disable Function...
Page 357: Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) RV bit (Output Phase Rotation Direction Reversal Control) The RV bit reverses the direction of rotation of the motor by inverting the input phase. ALIGN bit (Input Phase Alignment) The ALIGN bit selects the PCLKD or PWM for the sampling of the input phase (input phase is specified in the OPSCR.FB bit).
Page 358 RA2L1 User's Manual 20. General PWM Timer (GPT) Periodic count operation in up-counting by count clock The GTCNT counter in each channel starts up-counting when the associated GTCR.CST bit is set to 1 with GTUPSR and GTDNSR registers set to 0x00000000. When the GTCNT value changes from the GTPR value to 0 (overflow), the GTST.TCFPO flag is set to 1.
Page 359 RA2L1 User's Manual 20. General PWM Timer (GPT) GTCNT counter value GTCNT counter is written by software. GTPR register 0x00000000 Time Flag is cleared by software GTCR.CST bit GTST.TCFPU flag Figure 20.4 Example of periodic count operation in down-counting by the count clock Table 20.6 shows an example for setting periodic count operation in down-counting by the count clock.
Page 360 RA2L1 User's Manual 20. General PWM Timer (GPT) GTETRGA pin Bus clock GTETRGA (internal signal) Core clock GTCNT N + 1 Note: Bus clock: PCLKB, Core clock: PCLKD Note 1. The GTETRGA internal signal reflects the signal being input to the GPTW when the digital noise filter for the GTETRGA pin in the POEG is not in use.
Page 361: Counter Clear Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) GTETRGA pin Bus clock GTETRGA (internal signal) Core clock GTCNT N + 1 Note: Bus clock: PCLKB, Core clock: PCLKD Note 1. The GTETRGA internal signal reflects the signal being input to the GPTW when the digital noise filter for the GTETRGA pin in the POEG is not in use.
Page 362 RA2L1 User's Manual 20. General PWM Timer (GPT) 20.3.1.2 Waveform output by compare match Compare match means that the GTCNT counter value matches the value of GTCCRA or GTCCRB. When a compare match occurs, the compare match flag is generated synchronously with the count clock, including the event count. At the same time, the GPT can output low, high, or toggled output from the associated GTIOCnA or GTIOCnB output pin (n = 0 to 9).
Page 363 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.9 Example for setting low output and high output operation (2 of 2) Step Name Description Set GTIOCnm pin function Set the GTIOCnm pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR. In Figure Figure 20.7, GTIOA[4:0] = 00010b, GTIOB[4:0] = 10001b.
Page 364: Input Capture Function
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register 0x00000000 Time GTIOC0A pin output GTIOC0B pin output [Setting examples] GPT320.GTIOR.GTIOA[4:0] bits: Initial output is high, output toggled at compare match, output retained at cycle end GPT320.GTIOR.GTIOB[4:0] bits: Initial output is low, output retained at compare match, output toggled at cycle end Figure 20.9 Example of toggled output operation (2)
Page 365: Buffer Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0xE400 0xC154 0x9682 0x1100 0x00000000 Time GTIOC0A pin input GTIOC0B pin input GPT320.GTCCRA register 0x9682 0x1100 0xE400 0xC154 GPT320.GTCCRB register [Setting examples] GTICASR setting input capture at both edges GTICBSR setting input capture at the rising edge Figure 20.10 Example of input capture operation...
Page 366 RA2L1 User's Manual 20. General PWM Timer (GPT) In saw-wave mode or in event count, the buffer transfer is performed when the following counter clear operations occur during counting: ● Clear by hardware sources (the clear source is selected in CTCSR register) ●...
Page 367 RA2L1 User's Manual 20. General PWM Timer (GPT) GTCNT counter value cccc bbbb aaaa 0x00000000 Time Register write Register write Register write GTPBR register aaaa bbbb cccc Buffer transfer at trough Buffer transfer at trough Buffer transfer at trough GTPR register aaaa bbbb cccc...
Page 368 RA2L1 User's Manual 20. General PWM Timer (GPT) In saw-wave mode or in event count operation, during counting, buffer transfer (which is the same as an overflow during up-counting or an underflow during down-counting) is performed by the counter clear sources similar to the case shown in section 20.3.2.1.
Page 369 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0x00000000 Time Register write Register write Register write cccc GPT320.GTCCRD register Buffer transfer at Buffer transfer at trough trough GPT320.GTCCRC register bbbb cccc Buffer transfer at Buffer transfer at trough trough...
Page 370 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.13 Example for setting GTCCRA and GTCCRB buffer operation for output compare Step Name Description Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 20.14, 000b (saw-wave PWM mode) is set, in Figure 20.15, 100b (triangle-wave PWM mode 1) is set, and in...
Page 371 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0x00000000 Time GTIOC0A pin input aaaa bbbb cccc GPT320.GTCCRA register Buffer transfer at input Buffer transfer at input Buffer transfer at capture capture input capture aaaa bbbb GPT320.GTCCRC register...
Page 372: Pwm Output Operating Mode
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.14 Example for setting GTCCRA and GTCCRB buffer operation for input capture (2 of 2) Step Name Description Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 20.17, after 11b is set in GTUDDTYC[1:0], 01b is set in GTUDDTYC[1:0] (up-counting).
Page 373 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register ffff eeee dddd cccc bbbb aaaa 0x00000000 Time Register write Register write Register write Register write GPT320.GTCCRC register cccc eeee Buffer transfer Buffer transfer Buffer transfer at overflow at overflow at overflow GPT320.GTCCRA register...
Page 374 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.15 Example for setting saw-wave PWM mode (2 of 2) Step Name Description Set buffer value for each cycle For buffer operation, set the GTIOCnA pin and GTIOCnB pin transitions in 1 cycle after the current cycle in GTCCRC and GTCCRE, respectively.
Page 375 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0x00000000 Time Register write Register write Register write GPT320.GTCCRD register eeee Buffer transfer Buffer transfer at overflow at overflow Temporary register A gggg eeee...
Page 376 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.16 Example setting for saw-wave one-shot pulse mode (2 of 2) Step Name Description Select count clock Select the count clock with GTCR.TPCS[2:0]. Set cycle Set the cycle in GTPR. Set initial value for counter Set the initial value in the GTCNT counter.
Page 377 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register ffff eeee dddd cccc bbbb aaaa 0x00000000 Time Register write Register write Register write GPT320.GTCCRC register dddd ffff Buffer transfer at Buffer transfer at trough trough GPT320.GTCCRA register bbbb dddd ffff...
Page 378 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.17 Example setting for triangle-wave PWM mode 1 (2 of 2) Step Name Description Set buffer value for each cycle For buffer operation, set the GTIOCnA pin and GTIOCnB pin transitions in 1 cycle after the current cycle in GTCCRC and GTCCRE, respectively.
Page 379 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.18 Example for setting triangle-wave PWM mode 2 Step Name Description Set operating mode Set the operating mode with GTCR.MD[2:0]. Figure 20.22, 101b (triangle-wave PWM mode 2) is set. Select count clock Select the count clock with GTCR.TPCS[2:0].
Page 380 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register hhhh gggg ffff eeee dddd cccc bbbb aaaa 0x00000000 Time Register write Register write GPT320.GTCCRD register hhhh Buffer transfer at trough Temporary register A ffff hhhh Register write Register write GPT320.GTCCRC register dddd...
Page 381: Automatic Dead Time Setting Function
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.19 Example setting for triangle-wave PWM mode 3 (2 of 2) Step Name Description Set GTIOCnm pin function Set the GTIOCnm pin function with GTIOA[4:0] and GTIOB[4:0] in GTIOR. Figure 20.23, GTIOA[4:0] = 00011b and GTIOB[4:0] = 10011b. Enable GTIOCnm pin output Set to enable the GTIOCnm pin output with OAE and OBE in GTIOR.
Page 382 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register 0x00000000 Time Buffer transfer Buffer transfer Buffer transfer Buffer transfer at overflow at compare match at overflow at compare match GPT320.GTCCRA register GPT320.GTCCRB register GTCCRA GTCCRA - GTDVU GTCCRA + GTDVU GTCCRA + GTDVU...
Page 383 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register Time 0x00000000 Buffer transfer at trough Buffer transfer at trough GPT320.GTCCRA register GPT320.GTCCRB register GTCCRA - GTDVU GTCCRA - GTDVU (Automatic setting) GTIOC0A pin output GTDVU GTDVU GTDVU...
Page 384 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.21 Example setting for automatic dead time setting function in saw-wave one-shot pulse mode, and triangle-wave PWM mode 3 (2 of 2) Step Name Description Set count direction Select the count direction (up or down) with the GTUDDTYC register. Figure 20.24, 01b is set after 11b is set in GTUDDTYC[1:0] (up count).
Page 385: Count Direction Changing Function
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.22 Example setting for automatic dead time setting function in triangle-wave PWM mode 1 or 2 (2 of 2) Step Name Description Set buffer value for each cycle When the compare match register is used for buffer operation, set the GTIOCnA pin transition in 1 cycle after the current cycle (in triangle-wave PWM mode 1) or half cycle after the current cycle (in triangle-wave PWM mode 2) in GTCCRC.
Page 386 RA2L1 User's Manual 20. General PWM Timer (GPT) In saw-wave mode, if the GTUDDTYC.OADTY bit or the GTUDDTYC.OBDTY bit is modified during the count operation, the output duty setting is reflected at an overflow (when modified during up-counting) or an underflow (when modified during down-counting).
Page 387: Hardware Count Start/Count Stop And Clear Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register bbbb aaaa 0x00000000 Time Register write Register write Register write GTUDDTYC.OADTY GTIOC0A pin output GTIOC0B pin output 100% [Setting examples] GPT320.GTIOR.GTIOA[4:0] bits: 00011b initial low output, output toggled at compare match, output retained at cycle end GPT320.GTUDDTYC.OADTYR bit: 0b Applied the value of duty 0% or 100% output to GTIOA[3:2] bits function after 0% or 100% duty setting is released...
Page 388 RA2L1 User's Manual 20. General PWM Timer (GPT) GTCNT counter value GTPR register Count started at ELC event Input 0x00000000 Time ELC event input Note: ELC event input: ELC_GPTA event input Figure 20.30 Example of count start operation by a hardware source started at the input of the signal from the ELC_GPTA event Table 20.24 Example setting for count start operation by a hardware source...
Page 389 RA2L1 User's Manual 20. General PWM Timer (GPT) Count stopped at Count started at ELC event input 1 ELC event Input 2 GTCNT counter value GTPR register Software start 0x00000000 Time ELC event input 1 ELC event input 2 Note: ELC event input 1: ELC_GPTA event input ELC event input 2: ELC_GPTB event input Figure 20.31...
Page 390 RA2L1 User's Manual 20. General PWM Timer (GPT) Count started on the rising Count stopped on the falling edge of GTETRGA edge of GTETRGA GTCNT counter value GTPR register Count started on the rising edge of GTETRGA 0x00000000 Time GTETRGA pin input Figure 20.32 Example of count start/stop operation by a hardware source started on the rising edge of GTETRGA pin input, and stopped on the falling edge of GTETRGA pin input...
Page 391 RA2L1 User's Manual 20. General PWM Timer (GPT) GTCNT counter value Count stopped/cleared at ELC event Input 2 Clear by software (by writing 1 to corresponding channel number bit of GTCLR register) Count started at Count started at ELC event input 1 ELC event input 1 0x00000000 Time...
Page 392: Synchronized Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.27 Example setting for count clearing operation by a hardware source (2 of 2) Step Name Description Set cycle Set the cycle in the GTPR register. Set initial value for counter Set the initial value in the GTCNT counter.
Page 393 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0x00000000 Time GPT321.GTCNT counter value GPT321.GTPR register 0x00000000 Time GPT322.GTCNT counter value GPT322.GTPR register 0x00000000 Time GPT323.GTCNT counter value GPT323.GTPR register Time 0x00000000 Write 0x0000000F in Write 0x0000000F in Write 0x0000000F in GTSTP or GTCLR register GTSTR register...
Page 394 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register Set initial value cccc bbbb aaaa 0x00000000 Time GPT321.GTCNT counter value GPT321.GTPR register cccc Set initial value bbbb aaaa Time 0x00000000 GPT322.GTCNT counter value GPT322.GTPR register cccc bbbb Set initial value aaaa...
Page 395 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0x00000000 Time GPT321.GTCNT counter value GPT321.GTPR register 0x00000000 Time GPT322.GTCNT counter value GPT322.GTPR register 0x00000000 Time GPT323.GTCNT counter value GPT323.GTPR register Time 0x00000000 Count operation of channel 0/1/2/3 Count operation of channel started by ELC event input 1 0/1/2/3 started by ELC...
Page 396: Pwm Output Operation Examples
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.28 Example setting for simultaneous start by a hardware source (2 of 2) Step Name Description Set hardware count stop Select a hardware source for stopping count operation with GTPSR register and wait for count stop by the hardware source Figure 20.38, GTPSR.PSELCB = 1.
Page 397 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRB register GPT320.GTCCRA register GPT164.GTCNT counter GPT164.GTPR register GPT164.GTCCRB register GPT164.GTCCRA register GPT165.GTCNT counter GPT165.GTPR register GPT165.GTCCRB register GPT165.GTCCRA register GPT166.GTCNT counter GPT166.GTPR register GPT166.GTCCRB register GPT166.GTCCRA register GTIOC0A pin output GTIOC0B pin output GTIOC4A pin output...
Page 398 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register = GPT320.GTCCRB register GPT164.GTCNT counter GPT164.GTPR register GPT164.GTCCRA register = GPT164.GTCCRB register GPT165.GTCNT counter GPT165.GTPR register GPT165.GTCCRA register = GPT165.GTCCRB register GTIOC0A pin output GTIOC0B pin output GTIOC4A pin output GTIOC4B pin output GTIOC5A pin output...
Page 399 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRD register GPT320.GTCCRC register GPT164.GTCNT counter GPT164.GTPR register GPT164.GTCCRD register GPT164.GTCCRC register GPT165.GTCNT counter GPT165.GTPR register GPT165.GTCCRD register GPT165.GTCCRC register GTIOC0A pin output GTIOC0B pin output GPT320.GTDVU GPT320.GTDVU GTIOC4A pin output GTIOC4B pin output GPT164.GTDVU...
Page 400 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register GPT164.GTCNT counter GPT164.GTPR register GPT164.GTCCRA register GPT164.GTCCRB register GPT165.GTCNT counter GPT165.GTPR register GPT165.GTCCRA register GPT165.GTCCRB register GTIOC0A pin output GTIOC0B pin output GTIOC4A pin output GTIOC4B pin output GTIOC5A pin output GTIOC5B pin output...
Page 401 RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRA register GPT164.GTCNT counter GPT164. GTPR register GPT164.GTCCRA register GPT165.GTCNT counter GPT165. GTPR register GPT165.GTCCRA register GPT320.GTDVU GPT320.GTDVU GTIOC0A pin output GTIOC0B pin output GPT164.GTDVU GTIOC4A pin output GPT164.GTDVU GTIOC4B pin output GPT165.GTDVU...
Page 402: Phase Counting Function
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter GPT320. GTPR register GPT320.GTCCRC register GPT320.GTCCRD register GPT164.GTCNT counter GPT164. GTPR register GPT164.GTCCRC register GPT164.GTCCRD register GPT165.GTCNT counter GPT165. GTPR register GPT165.GTCCRC register GPT165.GTCCRD register GPT320.GTDVU GPT320.GTDVU GTIOC0A pin output GTIOC0B pin output GPT164.GTDVU GTIOC4A pin output...
Page 403 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Up-counting Down-counting Time Figure 20.45 Example of phase counting mode 1 Table 20.29 Conditions of up-counting/down-counting in phase counting mode 1 : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 404 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Up-counting Down-counting Time Figure 20.46 Example of phase counting mode 2 (A) Table 20.30 Conditions of up-counting/down-counting in phase counting mode 2 (A) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 405 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Down-counting Up-counting Time Figure 20.47 Example of phase counting mode 2 (B) Table 20.31 Conditions of up-counting/down-counting in phase counting mode 2 (B) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 406 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Up-counting Down-counting Time Figure 20.48 Example of phase counting mode 2 (C) Table 20.32 Conditions of up-counting/down-counting in phase counting mode 2 (C) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 407 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Down-counting Up-counting Time Figure 20.49 Example of phase counting mode 3 (A) Table 20.33 Conditions of up-counting/down-counting in phase counting mode 3 (A) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 408 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Down-counting Up-counting Time Figure 20.50 Example of phase counting mode 3 (B) Table 20.34 Conditions of up-counting/down-counting in phase counting mode 3 (B) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 409 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Up-counting Down-counting Time Figure 20.51 Example of phase counting mode 3 (C) Table 20.35 Conditions of up-counting/down-counting in phase counting mode 3 (C) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 410 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Down-counting Up-counting Time Figure 20.52 Example of phase counting mode 4 Table 20.36 Conditions of up-counting/down-counting in phase counting mode 4 : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 411 RA2L1 User's Manual 20. General PWM Timer (GPT) GTIOC0A pin input GTIOC0B pin input GTCNT counter Up-counting Time Figure 20.53 Example of phase counting mode 5 (A) Table 20.37 Conditions of up-counting/down-counting in phase counting mode 5 (A) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input...
Page 412: Output Phase Switching (Gpt_Ops)
RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.38 Conditions of up-counting/down-counting in phase counting mode 5 (B) : Rising edge : Falling edge GTIOC0A pin input GTIOC0B pin input Operation Register setting High Not counting GTUPSR = 0x0000C000 GTDNSR = 0x00000000 Up-counting Not counting...
Page 413 RA2L1 User's Manual 20. General PWM Timer (GPT) Soft setting (UF/VF/WF) OPSCR. Hall sensor UF/VF/WF input edge sample GPT_UVWEDGE GPT core clock (every GPT core clock) sample Input phase (Input U-phase) PWM edge (Input V-phase) sample Synchronize (Input W-phase) From Hall element noise filter GPT core clock GTIU...
Page 414 RA2L1 User's Manual 20. General PWM Timer (GPT) PWM signal Input sel after “U-phase” GTIU Input sel after “V-phase” GTIV Input sel after “W-phase” GTIW Output “U-phase (Up)” GTOUUP Output “U-phase (Lo)” GTOULO Output “V-phase (Up)” GTOVUP Output “V-phase (Lo)” GTOVLO Output “W-phase (Up)”...
Page 415 RA2L1 User's Manual 20. General PWM Timer (GPT) PWM signal "U-phase" after input selection GTIU "V-phase" after input selection GTIV "W-phase" after input selection GTIW Output enable OPSCR.EN Auto clear Setting by software Output Disabled Source Select 0 (Group A output disable request) OPSCR.GRP Group output disable OPSCR.GODF...
Page 416 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.39 Input selection processing method Register OPSCR Selection of input phase sampling method Synchronization input/output selection FB bit ALIGN bit (U/V/W-phase) process (GPT_OPS internal node name) External Input at PWM Falling Edge Sampling Input Phase (PCLKD synchronization + falling edge sample) Input U-Phase (gtu_sync)
Page 417 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.41 Decode table of input phase (OPSCR.RV = 1) (2 of 2) Input phase (U/V/W) 6-phase enable {U/V/W (Up/Lo)} by decoding input phase (GPT_OPS internal node name) (GPT_OPS internal node name) Input U- Input V- Input W-...
Page 418 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.43 Output selection control method (positive phase) (2 of 2) Enable-phase output Positive-phase output Invert-phase output Output port name (positive phase = up) control (P) control control (output selection internal node allocation) GTOUUP GTOVUP OPSCR.EN...
Page 419: Interrupt Sources
RA2L1 User's Manual 20. General PWM Timer (GPT) 20.3.11.7 Event Link Controller (ELC) output In the GPT_OPS control flow conceptual diagram shown in Figure 20.55, (5) outputs the Hall sensor input signal edge to the ELC. The Hall sensor input edge signal is the logical OR of the rising and falling edge signals of each U-phase/V-phase/W-phase input sampled at PCLKD.
Page 420 RA2L1 User's Manual 20. General PWM Timer (GPT) Table 20.46 Interrupt sources Channel Name Interrupt source Interrupt flag DTC activation n = 0 to 3 GPTn_CCMPA GPT32n.GTCCRA input capture/compare match GTST[0] (TCFA) Possible GPTn_CCMPB GPT32n.GTCCRB input capture/compare match GTST[1] (TCFB) Possible GPTn_CMPC GPT32n.GTCCRC compare match...
Page 421: Dtc Activation
RA2L1 User's Manual 20. General PWM Timer (GPT) ● GTBER.CCRA[1:0] = 10b, 11b (buffer operation with the GTCCRD register). GPTn_OVF interrupt (n = 0 to 9) An interrupt request is generated in the following conditions: ● In saw-wave mode, interrupt requests are enabled at overflows (when the GTCNT counter value changes from GTPR to 0 during up-counting) ●...
Page 422: Protection Function
RA2L1 User's Manual 20. General PWM Timer (GPT) The noise filter functionality includes enabling and disabling the noise filter for each pin and setting of the sampling clock for each channel. Figure 20.59 shows the timing of noise filtering. Sampling clock Noise filter enable/ disable register Eliminated...
Page 423: Gtiocnm Pin Output Negate Control (N = 0 To 9, M = A, B)
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register 0x00000000 Time Register write timing is too late Register write Register write for buffer transfer timing bbbb cccc dddd eeee GPT320.GTCCRF register Buffer transfer at trough Buffer transfer at crest Buffer transfer at crest aaaa bbbb...
Page 424: Initialization Method Of Output Pins
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register cccc bbbb aaaa 0x00000000 Time Register write Register write Register write Register write GPT320.GTCCRC register bbbb cccc Buffer transfer Buffer transfer Buffer transfer at overflow at overflow at overflow GPT320.GTCCRA register aaaa...
Page 425: Pin Initialization Due To Error During Operation
RA2L1 User's Manual 20. General PWM Timer (GPT) GPT320.GTCNT counter value GPT320.GTPR register GPT320.GTCCRA register GPT320.GTCCRB register 0x00000000 Time Hi-Z GTIOC0A pin output Hi-Z GTIOC0B pin output Reset is released Count operation starts GTIOR.OAE and OBE bits are set Reset GPT initialization settings Count operation [Setting examples]...
Page 426: Setting Range For Gtcnt Counter
RA2L1 User's Manual 20. General PWM Timer (GPT) When the setting of GTCCRA = 0 or GTCCRA ≥ GTPR is made for the GTCCRA register during count operation, the output protection function is activated. However, if the following condition is not satisfied, the output protection function does not work normally: ●...
Page 427: Priority Order Of Each Event
RA2L1 User's Manual 20. General PWM Timer (GPT) selected in GTCR.TPCS[2:0]. Therefore, an event generated before the GTCNT counter actually starts is ignored, resulting in situations in which an event is accepted or an interrupt occurs after GTCR.CST is set to 0. 20.9.5 Priority Order of Each Event GTCNT register...
Page 428: Low Power Asynchronous General Purpose Timer (Agt)
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Low Power Asynchronous General Purpose Timer (AGT) 21.1 Overview The low power Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse output, external pulse width or period measurement, and counting external events.
Page 429 RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Data bus 16-bit 16-bit 16-bit reload reload reload register register register TCMEA or TCMEB = 1 TCK[2:0] AGT underflows TCK[2:0] = 000b CKS[2:0] PCLKB AGT underflows or AGTLCLK AGTCMA AGTCMB = 100b AGT is rewritten...
Page 430: Register Descriptions
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) 21.2 Register Descriptions 21.2.1 AGT : AGT Counter Register Base address: AGTn = 0x4008_4000 + 0x0100 × n (n = 0, 1) Offset address: 0x00 Bit position: Bit field: Value after reset: Symbol Function...
Page 431: Agtcmb : Agt Compare Match B Register
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) 21.2.3 AGTCMB : AGT Compare Match B Register Base address: AGTn = 0x4008_4000 + 0x0100 × n (n = 0, 1) Offset address: 0x04 Bit position: Bit field: Value after reset: Symbol Function 15:0...
Page 432 RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) TSTART bit (AGT Count Start) The count operation is started by writing 1 to the TSTART bit and stopped by writing 0. When the TSTART bit is set to 1 (count starts), the TCSTF flag is set to 1 (count in progress) in synchronization with the count source.
Page 433: Agtmr1 : Agt Mode Register 1
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) 21.2.5 AGTMR1 : AGT Mode Register 1 Base address: AGTn = 0x4008_4000 + 0x0100 × n (n = 0, 1) Offset address: 0x09 Bit position: TEDG Bit field: — TCK[2:0] TMOD[2:0] Value after reset:...
Page 434 RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Symbol Function CKS[2:0] *1 *2 *3 AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio 0 0 0: 1/1 0 0 1: 1/2 0 1 0: 1/4 0 1 1: 1/8 1 0 0: 1/16 1 0 1: 1/32 1 1 0: 1/64...
Page 435: Agtioc : Agt I/O Control Register
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Start count start setting Start count stop setting Count start Low power mode off （AGTCR.TSTART=1）（AGTMR2.LPM=0） Low power mode setting Count stop （AGTMR2.LPM=1）（AGTCR.TSTART=0） Finish setting Finish setting Figure 21.2 LPM how to write flow chart 21.2.7 AGTIOC : AGT I/O Control Register...
Page 436: Agtisr : Agt Event Pin Select Register
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) In pulse output mode, it only controls polarity of the AGTOn pin output and AGTIOn pin output. AGTOn pin output and AGTIOn pin output are initialized when the AGTMR1 register is written or the TSTOP bit in the AGTCR register is written with 1.
Page 437: Agtcmsr : Agt Compare Match Function Select Register
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) 21.2.9 AGTCMSR : AGT Compare Match Function Select Register Base address: AGTn = 0x4008_4000 + 0x0100 × n (n = 0, 1) Offset address: 0x0E Bit position: TOPO TCME TOPO TCME Bit field:...
Page 438: Operation
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Symbol Function TIES AGTIOn Pin Input Enable 0: External event input is disabled during Software Standby mode 1: External event input is enabled during Software Standby mode — These bits are read as 0. The write value should be 0. Note 1.
Page 439 RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0x5678 to AGT register with software Write 0x1234 to AGT register with software Register write clock Count source TSTART bit in AGTCR register TCMEB bit in AGTCMSR...
Page 440: Reload Register And Agt Compare Match A/B Register Rewrite Operation
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0x1234 to AGT register with software Write 0x5678 to AGT register with software Register write clock Count source TSTART bit in AGTCR register TCMEB bit in AGTCMSR...
Page 441: Timer Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0x1234 to AGTCMA register with software Write 0x2345 to AGTCMA register with software Register write clock Count source TSTART bit in AGTCR register 0x567...
Page 442: Pulse Output Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Count source Previous value Reload register New value (0x1010) (0x0300) Counter reloading occurs 0x02F 0x02F 0x02F 0x02F 0x101 0x100 0x100 0x000 0x101 0x100 0x100 0x100 0x100 0x100 AGT counter •••••...
Page 443: Event Counter Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Write 1 to TSTART bit in AGTCR register with software Write 0x0002 to Write 0x0004 to AGT register with AGT register with software software Count source TSTART bit in AGTCR register AGT register 0xFFFF...
Page 444: Pulse Width Measurement Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Event counter mode is entered TMOD[2:0] bits in 010b AGTMR1 register Event is counted at rising edge AGTIOC register 0x00 TSTART bit in AGTCR register Event input is started Event input is complete AGTIOn pin event input...
Page 445: Pulse Period Measurement Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) count source selected with the TCK[2:0] bits in the AGTMR1 register. When the specified level on the AGTIOn pin ends, the counter is stopped, the TEDGF bit in the AGTCR register is set to 1 (active edge received), and an interrupt request is generated.
Page 446: Compare Match Function
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Count source TSTART bit in AGTCR register Measurement pulse input Counter is reloaded 0x02F 0x02F 0x030 0x02F 0x02F 0x02F 0x02F 0x02F 0x02F 0x02F 0x02F 0x02F 0x030 0x02F 0x000 0x000 0x030 0x02F 0x02F...
Page 447: Output Settings For Each Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) n = AGT register content m = AGT Compare Match A register setting value p = AGT Compare Match B register setting value 0xFFFF Count starts Underflow Underflow Matched Matched Matched Matched...
Page 448: Standby Mode
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Table 21.6 AGTIOn pin setting AGTIOC register Operating mode TEDGSEL bit AGTIOn pin I/O Timer mode 0 or 1 Input (not used) Pulse output mode Normal output Inverted output Event counter mode 0 or 1 Input...
Page 449: Interrupt Sources
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) Table 21.9 Usable settings in Software Standby mode (AGT0) Operating mode AGTMR1.TCK[2:0] Operating clock Resurgence factor of CPU Timer mode 100b or 110b AGTLCLK or AGTSCLK — Pulse output mode 100b or 110b AGTLCLK or AGTSCLK —...
Page 450: Access To Counter Register
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) – After 1 (count starts) is written to the TSTART bit in the AGTCR register while the count is stopped, the TCSTF flag in the AGTCR register remains 0 (count stops) for 3 cycles of the count source. Do not access the registers associated with AGT other than the TCSTF flag until this bit is set to 1 (count in progress).
Page 451: How To Calculate Event Number, Pulse Width, And Pulse Period
RA2L1 User's Manual 21. Low Power Asynchronous General Purpose Timer (AGT) 21.4.6 How to Calculate Event Number, Pulse Width, and Pulse Period ● In event counter mode, event number is expressed mathematically as follows: Event number = initial value of counter [AGT register] - counter value of active event end ●...
Page 452: Realtime Clock (Rtc)
RA2L1 User's Manual 22. Realtime Clock (RTC) Realtime Clock (RTC) 22.1 Overview The RTC has two operation modes, normal operation mode and low-consumption clock mode. In each of the operation mode, the RTC has two counting modes, calendar count mode and binary count mode, that are used by switching register settings.
Page 453: Register Descriptions
RA2L1 User's Manual 22. Realtime Clock (RTC) Internal peripheral bus Realtime clock (RTC) Bus interface To each RCR2 RTCOUT function Time counter 1-Hz/64-Hz output Alarm function prescaler XCIN 128 Hz RSECAR/ RMINAR/ RSECCNT/ 32.768 kHz Sub-clock 128 Hz generation R64CNT BCNT0AR BCNT1AR BCNT0...
Page 454: Rseccnt : Second Counter (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) Symbol Function F16HZ 16-Hz Flag This bit indicates the 16-Hz state of the sub-second digit. F8HZ 8-Hz Flag This bit indicates the 8-Hz state of the sub-second digit. F4HZ 4-Hz Flag This bit indicates the 4-Hz state of the sub-second digit. F2HZ 2-Hz Flag This bit indicates the 2-Hz state of the sub-second digit.
Page 455: Rhrcnt : Hour Counter (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) Symbol Function MIN1[3:0] 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place. MIN10[2:0] 10-Minute Count Counts from 0 to 5 for 60-minute counting. —...
Page 456: Bcntn : Binary Counter N (N = 0 To 3) (In Binary Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) Symbol Function DAYW[2:0] Day-of-Week Counting 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday 1 0 1: Friday 1 1 0: Saturday 1 1 1: Setting prohibited —...
Page 457: Rmoncnt : Month Counter
RA2L1 User's Manual 22. Realtime Clock (RTC) A value from 01 through 31 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly. When specifying a value, the range of specifiable days depends on the month and whether the year is a leap year.
Page 458: Rsecar : Second Alarm Register (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.10 RSECAR : Second Alarm Register (in Calendar Count Mode) Base address: RTC = 0x4004_4000 Offset address: 0x10 Bit position: Bit field: SEC10[2:0] SEC1[3:0] Value after reset: Symbol Function SEC1[3:0] 1 Second Value for the ones place of seconds. SEC10[2:0] 10 Seconds Value for the tens place of seconds.
Page 459: Rhrar : Hour Alarm Register (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) This register is not used in low-consumption clock mode. RMINAR is an alarm register associated with the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1, the RMINAR value is compared with the RMINCNT value. From the following alarm registers, only those selected with the ENB bits set to 1 are compared with the associated counters: ●...
Page 460: Rwkar : Day-Of-Week Alarm Register (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) When all the respective values match, the IR flag associated with the RTC_ALM interrupt is set to 1. The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24): ● When the RCR2.HR24 bit is 0 – From 00 to 11 (in BCD). ●...
Page 461: Bcntnar : Binary Counter N Alarm Register (N = 0 To 3) (In Binary Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.14 BCNTnAR : Binary Counter n Alarm Register (n = 0 to 3) (in Binary Count Mode) Base address: RTC = 0x4004_4000 Offset address: 0x10 + 0x02 × n Bit position: Bit field: BCNTAR Value after reset: Symbol...
Page 462: Rmonar : Month Alarm Register (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.16 RMONAR : Month Alarm Register (in Calendar Count Mode) Base address: RTC = 0x4004_4000 Offset address: 0x1A Bit position: MON1 Bit field: — — MON1[3:0] Value after reset: Symbol Function MON1[3:0] 1 Month Value for the ones place of months.
Page 463: Ryraren : Year Alarm Enable Register (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) This register is not used in low-consumption clock mode. RYRAR is an alarm register associated with the BCD-coded year counter RYRCNT. The RYRAR values from 00 through 99 (in BCD) can be specified. If a value outside of this range is specified, the RTC does not operate correctly. This register is set to 0x0000 by an RTC software reset.
Page 464: Bcnt2Aer : Binary Counter 2 Alarm Enable Register (In Binary Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) the BCNTAER.ENB[7:0] bits. The binary counter (BCNT[31:0]) associated with the BCNTAER.ENB[31:0] bits that are set to 1 is compared with the binary alarm register (BCNTAR) and, when all match, the IR flag associated with the RTC_ALM interrupt is set to 1.
Page 465: Rcr1 : Rtc Control Register 1
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.22 RCR1 : RTC Control Register 1 Base address: RTC = 0x4004_4000 Offset address: 0x22 Bit position: RTCO Bit field: PES[3:0] Value after reset: Symbol Function Alarm Interrupt Enable 0: Disable alarm interrupt requests 1: Enable alarm interrupt requests Carry Interrupt Enable 0: Disable carry interrupt requests...
Page 466: Rcr2 : Rtc Control Register 2 (In Calendar Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) PES[3:0] bits (Periodic Interrupt Select) The PES[3:0] bits specify the period for the periodic interrupt. A periodic interrupt is generated with the period specified in these bits. 22.2.23 RCR2 : RTC Control Register 2 (in Calendar Count Mode) Base address: RTC = 0x4004_4000 Offset address: 0x24 Bit position:...
Page 467 RA2L1 User's Manual 22. Realtime Clock (RTC) START bit (Start) The START bit stops or restarts the prescaler or time counter operation. This bit is updated in synchronization with the next cycle of the count source. When the START bit is modified, check that the bit is updated before proceeding. RESET bit (RTC Software Reset) The RESET bit initializes the prescaler and registers to be reset by RTC software.
Page 468: Rcr2 : Rtc Control Register 2 (In Binary Count Mode)
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.24 RCR2 : RTC Control Register 2 (in Binary Count Mode) Base address: RTC = 0x4004_4000 Offset address: 0x24 Bit position: CNTM AADJ AADJ RTCO RESE Bit field: — — START Value after reset: Symbol Function Start...
Page 469: Rcr4 : Rtc Control Register 4
RA2L1 User's Manual 22. Realtime Clock (RTC) RTCOE bit (RTCOUT Output Enable) The RTCOE bit enables output of a 1-Hz/64-Hz clock signal from the RTCOUT pin. Use the START bit to stop counting before changing the value of the RTCOE bit. Do not stop counting (write 0 to the START bit) and change the value of the RTCOE bit at the same time.
Page 470: Rfrl : Frequency Register L
RA2L1 User's Manual 22. Realtime Clock (RTC) For details on count source setting, see section 22.3.1. Outline of Initial Settings of Registers after Power On section 22.3.2. Operation mode, Clock and Count Mode Setting Procedure. The count source must be selected only once before specifying the initial settings of the RTC registers at power on.
Page 471: Radj : Time Error Adjustment Register
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.2.28 RADJ : Time Error Adjustment Register Base address: RTC = 0x4004_4000 Offset address: 0x2E Bit position: Bit field: PMADJ[1:0] ADJ[5:0] Value after reset: Symbol Function ADJ[5:0] Adjustment Value In normal operation mode, these bits specify the adjustment value from the prescaler. In low-consumption clock mode, these bits specify the adjustment value from the 64-Hz counter.
Page 472: Operation Mode, Clock And Count Mode Setting Procedure
RA2L1 User's Manual 22. Realtime Clock (RTC) Power on Initial setting for clock supply, operation mode and count mode Clock supply, operation mode and count mode settings Time setting in the clock counter and initial Set the time setting of the time error adjustment register Initial setting of the alarm register Set the alarm Initial setting of the interrupt control register...
Page 473: Setting The Time
RA2L1 User's Manual 22. Realtime Clock (RTC) Set RCR4.ROPSEL bit=0; Set sub-clock or LOCO clock Select the operation mode RCR4.ROPSEL bit setting Supply 6 clocks of the clock selected by the Supply 6 count source clocks RCR4.ROPSEL and RCR4.RCKSEL bits Set the START bit to 0 Write 0 to the RCR2.START bit Wait for the RCR2.START bit to become 0...
Page 474: 30-Second Adjustment
RA2L1 User's Manual 22. Realtime Clock (RTC) Set the START bit to 0 Write 0 to the RCR2.START bit START = 0 Wait for the RCR2.START bit to become 0 Execute an RTC software reset Write 1 to the RCR2.RESET bit RESET = 0 Wait for the RCR2.RESET bit to become 0 Set the year, month, day of the week,...
Page 475: Reading 64-Hz Counter And Time
RA2L1 User's Manual 22. Realtime Clock (RTC) Clock is in operation RCR2.START = 1 Set the RCR2.ADJ30 bit to 1 Execute 30-second adjustment. Confirm RCR2.ADJ30 = 0 Wait for the RCR2.ADJ30 bit to become 0 Figure 22.5 30-second adjustment 22.3.5 Reading 64-Hz Counter and Time Figure 22.6 shows how to read a 64-Hz counter and time.
Page 476 RA2L1 User's Manual 22. Realtime Clock (RTC) (a) To read the time without using interrupt Disable the NVIC carry interrupt request Write 1 to the Interrupt Clear-Enable Register corresponding to the RTC_CUP interrupt Enable the RTC carry interrupt request Write 1 to the RCR1.CIE bit Write 0 to the ICU.IELSRn.IR flag and write 1 to the Interrupt Clear-Pending Register Clear the interrupt flag...
Page 477: Alarm Function
RA2L1 User's Manual 22. Realtime Clock (RTC) Only method (a) could be used in low-consumption mode. 22.3.6 Alarm Function Alarm function is not supported in low-consumption clock mode. Figure 22.7 shows how to use the alarm function. Write 1 to the Interrupt Clear-Enable Register Disable the NVIC alarm interrupt request associated with the RTC_ALM interrupt Set alarm enable at the same time as or after the...
Page 478: Procedure For Disabling Alarm Interrupt
RA2L1 User's Manual 22. Realtime Clock (RTC) Counter registers: RSECCNT, RMINCNT, RHRCNT, RWKCNT, RDAYCNT, RMONCNT, RYRCNT Alarm registers: RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, RYRAREN 22.3.7 Procedure for Disabling Alarm Interrupt Figure 22.8 shows the procedure for disabling the enabled alarm interrupt request. Enable the alarm interrupt The RCR1.AIE bit register is set to 1 Write 0 to the Interrupt Clear-Enable Register...
Page 479 RA2L1 User's Manual 22. Realtime Clock (RTC) Example 1: Sub-clock oscillator running at 32.769 kHz Adjustment procedure When the sub-clock oscillator is running at 32.769 kHz, 1 second elapses every 32769 clock cycles. The RTC is meant to run at 32768 clock cycles, so the clock runs fast by 1 clock cycle every second. The time on the clock is fast by 60 clock cycles per minute, so adjustment can take the form of setting the clock back by 60 cycles every minute.
Page 480: Adjustment By Software
RA2L1 User's Manual 22. Realtime Clock (RTC) Example 5: Sub-clock oscillator running at 32.764 kHz Adjustment procedure The 128-Hz clock is generated from the sub-clock with 256 dividing ratio. When the sub-clock oscillator runs at 32.764 kHz, 1 second elapses in every 32764 sub-clock cycles, thus 32764/256 count source cycles. Because the RTC operates for 32768/256 clock cycles as 1 second, the clock is delayed for 4/256 clock cycles per second.
Page 481: Interrupt Sources
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.4 Interrupt Sources The RTC has three interrupt sources, as listed in Table 22.3. Table 22.3 RTC interrupt sources Name Interrupt source RTC_ALM Alarm interrupt RTC_PRD Periodic interrupt RTC_CUP Carry interrupt Alarm interrupt (RTC_ALM) This interrupt is generated based on the comparison result between the alarm registers and RTC counters.
Page 482: Event Link Output
RA2L1 User's Manual 22. Realtime Clock (RTC) 64 Hz Interrupt generated by the simultaneous occurrence of the selected edge of the R64CNT signal 64-Hz signal and register reading 1 Hz An interrupt is generated by a carry to the second counter/ Interrupt binary counter 0 Detail...
Page 483: Use Of Periodic Interrupts
RA2L1 User's Manual 22. Realtime Clock (RTC) ● RMONCNT ● RYRCNT ● RCR1.RTCOS ● RCR2.RTCOE ● RCR2.HR24 ● RFRL The counter should be stopped before writing to any of these registers. 22.6.2 Use of Periodic Interrupts Figure 22.11 shows the procedure for using periodic interrupts. The generation and period of the periodic interrupt can be changed by setting the RCR1.PES[3:0] bits.
Page 484: Transitions To Low Power Modes After Setting Registers
RA2L1 User's Manual 22. Realtime Clock (RTC) 22.6.4 Transitions to Low Power Modes after Setting Registers A transition to a low power state (Software Standby mode) during a write to an RTC register might corrupt the value of the register. After setting the register, confirm that the setting is in place before initiating a transition to a low power state. 22.6.5 Notes on Writing to and Reading from Registers ●...
Page 485 RA2L1 User's Manual 22. Realtime Clock (RTC) Set RCR4.ROPSEL bit to 0 Select the operation mode Select the count source RCR4.RCKSEL bit setting Supply 6 clocks of the clock selected by the Supply 6 clocks of the count source RCR4.RCKSEL bit Clear the START bit to 0 Wait for the RCR2.START bit to become 0 START = 0...
Page 486: Watchdog Timer (Wdt)
RA2L1 User's Manual 23. Watchdog Timer (WDT) Watchdog Timer (WDT) 23.1 Overview The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow interrupt or watchdog timer reset.
Page 487: Register Descriptions
RA2L1 User's Manual 23. Watchdog Timer (WDT) Interrupt request (WDT_NMIUNDF) Interrupt control circuit Clock frequency WDT output divider Reset control circuit PCLK/4 PCLK/64 PCLK PCLK/128 WDT control circuit 14-bit down-counter PCLK/512 PCLK/2048 PCLK/8192 Option Function Select Register 0 (OFS0) Count stop control output in Sleep mode Clock control circuit Event signal output...
Page 488: Wdtcr : Wdt Control Register
RA2L1 User's Manual 23. Watchdog Timer (WDT) 23.2.2 WDTCR : WDT Control Register Base address: WDT = 0x4004_4200 Offset address: 0x02 Bit position: Bit field: — — RPSS[1:0] — — RPES[1:0] CKS[3:0] — — TOPS[1:0] Value after reset: Symbol Function TOPS[1:0] Timeout Period Select 0 0: 1024 cycles (0x03FF)
Page 489 RA2L1 User's Manual 23. Watchdog Timer (WDT) Table 23.2 Timeout period settings Timeout period CKS[3:0] bits TOPS[1:0] bits Clock division ratio (number of cycles) PCLKB clock cycles PCLKB/4 1024 4096 4096 16384 8192 32768 16384 65536 PCLKB/64 1024 65536 4096 262144 8192 524288...
Page 490: Wdtsr : Wdt Status Register
RA2L1 User's Manual 23. Watchdog Timer (WDT) Table 23.3 Relationship between the timeout period and window start and end counter values Timeout period Window start and end counter value TOPS[1:0] Cycles Counter value 100% 1024 0x03FF 0x03FF 0x02FF 0x01FF 0x00FF 4096 0x0FFF 0x0FFF 0x0BFF...
Page 491: Wdtrcr : Wdt Reset Control Register
RA2L1 User's Manual 23. Watchdog Timer (WDT) Symbol Function REFEF Refresh Error Flag 0: No refresh error occurred 1: Refresh error occurred Note 1. Only 0 can be written to clear the flag. The WDTSR register indicates the counter value of the down-counter and the status of whether an underflow or refresh error occurred in the down-counter.
Page 492: Wdtcstpr : Wdt Count Stop Control Register
RA2L1 User's Manual 23. Watchdog Timer (WDT) Symbol Function RSTIRQS Reset Interrupt Request Select 0: Enable non-maskable interrupt request or interrupt request output 1: Enable reset output The WDTRCR register controls reset output by a WDT down-counter underflow or interrupt request output. Some constraints apply to writes to the WDTRCR register.
Page 493: Register Start Mode
RA2L1 User's Manual 23. Watchdog Timer (WDT) Select auto start mode or register start mode by setting the WDT Start Mode Select bit (OFS0.WDTSTRT) in the OFS0 register. When the auto start mode is selected, the settings in the WDT Control Register (WDTCR), WDT Reset Control Register (WDTRCR), and WDT Count Stop Control Register (WDTCSTPR) are disabled while the settings in the OFS0 register are enabled.
Page 494: Auto Start Mode
RA2L1 User's Manual 23. Watchdog Timer (WDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period Reset pin Control register (WDTCR) Writing to Writing to the (1) Initial value Writing to the Writing to the Writing to the the register register is (2) Set value...
Page 495: Controlling Writes To The Wdtcr, Wdtrcr, And Wdtcstpr Registers
RA2L1 User's Manual 23. Watchdog Timer (WDT) runaway program or if a refresh error occurs due to refreshing outside the refresh-permitted period, the WDT outputs the reset signal or non-maskable interrupt request/interrupt request (WDT_NMIUNDF). After the reset signal or non-maskable interrupt request/interrupt request is generated, the counter reloads the timeout period after counting for 1 cycle.
Page 496: Refresh Operation
RA2L1 User's Manual 23. Watchdog Timer (WDT) After a refresh (counting starts) or a write to WDTCR, WDTRCR or WDTCSTPR register, the protection signal in the WDT becomes 1 to protect WDTCR, WDTRCR and WDTCSTPR register against subsequent write attempts. This protection is released by the reset source of the WDT.
Page 497: Status Flags
RA2L1 User's Manual 23. Watchdog Timer (WDT) Peripheral clock (PCLK) WDTCLK Data written to 0x00 0x54 0x00 0xFF WDTRR register Refresh WDTRR register write signal enabled (internal signal) WDTRR register 0xFF 0x00 0xFF 0x00 0xFF Refresh disabled Refresh synchronization signal Refresh signal (after synchronization Refresh request...
Page 498: Reading The Down-Counter Value
RA2L1 User's Manual 23. Watchdog Timer (WDT) Table 23.4 WDT interrupt source Name Interrupt source Interrupt to CPU Start DTC WDT_NMIUNDF ● Down-counter underflow Possible Not possible ● Refresh error 23.3.7 Reading the Down-Counter Value The WDT stores the counter value in the down-counter value bits (WDTSR.CNTVAL[13:0]) of the WDT Status Register. Check these bits to obtain the counter value.
Page 499: Output To The Event Link Controller (Elc)
RA2L1 User's Manual 23. Watchdog Timer (WDT) 23.4 Output to the Event Link Controller (ELC) The WDT is capable of a link operation for the previously specified module when interrupt request signal is used as an event signal by the ELC. The event signal is output by the counter underflow and refresh error. An event signal is output regardless of the setting of the Reset Interrupt Request Select bit (WDTRCR.RSTIRQS) in register start mode or auto start mode.
Page 500: Independent Watchdog Timer (Iwdt)
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) Independent Watchdog Timer (IWDT) 24.1 Overview The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be serviced periodically to prevent counter underflow. The IWDT provides functionality to reset the MCU or to generate a non-maskable interrupt or an underflow interrupt.
Page 501: Register Descriptions
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) Interrupt request (IWDT_NMIUNDF) Interrupt control circuit IWDT reset output Reset control circuit Clock frequency divider IWDTCLK IWDTCLK IWDTCLK/16 IWDTCLK/32 IWDT control circuit 14-bit counter IWDTCLK/64 IWDTCLK/128 IWDTCLK/256 Option Function Select Register 0 (OFS0) Event signal output Event link controller...
Page 502: Iwdtsr : Iwdt Status Register
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) 24.2.2 IWDTSR : IWDT Status Register Base address: IWDT = 0x4004_4400 Offset address: 0x04 Bit position: REFE UNDF Bit field: CNTVAL[13:0] Value after reset: Symbol Function 13:0 CNTVAL[13:0] Down-counter Value Value counted by the down-counter UNDFF Underflow Flag 0: No underflow occurred...
Page 503: Ofs0 : Option Function Select Register 0
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) ● When OFS0.IWDTCKS[3:0] = 0x5, N = 256. 24.2.3 OFS0 : Option Function Select Register 0 For information on the Option Function Select Register 0 (OFS0), see section 6.2.1. OFS0 : Option Function Select Register IWDTTOPS[1:0] bits (IWDT Timeout Period Select) The IWDTTOPS[1:0] bits select the timeout period, that is, the period until the down-counter underflows, from 128, 512, 1024, or 2048 cycles, taking the divided clock specified in the IWDTCKS[3:0] bits as 1 cycle.
Page 504 RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) IWDTRPES[1:0] bits (IWDT Window End Position Select) The IWDTRPES[1:0] bits specify the window end position that indicates the refresh-permitted period. 75%, 50%, 25%, or 0% of the timeout period can be selected for the window end position. Set the window end position to a value less than the window start position (window start position >...
Page 505: Operation
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) IWDTSTPCTL bit (IWDT Stop Control) The IWDTSTPCTL bit selects whether to stop counting on transition to Sleep, Snooze, or Software Standby mode. 24.3 Operation 24.3.1 Auto Start Mode When the IWDT Start Mode Select bit (OFS0.IWDTSTRT) in the Option Function Select Register 0 is 0, auto start mode is selected, otherwise the IWDT is disabled.
Page 506: Refresh Operation
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) Counter value 100% Refresh- prohibited period Refresh- permitted period Refresh- prohibited period Reset pin Refresh the counter Active: High Counting starts Counting starts Counting starts Counting starts Underflow Refresh error Refresh error Status flag Refresh error flag cleared...
Page 507: Status Flags
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) ● 0x00 → 0xAA (0x00 and a value other than 0xFF) → 0xFF. After 0xFF is written to the IWDTRR register, refreshing the counter requires up to 4 cycles of the signal for counting (the IWDT-Dedicated Clock Frequency Division Ratio Select bits (OFS0.IWDTCKS[3:0]) to determine how many cycles of the IWDT-dedicated clock (IWDTCLK) make up 1 cycle for counting.
Page 508: Reset Output
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) written. For the time period between when 0 is written in each flag and when its value is reflected, see section 24.2.2. IWDTSR : IWDT Status Register. 24.3.4 Reset Output When the IWDT Reset Interrupt Request Select bit (OFS0.IWDTRSTIRQS) in the Option Function Select Register 0 (OFS0) is set to 1, a reset signal is output when an underflow in the counter or a refresh error occurs.
Page 509: Usage Notes
RA2L1 User's Manual 24. Independent Watchdog Timer (IWDT) An event signal is output regardless of the setting of the OFS0.IWDTRSTIRQS bit. An event signal can also be output at generation of the next interrupt source while the Refresh Error flag (IWDTSR.REFEF) or Underflow flag (IWDTSR.UNDFF) is 1.
Page 510: Serial Communications Interface (Sci)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Serial Communications Interface (SCI) 25.1 Overview The Serial Communications Interface (SCI) × 5 channels have asynchronous and synchronous serial interfaces: ● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter (ACIA)) ● 8-bit clock synchronous interface ●...
Page 511 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.1 SCI specifications (2 of 2) Parameter Specifications Address match Interrupt request/event output can be issued upon detecting a match between received data and the value in the compare match register Address mismatch (SCI0 Snooze end request can be issued when detecting a mismatch between the only) receive data...
Page 512: Register Descriptions
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Internal Module Data Bus Peripheral Bus SCMR RDRHL FRDRH TDRHL FTDRH MDDR SSR/SSR_SMCI/ PCLK FRDRL FTDRL SSR_FIFO PCLK/4 Baud rate SCR/SCR_SMCI generator PCLK/16 SMR/SMR_SMCI Clock SEMR PCLK/64 RXDn/SCLn/MISOn SPMR Parity addition SCIn_TEI SCIn_TXI Match check (interrupt request)
Page 513: Rdr : Receive Data Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.2 RDR : Receive Data Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x05 Bit position: Bit field: Value after reset: RDR is an 8-bit register that stores received data. When one frame of serial data is received, it is transferred from RSR to RDR, and the RSR register can receive more data.
Page 514 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function RDAT[8:0] Serial receive data Stores the serial receive data. Valid only in asynchronous mode, including multi-processor mode, and clock synchronous mode, and with FIFO selected. Multi-Processor Bit Flag Stores the value of the multi-processor bit in the serial receive data, RDAT[8:0]. Valid only in asynchronous mode with SMR.MP = 1, and with FIFO selected.
Page 515: Tdr : Transmit Data Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.5 TDR : Transmit Data Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x03 Bit position: Bit field: Value after reset: Symbol Function Serial Transmit Data TDR is an 8-bit register that stores transmit data.
Page 516: Ftdrhl/Ftdrh/Ftdrl : Transmit Fifo Data Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.7 FTDRHL/FTDRH/FTDRL : Transmit FIFO Data Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0) Offset address: 0x0E (FTDRHL/FTDRH) 0x0F (FTDRL) Bit position: Bit field: — — — —...
Page 517: Smr : Serial Mode Register For Non-Smart Card Interface Mode (Scmr.smif = 0)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.9 SMR : Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0) Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x00 Bit position: Bit field: STOP...
Page 518: Smr_Smci : Serial Mode Register For Smart Card Interface Mode (Scmr.smif = 1)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) STOP bit (Stop Bit Length) The STOP bit selects the stop bit length in transmission. In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit frame.
Page 519: Scr : Serial Control Register For Non-Smart Card Interface Mode (Scmr.smif = 0)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Note 1. n is the decimal notation of the value of n in the BRR register. See section 25.2.17. BRR : Bit Rate Register. Note 2. Writable only when SCR_SMCI.TE = 0 and SCR_SMCI.RE = 0 (both serial transmission and reception are disabled). The SMR_SMCI register sets the communication format and clock source for the on-chip baud rate generator.
Page 520 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function CKE[1:0] Clock Enable 0 0: In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin. 0 1: In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin.
Page 521: Scr_Smci : Serial Control Register For Smart Card Interface Mode (Scmr.smif = 1)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) When the MPB bit is set to 1, the MPIE bit is automatically set to 0, SCIn_RXI and SCIn_ERI interrupt requests are enabled (if the RIE bit in SCR is set to 1), and setting of the ORER and FER flags to 1 is enabled. Set MPIE to 0 if the multi-processor communications function is not used.
Page 522 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function MPIE Multi-Processor Interrupt Enable Set this bit to 0 in smart card interface mode Receive Enable 0: Disable serial reception 1: Enable serial reception Transmit Enable 0: Disable serial transmission 1: Enable serial transmission Receive Interrupt Enable 0: Disable SCIn_RXI and SCIn_ERI interrupt requests...
Page 523: Ssr : Serial Status Register For Non-Smart Card Interface And Non-Fifo Mode (Scmr.smif = 0, Fcr.fm = 0)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.13 SSR : Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0) Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x04 Bit position: Bit field:...
Page 524 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [Clearing conditions] ● When transmit data is written to the TDR register while the SCR.TE bit is 1 ● When 0 is written to TDRE after reading TDRE = 1 while the SCR.TE bit is 1 PER flag (Parity Error Flag) The PER flag indicates that a parity error occurred during reception in asynchronous mode and the reception ended abnormally.
Page 525: Ssr_Fifo : Serial Status Register For Non-Smart Card Interface And Fifo Mode (Scmr.smif = 0, Fcr.fm = 1)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) [Setting condition] ● When the reception ends normally, and receive data is forwarded from the RSR register to the RDR register. [Clearing conditions] ● When 0 is written to RDRF after reading RDRF = 1 ●...
Page 526 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function TDFE Transmit FIFO Data Empty Flag 0: The amount of transmit data written in FTDRHL exceeds the specified transmit triggering number 1: The amount of transmit data written in FTDRHL is equal to or less than the specified transmit triggering number Note 1.
Page 527 RA2L1 User's Manual 25. Serial Communications Interface (SCI) When the SCR.RE bit is set to 0 (serial reception is disabled), the PER flag is not affected and retains its previous value. FER flag (Framing Error Flag) The FER flag indicates whether there is a framing error in the data read from the FRDRHL register in asynchronous mode when the address match function is disabled (DCCR.DCME = 0).
Page 528: Ssr_Smci : Serial Status Register For Smart Card Interface Mode (Scmr.smif = 1)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) ● When 0 is written to the TDFE flag after reading TDFE = 1. The setting conditions are given priority when TE = 0. When the setting condition and clearing condition occur at the same time, the TDFE flag is set to 0.
Page 529 RA2L1 User's Manual 25. Serial Communications Interface (SCI) – When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 0, 12.5 ETUs after the start of transmission – When SMR_SMCI.GM = 0 and SMR_SMCI.BLK = 1, 11.5 ETUs after the start of transmission –...
Page 530: Scmr : Smart Card Mode Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) TDRE flag (Transmit Data Empty Flag) The TDRE flag indicates the presence of transmit data in the TDR register. [Setting conditions] ● When the SCR_SMCI.TE bit is 0 ● When data is transmitted from the TDR register to the TSR register [Clearing conditions] ●...
Page 531: Brr : Bit Rate Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Note 1. Writable only when the TE and RE bits in SCR/SCR_SMCI are 0 (both serial transmission and reception are disabled). Note 2. The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode. Note 3.
Page 532 RA2L1 User's Manual 25. Serial Communications Interface (SCI) The initial value of the BRR register is 0xFF. The BRR register can be read by the CPU, but it can be written to only when the TE and RE bits in SCR/SCR_SMCI are 0. Table 25.5 Relationship between N setting in BRR and bit rate B SEMR settings...
Page 533 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.8 Base clock settings in smart card interface mode (2 of 2) SCMR.BCP2 bit setting SMR_SMCI.BCP[1:0] bits setting BCP2 bit BCP[1:0] bits Base clock cycles for 1-bit period 186 clock cycles 512 clock cycles 32 clock cycles 64 clock cycles...
Page 534 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.9 Examples of BRR settings for different bit rates in asynchronous mode (1) (3 of 3) Operating frequency PCLK (MHz) 17.2032 19.6608 Bit rate (bps) Error (%) Error (%) Error (%) Error (%) Error (%) 9600...
Page 535 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.11 maximum bit rate for each operating frequency in asynchronous mode (2 of 2) SEMR settings SEMR settings Maximum Maximum PCLK BGDM ABCS ABCSE bit rate PCLK BGDM ABCS ABCSE bit rate (MHz) (bps) (MHz)
Page 536 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.12 Maximum bit rate with external clock input in asynchronous mode (2 of 2) Maximum bit rate (bps) PCLK (MHz) External input clock (MHz) SEMR.ABCS bit = 0 SEMR.ABCS bit = 1 4.5000 281250 562500...
Page 537 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.15 BBR settings for different bit rates in smart card interface mode (n = 0, S = 372) (2 of 2) Operating frequency PCLK (MHz) 14.2848 16.00 18.00 20.00 Bit rate (bps) Error (%) Error (%) Error (%)
Page 538: Mddr : Modulation Duty Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.18 MDDR : Modulation Duty Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x12 Bit position: Bit field: Value after reset: MDDR corrects the bit rate adjusted by the BRR register. When the BRME bit in SEMR is set to 1, the bit rate generated by the on-chip baud rate generator is evenly corrected using the settings in MDDR (M/256).
Page 539 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.20 Examples of BRR and MDDR settings for multiple bit rates in asynchronous mode (1) (1 of 3) Operating frequency PCLK (MHz) 9.8304 Bit rate BGDM Error BGDM Error BGDM Error (bps) 38400 0.03...
Page 540: Semr : Serial Extended Mode Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.19 SEMR : Serial Extended Mode Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x07 Bit position: RXDE ABCS Bit field: BGDM NFEN ABCS BRME...
Page 541: Snfr : Noise Filter Setting Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) NFEN bit (Digital Noise Filter Function Enable) The NFEN bit enables or disables the digital noise filter function. When the digital noise filter function is enabled: ● Noise cancellation is applied to the RXDn input signal in asynchronous mode ●...
Page 542: Simr1 : Iic Mode Register 1
RA2L1 User's Manual 25. Serial Communications Interface (SCI) NFCS[2:0] bits (Noise Filter Clock Select) The NFCS[2:0] bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set these bits to 000b. In simple I C mode, when 32 clocks are selected as one bit period in the basic clock selection bits of the SEMR register, set the NFCS [2: 0] bits in the range from 001b to 100b.
Page 543: Simr2 : Iic Mode Register 2
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.22 SIMR2 : IIC Mode Register 2 Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x0A Bit position: IICAC IICCS IICINT Bit field: —...
Page 544 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function IICRSTAREQ Restart Condition Generation 0: Do not generate restart condition 1: Generate restart condition *2 *3 *5 *6 IICSTPREQ Stop Condition Generation 0: Do not generate stop condition 1: Generate stop condition *2 *3 *5 *6 IICSTIF Issuing of Start, Restart, or Stop Condition Completed Flag...
Page 545: Sisr : Iic Status Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) [Clearing condition] ● On completion of stop condition generation. IICSTIF flag (Issuing of Start, Restart, or Stop Condition Completed Flag) After generating a condition, the IICSTIF flag indicates that the condition generation is complete. When using the IICSTAREQ, IICRSTAREQ, or IICSTPREQ bit to cause generation of a condition, do so after setting the IICSTIF flag to 0.
Page 546: Spmr : Spi Mode Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.2.25 SPMR : SPI Mode Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x0D Bit position: CKPO Bit field: CKPH — — CTSE Value after reset: Symbol...
Page 547: Fcr : Fifo Control Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) MFF flag (Mode Fault Flag) The MFF flag indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by reading this flag. [Setting condition] ● When input on the SSn pin is low during master operation in simple SPI mode (SSE bit = 1 and MSS bit = 0). [Clearing condition] ●...
Page 548: Fdr : Fifo Data Count Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function 15:12 RSTRG[3:0] RTS Output Active Trigger Number Select Valid only in asynchronous mode, including multi-processor mode, or clock synchronous mode, when FCR.FM = 1, SPMR.CTSE = 0, and SPMR.SSE = 0. The trigger number is specified in the RSTRG[3:0] bits.
Page 549: Lsr : Line Status Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function R[4:0] Receive FIFO Data Count Valid only in asynchronous mode, including multi-processor mode, or clock synchronous mode, when FCR.FM = 1. Indicates the amount of receive data stored in FRDRHL. —...
Page 550: Cdr : Compare Match Data Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) PNUM[4:0] bits (Parity Error Count) The PNUM[4:0] value indicates the amount of data with a parity error stored in the FRDRHL register. 25.2.29 CDR : Compare Match Data Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x1A Bit position: Bit field:...
Page 551 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Symbol Function IDSEL ID Frame Select Valid only in asynchronous mode, including multi-processor mode. 0: Always compare data regardless of the MPB bit value 1: Only compare data when MPB bit = 1 (ID frame) DCME Data Compare Match Enable Valid only in asynchronous mode, including multi-processor mode.
Page 552: Sptr : Serial Port Register
RA2L1 User's Manual 25. Serial Communications Interface (SCI) The write value must be 0 for all modes other than asynchronous mode. 25.2.31 SPTR : Serial Port Register Base address: SCIn = 0x4007_0000 + 0x0020 × n (n = 0 to 3, 9) Offset address: 0x1C Bit position: SPB2I...
Page 553: Serial Data Transfer Format
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Idle state (mark state) Serial data Start bit Transmit/receive data Parity bit Stop bit 1 bit 7, 8 or 9 bits 1 or 0 bit 1 or 2 bits One unit of transfer data (character or frame) Figure 25.2 Data format in asynchronous serial communications with 8-bit data, parity bit, and 2 stop bits 25.3.1...
Page 554: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined using the following formula: This represents the computed value. Renesas recommends a margin of 20% to 30% in system design. Note 1. In this example, the SEMR.ABCS bit is 0 and the SEMR.ABCSE is 0. When the ABCS bit is 1 and the ABCSE bit is 0, a frequency of 8 times the bit rate is used as a base clock, and receive data is sampled on the rising edge of the 4th pulse of the base clock.
Page 555: Clock
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 16 clock pulses 8 clock pulses Internal base clock Receive data (RXDn) Start bit Synchronization sampling timing Data sampling timing Figure 25.3 Receive data sampling timing in asynchronous mode 25.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the transfer clock of the SCI, based on the SMR.CM and SCR.CKE[1:0] settings.
Page 556: Cts And Rts Functions
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.3.5 CTS and RTS Functions The CTS function uses input on the CTSn_RTSn pin in transmission control. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing a low level on the CTSn_RTSn pin causes transmission to start. Driving the CTSn_RTSn pin high while transmission is in progress does not affect transmission of the current frame.
Page 557 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Note 3. This comparative target can select one length of 3 types: CMPD[6:0] with 7-bit length, CMPD[7:0] with 8-bit length, and CMPD[8:0] with 9-bit length. Note 4. Set the DCCR.DCME bit to 1 before receiving the start bit of the received frame that performs address matching. Data (ID1) Data (Data1) Start bit...
Page 558: Sci Initialization In Asynchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data (Data0) Data (ID1) Start bit Stop bit Start bit MPB Stop bit Start bit SCIn_AM SCI0_DCUF DCME DCMF flag SCIn_RXI interrupt flag (ICU.IELSRn.IR) RDRF flag DPER flag DFER flag The data by which MPB is 0 detects If compare mismatched, Not stored to RDR, if CDR mismatched certainly in SCI...
Page 559 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Note: Setting the SCR.RE bit to 0 initializes neither the ORER, FER, RDRF, RDF, PER, and DR flags in SSR/SSR_FIFO nor RDR and RDRHL. When the TE bit is set to 0, the TEND flag for the selected FIFO buffer is not initialized. Note: In non-FIFO mode, switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the generation of an SCIn_TXI interrupt request.
Page 560: Serial Data Transmission In Asynchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.26 Example flow of SCI initialization in asynchronous mode with FIFO selected (2 of 2) Step Name Description Set the FCR.TFRST and Set the FCR.TFRST and RFRST bits to 0. RFRST bits to 0 Set the I/O port functions Make I/O port settings to enable input and output functions as required for TXDn, RXDn, and SCKn pins.
Page 561 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data Start bit Parity bit Stop bit D7 0/1 1 D7 0/1 D0 D1 SCR.TE bit 1 frame SCIn_TXI interrupt flag (IELSRn.IR SSR.TEND flag SCIn_TXI interrupt Data written to TDR in SCIn_TXI interrupt Data written to TDR in Data written to TDR in request generated...
Page 562 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data Start bit Parity bit Stop bit Idle state 0 D0 D7 0/1 1 D7 0/1 D7 0/1 1 0 D0 D1 0 D0 (mark state) SCR.TE bit (TIE = 1) SCIn_TXI interrupt flag (IELSRn.IR (TIE = 0) SSR.TEND flag...
Page 563 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] [1] SCI Initialization: Initialization Set data transmission. After the SCR.TE bit is set to 1, 1 is output for a Start transmission frame, and transmission is enabled. [ 2 ] [2] Transmit data write to TDR by an SCIn_TXI interrupt request.
Page 564 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Transmit data in FTDRH, FTDRL Data Register Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits 7-bit transmit data — — — — — — — — — 8 bits 8-bit transmit data —...
Page 565: Serial Data Reception In Asynchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] SCI initialization: [ 1 ] Set data transmission. After the SCR.TE bit is set to 1, 1 is output for a frame, Start data transmission and transmission is enabled. [ 2 ] Transmit data write to FTDRL by an SCIn_TXI interrupt...
Page 566 RA2L1 User's Manual 25. Serial Communications Interface (SCI) cannot detect a parity or framing error as receive data are skipped (discarded) until the SCI detects a match between the receive data and comparison data (CDR.CMPD 4. If the SCI detects an address match, the DCCR.DCME bit is automatically cleared, the DCCR.DCMF flag becomes 1, and an SCIn_AM interrupt request is generated.
Page 567 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data Data Data Parity Stop Parity Stop Start bit Start bit Start bit Idle state RXDn pin (mark state) SCIn_RXI interrupt flag (IELSRn.IR SSR.FER flag SCIn_RXI interrupt RDR data read in SCIn_RXI request generated interrupt handling routine SCIn_ERI interrupt request...
Page 568 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] Initialization [ 1 ]SCI initialization: Start data reception Set data reception. [ 2 ][ 3 ]Receive error processing and break detection: If a receive error occurs, an SCIn_ERI interrupt is generated. The error [ 2 ] Read ORER, PER, and FER flags in SSR type is identified by reading the ORER, PER, and FER flags in SSR.
Page 569 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 3 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR. In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 570 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Initialization [ 1 ] Set data reception. [ 1-2 ] Address match cycle: Start of reception Set the DCCR.DCME bit to 1 to enable address matching. [ 1-3 ] Comparing receive data and data for comparison (CDR.CMPD): Compare receive data and data for comparison (CDR.CMPD).
Page 571 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1-5 ] Address match error processing DCCR.DFER = 1 Framing error processing DCCR.DPER = 1 Parity error processing [ 6 ] Clearing the error flag: Set the DCCR.DFER, and DPER flags to 0. [ 6 ] Set the error flag to 0.
Page 572 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 3 ] Error processing SSR.ORER = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR register. In combination with step [ 7 ]; this makes the correct reception of the next frame possible.
Page 573 RA2L1 User's Manual 25. Serial Communications Interface (SCI) SCI updates FER, PER, and receive data (RDAT[8:0]) in the FRDRL register with the next data. The flags RDF, ORER, and DR in the FRDRH register always reflect the associated flags in the SSR_FIFO register. Receive data in FRDRH, FRDRL Data Register...
Page 574 RA2L1 User's Manual 25. Serial Communications Interface (SCI) SCR.RIE bit in SCR is 1, an SCIn_RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to the FRDRL register in the SCIn_RXI interrupt handling routine, before an overrun error occurs.
Page 575 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 3 ] Error processing SSR_FIFO.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: The FRDRHL register is read and a space is made in the FRDRHL register.
Page 576 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Initialization Set data reception. [ 1-2 ] Address match cycle: Start of reception Set the DCCR.DCME bit to 1 to enable address matching. [ 1-3 ] Comparing received data and data for comparison (CDR.CMPD): Compare receive data and comparison data.
Page 577 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1-5 ] Address match error processing DCCR.DFER = 1 Framing error processing DCCR.DPER = 1 Parity error processing [ 1-6 ] Clearing the error flag: Set the DCCR.DFER, and DPER flags to 0. [ 1-6 ] Set the error flag to 0.
Page 578: Multi-Processor Communication Function
RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 3 ] [ 6 ] Processing in response to an overrun error: Read the FRDRHL register to empty it. Error processing [ 7 ] Transfer of the received data to the FRDRHL register stops when a break is detected.
Page 579 RA2L1 User's Manual 25. Serial Communications Interface (SCI) transmission cycle to specify the receiving station and a data transmission cycle to transmit data to the specified receiving station. The multi-processor bit is used to distinguish between the ID transmission cycle and the data transmission cycle: ●...
Page 580: Multi-Processor Serial Data Transmission
RA2L1 User's Manual 25. Serial Communications Interface (SCI) FIFO selected For data transmission, software must write data to FTDRHL.MPBT that corresponds to transmit data in FTDRHL.TDAT. For data reception, the multi-processor bit that is part of the receive data is written to FTDRHL.MPB and receive data is written to FRDRL.
Page 581 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After the SCR.TE bit is set to 1, 1 is output for a frame, and transmission is enabled. SCIn_TXI interrupt [ 2 ] [ 2 ]...
Page 582 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Transmit data in FTDRH, FTDRL Data Register Length Setting FTDRHL FTDRH FTDRL SCMR. SMR. CHR1 7 bits MPBT — — — — — — — — 7-bit transmit data 8 bits — —...
Page 583: Multi-Processor Serial Data Reception
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCI initialization: Start data transmission Set data transmission. After the SCR.TE bit is set to 1, 1 is output for a frame, and transmission is enabled. SCIn_TXI interrupt [ 2 ] [ 2 ]...
Page 584 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data (ID1) Data (Data1) Start bit Stop bit Start bit Stop bit Idle state (mark state) MPIE SCIn_RXI interrupt flag (IRn In ICU RDR value MPIE = 0 SCIn_RXI interrupt RDR data read in SCIn_RXI interrupt MPIE bit set to 1 again request (multi-processor...
Page 585 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] [ 1 ] SCI initialization: Initialization Set data reception. [ 2 ] ID reception cycle: Start data reception Set SCR.MPIE bit to 1 and wait for ID reception. [ 2 ] Set MPIE bit in SCR to 1 [ 3 ] SCI status confirmatIon and reception and comparison of ID:...
Page 586 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 5 ] Error processing SSR.ORER flag = 1 Overrun error processing [ 6 ] [ 6 ] Processing in response to an overrun error: Read the RDR . In combination with step [ 7 ], this will make correct reception of the next frame possible.
Page 587 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Receive data in FRDRH, FRDRL Data Register Length Setting FRDRHL FRDRH FRDRL SCMR. SMR. CHR1 7 bits — ORER 7-bit receive data 8 bits — ORER 8-bit receive data Don’t 9 bits —...
Page 588: Operation In Clock Synchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] SCI initialization: Set data reception. Initialization [ 1 ] [ 2 ] ID reception cycle: Set the SCR.MPIE bit to 1 and wait for ID reception. Start data reception [ 3 ] SCI status confirmation and reception and [ 2 ] Set MPIE bit in SCR to 1.
Page 589: Clock
RA2L1 User's Manual 25. Serial Communications Interface (SCI) transmission line holds the last bit as output state. When the SPMR.CKPH bit is 1 in slave mode, the transmission line holds the first bit output state. Within the SCI, the transmitter and receiver are independent units, enabling full-duplex communications by using a shared clock.
Page 590: Sci Initialization In Clock Synchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Non-FIFO selected when all of the following conditions are satisfied ● The value of the SCR.RE bit or the SCR.TE bit is 1 ● Neither transmission nor reception is in progress ● There is no received data available to be read when the SCR.RE bit is 1 ●...
Page 591: Serial Data Transmission In Clock Synchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.28 Example flow of SCI initialization in clock synchronous mode with non-FIFO selected (2 of 2) Step Name Description Set the SCR.TE or RE bit to 1, Set the SCR.TE or RE bit to 1. Also set the SCR.TIE and RIE bits. and set the SCR.TIE and RIE Setting the TE and RE bits allows TXDn and RXDn pins to be used.
Page 592 RA2L1 User's Manual 25. Serial Communications Interface (SCI) 3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when the clock output mode is specified and in synchronization with the input clock when the use of an external clock is specified. Output of the clock signal is suspended until the input CTS signal is low when the SPMR.CTSE bit is 1.
Page 593 RA2L1 User's Manual 25. Serial Communications Interface (SCI) CTSn_RTSn pin Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 SCR.TE bit SCIn_TXI interrupt flag (IELSRn.IR SSR.TEND flag SCIn_TXI interrupt SCIn_TXI interrupt SCIn_TXI interrupt request generated Request generated request generated Data written to TDR in Data written to TDR in...
Page 594 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] [ 1 ]SCI initialization: Initialization Set data transmission. Start transmission [ 2 ] [ 2 ]Writing transmit data write to TDR by an SCIn_TXI interrupt request: SCIn_TXI interrupt When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (SCIn_TXI) request is generated.
Page 595: Serial Data Reception In Clock Synchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 4. The SCI checks whether non-transmitted data remains in FTDRL on output of the stop bit. 5. When FTDRL is updated, the next transmit data is transferred from FTDRL to TSR and serial transmission of the next frame starts.
Page 596 RA2L1 User's Manual 25. Serial Communications Interface (SCI) 3. If an overrun error occurs, the SSR.ORER flag is set to 1. If the SCR.RIE bit is 1, an SCIn_ERI interrupt request is generated. Receive data is not transferred to the RDR register. 4.
Page 597 RA2L1 User's Manual 25. Serial Communications Interface (SCI) When a data reception is forced to terminate by a 0 write to the SCR.RE bit during operation, read the RDR register because received data that is not yet read might be left in the RDR register. Figure 25.43 shows an example flow of serial data reception.
Page 598 RA2L1 User's Manual 25. Serial Communications Interface (SCI) 2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock input or output, and stores the receive data in the RSR register. 3. If an overrun error occurs, the SSR_FIFO.ORER flag is set to 1. If the SCR.RIE bit is 1, an SCIn_ERI interrupt request is generated.
Page 599 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ]SCI initialization: Set the input port for pins to be used as RXDn pins. Start data reception [ 2 ][ 3 ]Receive error processing: If a receive error occurs, read the ORER flag in [ 2 ] Read ORER flag in SSR_FIFO...
Page 600: Simultaneous Serial Data Transmission And Reception In Clock Synchronous Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.5.6 Simultaneous Serial Data Transmission and Reception in Clock Synchronous Mode Non-FIFO selected Figure 25.45 shows an example flow of simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, use the following procedure for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode: 1.
Page 601 RA2L1 User's Manual 25. Serial Communications Interface (SCI) [ 1 ] Initialization [ 1 ]SCI initialization: The TXDn pin can act as the output pin for transmitted data and the RXDn pin can act as the input pin for received data at the same time. Start data transmission/reception SCIn_TXI interrupt [ 2 ]Transmit data write:...
Page 602 RA2L1 User's Manual 25. Serial Communications Interface (SCI) 1. Check that the SCI completes the reception. 2. Set the RIE and RE bits to 0. 3. Check that the receive error flags ORER in the SSR_FIFO register are 0, and then set the TIE, RIE, TE, and RE bits in the SCR register to 1 simultaneously by a single instruction.
Page 603: Operation In Smart Card Interface Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.6 Operation in Smart Card Interface Mode The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 25.6.1 Example Connection Figure 25.47...
Page 604 RA2L1 User's Manual 25. Serial Communications Interface (SCI) In normal transmission/reception Output from the transmitting station When a parity error occurs Output from the transmitting station Output from the receiving station Start bit D0 to D7: Data bits Parity bit Error signal Figure 25.48 Data formats in smart card interface mode...
Page 605: Block Transfer Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) (Z) state D7 D6 D5 D4 D3 D2 D1 D0 Dp Figure 25.50 Inverse convention with SDIR in SCMR = 1, SINV in SCMR = 1, and PM in SMR_SMCI = 1 25.6.3 Block Transfer Mode Block transfer mode differs from normal smart card interface mode as follows:...
Page 606: Sci Initialization (Smart Card Interface Mode)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 372 clocks 372 clocks 186 clocks 186 clocks 371 0 Internal base clock Start bit Receive data (RXDn) Synchronization sampling timing Data sampling timing Figure 25.51 Receive data sampling timing in smart card interface mode when the clock frequency is 372 times the bit rate 25.6.5 SCI Initialization (Smart Card Interface Mode)
Page 607: Serial Data Transmission (Except In Block Transfer Mode)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.30 Example flow of SCI initialization in smart card interface mode (2 of 2) Step Name Description Set SCMR.BCP2, SDIR, SINV Set the transmission or reception format in SCMR. Set SCMR.SMIF to 1 Set SEMR.BRME and Set SEMR.BRME and SEMR.RXDESEL to 0.
Page 608 RA2L1 User's Manual 25. Serial Communications Interface (SCI) (n + 1)-th transfer nth transfer frame Retransfer frame frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 D6 D7 Dp Ds D0 D1 D2 D3 D4 SCIn_TXI interrupt signal SSR_SMCI.FER flag/ SSR_SMCI.ERS flag...
Page 609: Serial Data Reception (Except In Block Transfer Mode)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Start Initialization Start data transmission SSR_SMCI.ERS flag = 0? Error processing SCIn_TXI interrupt Write transmit data to TDR Write all transmit data SSR_SMCI.ERS flag = 0? Error processing SCIn_TXI interrupt Set bits TIE, RIE, and TE in SCR_SMCI to 0 Figure 25.54 Example flow of smart card interface transmission...
Page 610 RA2L1 User's Manual 25. Serial Communications Interface (SCI) In reception, setting the RIE bit to 1 allows an SCIn_RXI interrupt request to be generated. The DTC is activated by an SCIn_RXI interrupt request if the SCIn_RXI interrupt request is previously specified as a source of DTC activation, allowing the transfer of receive data.
Page 611: Clock Output Control
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Start Initialization Start data reception SSR_SMCI.ORER = 0 and SSR_SMCI.PER = 0? Error processing SCIn_RXI interrupt Read data from RDR All data received? Set bits RIE and RE in SCR_SMCI to 0 Figure 25.56 Example flow of smart card interface reception 25.6.8...
Page 612: Operation In Simple Iic Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Base clock CKE[0] Case: GM = 0 SCKn Case: GM = 1 Figure 25.57 Clock Output timing 25.7 Operation in Simple IIC Mode Simple IIC mode format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device can specify a slave device as the partner for communications.
Page 613: Generation Of Start, Restart, And Stop Conditions
RA2L1 User's Manual 25. Serial Communications Interface (SCI) SSDAn D7-D1 D7-D1 D7-D1 SSCLn R/W# DATA DATA Figure 25.59 C bus timing when SLA is 7 bits ● S: Indicates a start condition, when the master device changes the level on the SDAn line from high to low while the SCLn line is high ●...
Page 614: Clock Synchronization
RA2L1 User's Manual 25. Serial Communications Interface (SCI) ● When a high level is detected on the SCLn line, the setup time for the stop condition is set as half of a bit period at the bit rate determined by the BRR setting ●...
Page 615: Sdan Output Delay
RA2L1 User's Manual 25. Serial Communications Interface (SCI) SSCLn output from the other device SSCLn line Internal SSCLn clock Clock driving transfer internally Counting of the period Counting of the period Counting of the period at high level starts. at high level starts. at low level starts.
Page 616: Operation In Master Transmission In Simple Iic Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Before making any changes to the operating mode or transfer format, be sure to set SCR to its initial value. In simple IIC mode, the open-drain setting for the communication ports should be made on the port side. Table 25.31 Example flow of SCI initialization in simple IIC mode Step Name...
Page 617 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Start condition Slave address (7 bits) Transmitted data Stop condition SSCLn SSDAn ACK/NACK SCIn_TXI interrupt flag (IELSRn.IR Acceptance of SCIn_TXI interrupt request STI interrupt flag Generation of SCIn_TXI interrupt request Generation of SCIn_TXI interrupt request (IELSRn.IR Generation of STI interrupt Acceptance of request...
Page 618 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] Initialization in simple IIC mode: For transmission, set the SCR.RIE to 0 to disable the RXI and ERI interrupts. Start of transmission Simultaneously set the SIMR3.IICSTAREQ bit to [ 2 ] Generate a start condition.
Page 619: Master Reception In Simple Iic Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.7.6 Master Reception in Simple IIC Mode Figure 25.66 shows an example operation in simple IIC mode master reception and Figure 25.67 shows an example flow of master reception. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts). In simple IIC mode, the transmit data empty interrupt (SCIn_TXI) is generated when communication of one frame is complete, unlike the SCIn_TXI interrupt request generation timing during clock synchronous transmission.
Page 620 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] Initialization in simple IIC mode: Set the RIE bit in SCR to 0. Start of reception [ 2 ] Generation of a start condition. Simultaneously set the SIMR3.IICSTAREQ bit [ 3 ] Writing to TDR: to 1 and the SIMR3.IICSCLS[1:0] and [ 2 ]...
Page 621: Operation In Simple Spi Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) 25.8 Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices and multiple slave devices. Using the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) and setting the SPMR.SSE bit to 1 places the SCI in simple SPI mode.
Page 622: Ss Function In Master Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.32 States of pins by mode and input level on SSn pin Mode Input on SSn pin State of MOSIn pin State of MISOn pin State of SCKn pin High level (transfer can Output for data Input for received data Master mode...
Page 623: Sci Initialization In Simple Spi Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) One unit of transfer data (character or frame) (1) When CKPH = 0 SSn pin (slave) SCKn pin (CKPOL = 0) SCKn pin (CKPOL = 1) MOSIn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4...
Page 624: Interrupt Sources
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Figure 25.70 shows an example where the PCLK is selected in the CKS[1:0] bits in SMR/SMR_SMCI, the BRR bit is set to 0, and the MDDR is set to 160 in asynchronous mode. In this example, the cycle of the base clock is evenly corrected (256/160) and the bit rate is also corrected (160/256).
Page 625 RA2L1 User's Manual 25. Serial Communications Interface (SCI) If the SCR.TIE bit is 1, an SCIn_TXI interrupt request is generated when transmit data is transferred from the TDR or TDRHL register to the TSR register. An SCIn_TXI interrupt request can also be generated by using a single instruction to set the SCR.TE and SCR.TIE bits to 1 at the same time.
Page 626: Interrupts In Smart Card Interface Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Table 25.33 SCI interrupt sources with non-FIFO selected (2 of 2) Interrupt Name Interrupt source Interrupt flag enable DTC activation SCIn_TEI (n = 0 to Transmit end SSR.TEND SCR.TEIE Not possible 3, 9) Note 1.
Page 627: Interrupts In Simple Iic Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) a source of DTC activation. If an error occurs, the error flag is set. Therefore, the DTC is not activated and an SCIn_ERI interrupt request is issued to the CPU instead. The error flag must be cleared. 25.10.5 Interrupts in Simple IIC Mode Table 25.36...
Page 628: Address Non-Match Event Output (Sci0_Dcuf)
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Receive data full event output (SCIn_RXI, n = 0 to 3, 9) ● Indicates that ACK is detected if the SIMR2.IICINTM bit is 0 in simple IIC mode ● Indicates that the 8th-bit SCLn falling edge is detected if the SIMR2.IICINTM bit is 1 in simple IIC mode ●...
Page 629: Usage Notes
RA2L1 User's Manual 25. Serial Communications Interface (SCI) In asynchronous mode, the noise cancellation function can be applied to the receive signal input to the RXDn pin. The receive level of the RXDn is taken in the flip-flop circuit of the noise filter on the base clock of asynchronous mode. In simple IIC mode, this function can be used for each input on SDAn and SCLn.
Page 630 RA2L1 User's Manual 25. Serial Communications Interface (SCI) To transmit data with a different transmission mode, initialize the SCI first. Figure 25.72 shows an example flow of transition to Software Standby mode during transmission. Figure 25.73 Figure 25.74 show the port pin states during transition to Software Standby mode. Before specifying the module-stop state or making a transition to Software Standby mode from the transmission mode using DTC transfer, stop the transmit operations (TE = 0).
Page 631 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data transmission [ 1 ] Data being transmitted is lost. Data can be normally [ 1 ] All data transmitted transmitted from the CPU by setting the TE bit in SCR/ SCR_SMCI to 1, reading SSR/SSR_FIFO/ SSR_SMCI, and writing in Software Standby mode.
Page 632 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Transition to Software Standby Software Standby mode mode canceled PmnPFS.PMR bit setting SPTR.SPB2IO SCR/SCR_SMCI.TE The level at transition to Software Standby mode is retained SCKn output pin The level before transition to TXDn output pin Port input/output High output...
Page 633 RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid [ 1 ] SCIn_RXI interrupt Read receive data in RDR SCR/SCR_SMCI.RE = 0 Transition to Software Standby mode [ 2 ] Setting for the module stop state is included [ 2 ] Cancel Software Standby mode Change operating mode...
Page 634: Break Detection And Processing
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Data reception [ 1 ] Received data is invalid [ 1 ] SCIn_RXI interrupt Read receive data in RDR SCR/SCR_SMCI.RE = 0 [ 2 ] Setting for the module-stop state is included Set the operation mode to cancel Software Standby mode Set a compared data to CDR...
Page 635: Mark State And Production Of Breaks
RA2L1 User's Manual 25. Serial Communications Interface (SCI) When the RXDn pin is set to 1 and the break ends, detecting the beginning of the start bit on the first falling edge of the RXDn pin allows the SCI to start the receiving operation. FIFO selected After a framing error is detected and when the SCI detects that continuous receive data is 0 for 1 frame, reception stops.
Page 636: Restrictions On Using Dtc
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Set t ≥ 1 PCLK cycle + data output delay time for the slave (t ) + setup time for the master (t Update TDR before bit [7] (D7) starts to transmit when continuous transmission is performed on the external clock Synchronous clock (external clock)
Page 637: Notes On Starting Transfer
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Reading data from RDR (FRDRHL) When using the DTC to read RDR and RDRHL, always set the receive data full interrupt (SCIn_RXI) as the activation source of the relevant SCI. 25.14.8 Notes on Starting Transfer At the point where transfer starts when the interrupt status flag (IELSRn.IR flag) in the ICU is 1, follow the procedure in this section to clear interrupt requests before permitting operations (by setting the SCR/SCR_SMCI.TE or SCR/ SCR_SMCI.RE bit to 1).
Page 638: Slave Mode
RA2L1 User's Manual 25. Serial Communications Interface (SCI) Slave mode ● Wait at least the following time from writing transmit data in the TDR register to the start of the external clock input. 1 PCLK cycle + data output delay for the slave (t ) + setup time for the master (t Also wait at least 5 PCLK cycles from the input of the low level on the SSn pin to the start of the external clock input.
Page 639: I2C Bus Interface (Iic)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) C Bus Interface (IIC) 26.1 Overview The I C bus interface (IIC) has 2 channels. The IIC module conforms with and provides a subset of the NXP I C (Inter- Integrated Circuit) bus interface functions. Table 26.1 lists the IIC specifications, Figure 26.1...
Page 640 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Table 26.1 IIC specifications (2 of 2) Parameter Specifications Event link function (output) ● Transfer error or event occurrence (arbitration-lost, NACK, timeout, start or restart condition, or stop condition) ● Receive data full, including matching with a slave address ●...
Page 641: Register Descriptions
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Power supply for pull-up SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 26.2 I/O pin connection to an external circuit (I C bus configuration example) The input level of the signals for IIC is CMOS when I C bus is selected (ICMR3.SMBS = 0), or TTL when SMBus is selected (ICMR3.SMBS = 1).
Page 642 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Symbol Function SCLI SCL Line Monitor 0: SCLn line is low 1: SCLn line is high SDAO SDA Output Control/Monitor 0: Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low 1: Read: IIC releases SDAn pin Write: IIC releases SDAn pin SCLO...
Page 643: Iccr2 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) ● I C Bus Control Register 2 (except ICCR2.BBSY bit) For the reset conditions for each register, see section 26.15. State of Registers When Issuing Each Condition. An internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states of the IIC without initializing the port settings and the control and setting registers of the IIC.
Page 644 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Symbol Function Stop Condition Issuance Request 0: Do not issue a stop condition request 1: Issue a stop condition request — This bit is read as 0. The write value should be 0. Transmit/Receive Mode 0: Receive mode 1: Transmit mode...
Page 645 RA2L1 User's Manual 26. I2C Bus Interface (IIC) SP bit (Stop Condition Issuance Request) The SP bit requests that a stop condition be issued in master mode. When this bit is set to 1, a stop condition is issued when the BBSY flag is set to 1 (bus busy state) and the MST bit is set to 1 (master mode).
Page 646: Icmr1 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Setting conditions] ● When a start condition is issued normally because of a start condition request (when a start condition is detected with the ST bit set to 1) ● When 1 is written to the MST bit with the MTWP bit in ICMR1 set to 1. [Clearing conditions] ●...
Page 647: Icmr2 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) BC[2:0] bits (Bit Counter) The BC[2:0] bits function as a counter indicating the number of bits remaining to be transferred on detection of a rising edge on the SCLn line. Although BC[2:0] are read/write bits, it is not required to access these bits under normal conditions. To write to these bits, specify the number of bits to be transferred plus one, for an additional acknowledge bit, between transferred frames when the SCLn line is at a low level.
Page 648: Icmr3 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) counts up in synchronization with the internal reference clock (IICφ) as a count source. For details on this function, see section 26.12.1. Timeout Function. TMOL bit (Timeout L Count Control) The TMOL bit enables or disables up-counting on the internal counter of the timeout function while the SCLn line is held low and the timeout function is enabled (ICFER.TMOE = 1).
Page 649 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Symbol Function WAIT Low-hold is released by reading ICDRR. 0: No wait (The SCLn line is not held low during the period between the 9th clock cycle and the 1st clock cycle.) 1: Wait (The SCLn line is held low during the period between the 9th clock cycle and the 1st clock cycle.) SMBS...
Page 650: Icfer : I C Bus Function Enable Register
RA2L1 User's Manual 26. I2C Bus Interface (IIC) WAIT bit (WAIT) The WAIT bit controls whether to force a low-hold between the ninth SCL clock cycle and the first SCL clock cycle, until the receive data buffer (ICDRR) is completely read each time single-byte data is received in receive mode. When the WAIT bit is 0, the receive operation continues without a low-hold between the ninth and the first SCL clock cycle.
Page 651: Icser : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) MALE bit (Master Arbitration-Lost Detection Enable) The MALE bit specifies whether to use the arbitration-lost detection function in master mode. Normally, set this bit to 1. NALE bit (NACK Transmission Arbitration-Lost Detection Enable) The NALE bit specifies whether to cause arbitration to be lost when ACK is detected during transmission of NACK in receive mode, for example when slaves with the same address exist on the bus or when two or more masters select the same slave device simultaneously with a different number of receive bytes.
Page 652: Icier : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Symbol Function DIDE Device-ID Address Detection Enable 0: Disable device-ID address detection 1: Enable device-ID address detection — This bit is read as 0. The write value should be 0. HOAE Host Address Enable 0: Disable host address detection 1: Enable host address detection SARyE bit (Slave Address Register y Enable) (y = 0 to 2)
Page 653 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Symbol Function ALIE Arbitration-Lost Interrupt Request Enable 0: Disable arbitration-lost interrupt (ALI) request 1: Enable arbitration-lost interrupt (ALI) request STIE Start Condition Detection Interrupt Request Enable 0: Disable start condition detection interrupt (STI) request 1: Enable start condition detection interrupt (STI) request SPIE Stop Condition Detection Interrupt Request Enable...
Page 654: Icsr1 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) 26.2.9 ICSR1 : I C Bus Status Register 1 Base address: IICn = 0x4005_3000 + 0x0100 × n (n = 0, 1) Offset address: 0x08 Bit position: Bit field: — — AAS2 AAS1 AAS0 Value after reset:...
Page 655 RA2L1 User's Manual 26. I2C Bus Interface (IIC) For 7-bit address format (SARUy.FS = 0): ● When the received slave address does not match the SVA[6:0] value in SARLy, with the SARyE bit in ICSER set to 1 (slave address y detection enabled). The AASy flag is set to 0 on the rising edge of the ninth SCL clock cycle in the frame.
Page 656: Icsr2 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) ● When the received slave address matches the host address (0001 000b), with the HOAE bit in ICSER set to 1 (host address detection enabled). The HOA flag is set to 1 on the rising edge of the ninth SCL clock cycle in the frame. [Clearing conditions] ●...
Page 657 RA2L1 User's Manual 26. I2C Bus Interface (IIC) ● When the SCLn line state remains unchanged for the period specified in the ICMR2.TMOH, TMOL, and TMOS bits while the ICFER.TMOE bit is 1 (timeout function enabled) in master or in slave mode and the received slave address matches.
Page 658 RA2L1 User's Manual 26. I2C Bus Interface (IIC) START flag (Start Condition Detection Flag) The START flag indicates whether a start or restart condition was detected. [Setting condition] ● When a start or restart condition is detected. [Clearing conditions] ● When 0 is written to the START flag after reading START = 1 ●...
Page 659: Icwur : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Clearing conditions] ● When 0 is written to the TEND flag after reading TEND = 1 ● When data is written to ICDRT ● When a stop condition is detected ● When 1 is written to the IICRST bit in ICCR1 to apply an IIC reset or an internal reset. TDRE flag (Transmit Data Empty Flag) The TDRE flag indicates whether the ICDRT contains transmit data.
Page 660: Icwur2 : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Table 26.5 Wakeup mode IICRST WUACK Operation mode Description Normal wakeup mode 1 ACK response on 9th SCL, and SCL low-hold after 9th SCL. Normal wakeup mode 2 No ACK response immediately and SCL low-hold between 8th and 9th SCL.
Page 661: Sarly : Slave Address Register Ly (Y = 0 To 2)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) WUASYF flag (Wakeup Function Asynchronous Operation Status Flag) The WUASYF flag can place the IIC in PCLKB asynchronous operation when the wakeup effective function is enabled (ICWUR.WUE = 1). [Setting condition] ● When the ICCR2.BBSY flag is 0, and the WUSEN bit is set to 0 with the ICWUR.WUE bit set to 1. [Clearing conditions] ●...
Page 662: Saruy : Slave Address Register Uy (Y = 0 To 2)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) SVA[6:0] bits (7-bit Address/10-bit Address Lower Bits) When the 7-bit address format is selected (SARUy.FS = 0), the SVA[6:0] bits function as a 7-bit address. When the 10- bit address format is selected (SARUy.FS = 1), these bits combine with the SVA0 bit to form the lower 8 bits of a 10-bit address.
Page 663: Icbrh : I C Bus Bit Rate High-Level Register
RA2L1 User's Manual 26. I2C Bus Interface (IIC) BRL[4:0] bits (Bit Rate Low-Level Period) The BRL[4:0] bits set the low-level period of the SCL clock. ICBRL counts the low-level period with the internal reference clock source (IICφ) specified by the CKS[2:0] bits in ICMR1. ICBRL also generates the data setup time for automatic SCL low-hold operation, see section 26.9.
Page 664: Icdrt : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Note 1. IICφ = PCLKB × division ratio Note 2. The SCLn line rise time (tr) and SCLn line fall time (tf) depend on the total bus line capacitance (Cb) and the pull-up resistor (Rp).
Page 665: Icdrs : I
RA2L1 User's Manual 26. I2C Bus Interface (IIC) If ICDRR receives the next receive data before the current data is read from ICDRR (while the RDRF flag in ICSR2 is 1), the IIC automatically holds the SCL clock low 1 cycle before the RDRF flag is set to 1 next. 26.2.19 ICDRS : I C Bus Shift Register...
Page 666: Initial Settings
RA2L1 User's Manual 26. I2C Bus Interface (IIC) SCLn 1 to 7 1 to 7 1 to 7 SDAn R/W# Data Data Figure 26.4 C bus timing when the SLA setting = 7 bits Start condition. The master device drives the SDAn line low from high while the SCLn line is high. SLA: Slave address, by which the master device selects a slave device.
Page 667: Master Transmit Operation
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Initial settings Set ICE in ICCR1 to 0 SCLn, SDAn pins not driven Set IICRST in ICCR1 to 1 IIC reset Set ICE in ICCR1 to 1 Internal reset, SCLn and SDAn pins in active state Set SARLy and SARUy Set slave address format and slave address Set ICSER...
Page 668 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition. For data transmission with an address in the 10-bit format, start by writing 11110b, the 2 higher-order bits of the slave address, and W to ICDRT as the first address transmission.
Page 669 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Master transmission [1] Process initial settings Initial settings ICCR2.BBSY = 0? [2] Check IIC bus occupation and issue a start condition ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte) [4] Check ACK and set transmit data Write data to ICDRT All data transmitted?
Page 670 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Automatic low-hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF DATA 1 DATA 2...
Page 671: Master Receive Operation
RA2L1 User's Manual 26. I2C Bus Interface (IIC) SCLn SDAn A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n DATA n-2 ICDRS DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR 0 (ACK)
Page 672 RA2L1 User's Manual 26. I2C Bus Interface (IIC) 5. After 1 byte of data is received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the 8th or 9th cycle of the SCL clock, as selected in the RDRFS bit in ICMR3. Reading ICDRR at this time produces the received data, and the RDRF flag is automatically set to 0 at the same time.
Page 673 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Master reception starts Initial settings (1) Process initial settings ICCR2.BBSY = 0? (2) Check IIC bus occupation and issue a start condition ICCR2.ST = 1 ICSR2.TDRE = 1? Write to the ICDRT register (3) Transmit the slave address followed by R and check ACK ICSR2.RDRF = 1?
Page 674 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Master reception Initial settings [1] Process initial settings ICCR2.BBSY = 0? [2] Check IIC- bus occupation and issue a start condition ICCR2.ST = 1 ICSR2.TDRE = 1? Write data to ICDRT [3] Transmit the slave address followed by R and check ACK ICSR2.RDRF = 1? ICSR2.NACKF = 0?
Page 675 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Automatic low hold Master transmit mode Master receive mode (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 676: Slave Transmit Operation
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Automatic low hold (WAIT) Automatic low hold (WAIT) SCLn SDAn NACK DATA n-2 DATA n-1 DATA n BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission ICDRT...
Page 677 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Slave transmission [1] Process initial settings Initial settings ICSR2.NACKF = 0? ICSR2.TDRE = 1? Write data to ICDRT [2], [3] Check ACK and set transmit data Checking of ACK not necessary immediately after address is received All data transmitted? ICSR2.TEND = 1?
Page 678: Slave Receive Operation
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF AASy...
Page 679 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Figure 26.18 shows an example of slave reception, and Figure 26.19 Figure 26.20 show the operation timing in slave reception. To set up and perform slave reception: 1. Initialize the IIC using the procedure in section 26.3.2.
Page 680: Scl Synchronization Circuit
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Automatic low hold (to prevent failure to receive data) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASy ICDRT XXXX (Initial value/last data for transmission)
Page 681: Sda Output Delay Function
RA2L1 User's Manual 26. I2C Bus Interface (IIC) driving the SCLn line, releasing the line, when it completes counting. The IIC repeats this process to generate the SCL clock. If multiple master devices are connected to the I C bus, a collision of SCL signals might arise because of contention with another master device.
Page 682: Digital Noise Filter Circuits
RA2L1 User's Manual 26. I2C Bus Interface (IIC) With this function, SDA output is delayed from the detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval during which the SCL clock is low. This approach helps prevent erroneous operation of communications devices, with the aim of satisfying the 300-ns minimum data-hold time requirement of the SMBus specification.
Page 683: Address Match Detection
RA2L1 User's Manual 26. I2C Bus Interface (IIC) required signals as noise. In such cases, it is possible to disable the digital noise-filter circuit by setting the ICFER.NFE bit to 0, and use only the analog noise filter circuit. Mismatch Match Com- parator...
Page 684 RA2L1 User's Manual 26. I2C Bus Interface (IIC) [7-bit address format: slave reception] SCLn SDAn 7-bit slave address Data (DATA 1) Data (DATA 2) BBSY Address match AASy Receive data (7-bit address) Receive data (DATA 1) TDRE RDRF Read ICDRR Read ICDRR (dummy read [7-bit address]) (DATA 1)
Page 685 RA2L1 User's Manual 26. I2C Bus Interface (IIC) [10-bit address format: slave reception] SCLn SDAn Upper 2 bits 10-bit slave address (lower 8 bits) Data BBSY Address match AASy Receive data (lower addresses) TDRE RDRF Read ICDRR (dummy read [lower addresses]) [10-bit address format: slave transmission] 1 to 8 SCLn...
Page 686: Detection Of General Call Address
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [When SAR0L = 7-bit address, SAR1L = 7-bit address, and SAR2 = 10-bit address (1)] 1 to 8 SCLn SDAn 7-bit slave address (SAR0L) R/W# DATA 7-bit slave address (SAR1L) R/W# BBSY Address mismatch AAS0 Address match...
Page 687: Device-Id Address Detection
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [General call address reception] SCLn SDAn Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2 General call address match (0000 000b + W) RDRF Read ICDRR Read ICDRR...
Page 688: Host Address Detection
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Device-ID reception] SCLn SDAn Address BBSY Device-ID match (1111 100b + W) Slave address match Device-ID match (1111 100b + R) AASy Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the device-ID ] SCLn...
Page 689: Wakeup Function
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Host address reception] SCLn SDAn Data (DATA 1) Data (DATA 2) BBSY AAS0 Receive data (7-bit address) Receive data (DATA 1) AAS1 AAS2 Host address match (0001 000b) RDRF Read ICDRR Read ICDRR (dummy read [7-bit address]) (DATA 1) Figure 26.29...
Page 690: Normal Wakeup Mode 1
RA2L1 User's Manual 26. I2C Bus Interface (IIC) ● Slave address 1 detection (valid when ICSER.SAR1E = 1) ● Slave address 2 detection (valid when ICSER.SAR2E = 1) Note 1. Only 7-bit address can be set. Set the FS bit in SARUy (y = 0 to 2) to 0. Precautions on the use of the wakeup function ●...
Page 691 RA2L1 User's Manual 26. I2C Bus Interface (IIC) IIC normal operation [1] Wait until I C bus is open and stay in standby state. BBSY = 0 MST = 0 & TRS = 0 (slave receive) [2] Negate internal reset (if asserted). IICRST = 0 (&...
Page 692 RA2L1 User's Manual 26. I2C Bus Interface (IIC) [1] Start PCLK to IIC due to other return factor (IRQn). [2] When the WUSEN bit is 0, slave mode can be selected WUE = 1 continuously. WUSEN = 0 [3] If the wakeup function is used continuously in slave mode, a wait for the wakeup interrupt request is generated.
Page 693: Normal Wakeup Mode 2
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Normal wakeup mode 1] As with normal operation, an ACK response when there is a match with its own slave address of the IIC, and SCL held low until the return. Before wakeup: Own slave ACK response. During wakeup: SCL held low on 9th SCL. After wakeup: Continue normal operation. Software Standby →...
Page 694 RA2L1 User's Manual 26. I2C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is free and stay in standby state MST = 0 & TRS = 0 (slave receive) IICRST = 0 (& ICE = 1) [2] Negate internal reset (if asserted) [3] Set up WUACK for the desired wakeup mode WUACK setting, WUIE = 1...
Page 695: Command Recovery Mode And Eep Response Mode (Special Wakeup Modes)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Note: Precautions on the use of the wakeup function. [Normal wakeup mode 2] IIC holds SCL low until wakeup on its own slave match. ACK response after wakeup. Before wakeup: Own slave – response. During wakeup: SCL held low between 8th and 9th SCL. After wakeup: Normal operation continues after own slave ACK response. Software Standby →...
Page 696 RA2L1 User's Manual 26. I2C Bus Interface (IIC) IIC normal operation BBSY = 0 [1] Wait until I C bus is open and stay in standby state. MST = 0 & TRS = 0 (slave receive) IICRST = 1 & ICE = 1 [2] Internal reset is asserted.
Page 697 RA2L1 User's Manual 26. I2C Bus Interface (IIC) [1] Start PCLK to IIC due to other return factor (IRQn). [2] When the WUSEN bit is 0, slave mode can be selected continuously. WUE = 1 [3] If the wakeup function is used continuously in slave mode, a wait for the wakeup interrupt request is generated.
Page 698: Automatic Low-Hold Function For Scl
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Command return mode and EEP response mode] Reply ACK/NACK in the period from wakeup start to wakeup processing. Reply ACK if own slave is specified again after IICRST release after wakeup. Before wakeup: Own slave ACK/NACK response. During wakeup: No SCL-low hold. After wakeup: Continue normal operation. Software Standby →...
Page 699: Nack Reception Transfer Suspension Function
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Automatic low-hold [Master transmit mode] (to prevent wrong Automatic low-hold (to prevent wrong transmission) Automatic low-hold (to prevent wrong transmission) transmission) SCLn SDAn Data (DATA 1) 7-bit slave address BBSY Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2) AASy...
Page 700: Function To Prevent Failure To Receive Data
RA2L1 User's Manual 26. I2C Bus Interface (IIC) [Master transmit mode] Automatic low-hold (to prevent wrong transmission) Bus free time (ICBRL) SCLn NACK SDAn 7-bit slave address 7-bit slave address Transfer suspended BBSY Transmit data Transmit data Transmit data (DATA 1) Transmit data (DATA 1) (7-bit address + W) (7-bit address + W)
Page 701: Arbitration-Lost Detection Functions
RA2L1 User's Manual 26. I2C Bus Interface (IIC) The RDRFS bit function is enabled for receive frames after a match with the IIC slave address, including the general call address and host address, is obtained in master or slave receive mode. Automatic low-hold [RDRFS = 0, WAIT = 0] (to prevent failure to receive data)
Page 702 RA2L1 User's Manual 26. I2C Bus Interface (IIC) A loss in arbitration of mastership is detected when the following conditions are met while the MALE bit in ICFER is 1 (master arbitration-lost detection enabled). [Master arbitration-lost conditions] ● Mismatching of the internal level for output on SDA and the level on the SDAn line after a start condition was issued by setting the ST bit in ICCR2 to 1 while the BBSY flag in ICCR2 is set to 0 (erroneous issuing of a start condition) ●...
Page 703: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Bus free (BBSY = 0) start condition issuance (ST = 1) error Bus busy (BBSY =1) start condition issuance (ST = 1) error SDA mismatch PCLK PCLK PCLK SCLn SCLn SCLn SDAn SDAn SDAn SCLn...
Page 704: Slave Arbitration-Lost Detection (Sale Bit)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) this occurs, master A cannot detect the ACK transmitted by master B and issues a stop condition. The stop condition issue conflicts with the SCL clock output of master B, which disrupts communication. When the IIC receives ACK during transmission of NACK, it detects a defeat in conflict with other master devices and causes arbitration to be lost.
Page 705: Start, Restart, And Stop Condition Issuing Function
RA2L1 User's Manual 26. I2C Bus Interface (IIC) 26.11 Start, Restart, and Stop Condition Issuing Function 26.11.1 Issuing a Start Condition The IIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition request is made, and the IIC issues a start condition when the BBSY flag in ICCR2 is 0 (bus free state).
Page 706 RA2L1 User's Manual 26. I2C Bus Interface (IIC) Figure 26.46 shows the operation timing when a restart condition is issued after the master transmission. [To issue a restart condition after the master transmission:] 1. Initialize the IIC using the procedure in section 26.3.2.
Page 707: Issuing A Stop Condition
RA2L1 User's Manual 26. I2C Bus Interface (IIC) 26.11.3 Issuing a Stop Condition The IIC issues a stop condition when the SP bit in ICCR2 is set to 1. When the SP bit is set to 1, a stop condition request is made, and the IIC issues a stop condition when the BBSY flag in ICCR2 is 1 (bus busy state) and the MST bit in ICCR2 is 1 (master mode).
Page 708: Extra Scl Clock Cycle Output Function
RA2L1 User's Manual 26. I2C Bus Interface (IIC) This timeout function is enabled when the ICFER.TMOE bit is 1. It detects a hung state when the SCLn line is stuck low or high during the following conditions: ● The bus is busy (ICCR2.BBSY flag is 1) in master mode (ICCR2.MST bit is 1) ●...
Page 709: Iic Reset And Internal Reset
RA2L1 User's Manual 26. I2C Bus Interface (IIC) single cycle of the SCL clock, the CLO bit is automatically set to 0. At this time, if ICCR2.BBSY = 1, the SCL pin goes low, and when ICCR2.BBSY = 0, the SCL pin goes high. After confirming that the CLO bit is 0 by software, write 1 to the CLO bit to output the additional clock continuously.
Page 710: Smbus Timeout Measurement
RA2L1 User's Manual 26. I2C Bus Interface (IIC) When transmitting the UDID (Unique Device Identifier), set the SALE bit in ICFER to 1 to enable the slave arbitration-lost detection function. 26.13.1 SMBus Timeout Measurement Measuring slave device timeout The following period (timeout interval: T ) must be measured for slave devices in SMBus communication: LOW: SEXT ●...
Page 711: Packet Error Code (Pec)
RA2L1 User's Manual 26. I2C Bus Interface (IIC) SMBus standard : Total clock low-level extended period (slave device) LOW:SEXT : Total clock low-level extended period (master device) LOW:MEXT Start Stop LOW:SEXT LOW:MEXT LOW:MEXT LOW:MEXT LOW:MEXT SCLn SDAn Data 7-bit slave address R/W# Data A/NA...
Page 712: Buffer Operation For Iicn_Txi And Iicn_Rxi Interrupts
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Table 26.10 Interrupt sources Symbol Interrupt source Interrupt flag DTC activation Interrupt condition Transfer error or event occurrence Not possible AL = 1, ALIE = 1 IICn_EEI NACKF NACKF = 1, NAKIE = 1 TMOF TMOF = 1, TMOIE = 1 START...
Page 713: Event Link Output
RA2L1 User's Manual 26. I2C Bus Interface (IIC) Table 26.11 Register states when issuing each condition (2 of 2) IIC reset Internal reset Start or restart Stop condition Registers Reset (ICE = 0, IICRST = 1) (ICE = 1, IICRST = 1) condition detection detection ICMR1...
Page 714: Usage Notes
RA2L1 User's Manual 26. I2C Bus Interface (IIC) The associated event link output signals are sent to other modules as event signals by the ELC when the interrupt source conditions are satisfied, regardless of the interrupt enable bit settings. For details on interrupt sources, see Table 26.10.
Page 715: Controller Area Network (Can) Module
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Controller Area Network (CAN) Module 27.1 Overview The Controller Area Network (CAN) module uses a message-based protocol to receive and transmit data between multiple slaves and masters in electromagnetically noisy applications. The module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO modes.
Page 716 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Table 27.1 CAN specifications (2 of 2) Parameter Specifications Software support unit Three software support units: ● Acceptance filter support ● Mailbox search support, including receive mailbox search, transmit mailbox search, and message lost search ●...
Page 717: Register Descriptions
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Performs filtering of received messages. MKR0 to MKR7 are used for the filtering process. ● Timer Used for the time stamp function. The timer value when a message is stored in the mailbox is written as the time stamp value.
Page 718 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function TSRC Time Stamp Counter Reset Command 0: Do not reset time stamp counter 1: Reset time stamp counter TSPS[1:0] Time Stamp Prescaler Select 0 0: Every 1-bit time 0 1: Every 2-bit time 1 0: Every 4-bit time 1 1: Every 8-bit time CANM[1:0]...
Page 719 RA2L1 User's Manual 27. Controller Area Network (CAN) Module TPM bit (Transmission Priority Mode Select) The TPM bit specifies the priority when transmitting messages. ID priority transmit mode or mailbox number transmit mode can be selected. All mailboxes are set for either ID priority transmission or mailbox number priority transmission. When TPM is 0, ID priority transmit mode is selected and transmission priority is arbitrated as defined in the ISO11898- 1 CAN specification.
Page 720: Bcr : Bit Configuration Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module RBOC bit (Forcible Return from Bus-Off) When the RBOC bit is set to 1 in the bus-off state, the CAN module forcibly exits the bus-off state. It is set to 0 automatically, and the error state changes from bus-off to error-active.
Page 721: Mkr[K] : Mask Register K (K = 0 To 7)
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function 25:16 BRP[9:0] Baud Rate Prescaler Select These bits set the frequency of the CAN communication clock (fCANCLK). 27:26 — These bits are read as 0. The write value should be 0. 31:28 TSEG1[3:0] Time Segment 1 Control...
Page 722: Fidcrk : Fifo Received Id Compare Register K (K = 0, 1)
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function 17:0 EID[17:0] Extended ID 0: Do not compare associated EID[17:0] bits 1: Compare associated EID[17:0] bits 28:18 SID[10:0] Standard ID 0: Do not compare associated SID[10:0] bits 1: Compare associated SID[10:0] bits 31:29 —...
Page 723: Mkivlr : Mask Invalid Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module SID[10:0] bits (Standard ID of data and remote frames) The SID[10:0] bits set the standard ID of data frames and remote frames. These bits are used to receive both standard ID and extended ID messages.
Page 724 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Table 27.4 for detailed on register addresses. Table 27.4 CANi mailbox memory mapping (i = 0) Address Message content CANn (n = 0) Memory mapping 0x4005_0200 + 1000 × n + 16 × j + 0 IDE, RTR, SID10 to SID6 0x4005_0200 + 1000 ×...
Page 725 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function ID Extension 0: Standard ID 1: Extended ID Note 1. If the mailbox receives a standard ID message, the EID bits in the mailbox are undefined. Note 2. The IDE bit is enabled when the CTLR.IDFM[1:0] bits are 10b (mixed ID mode). When the IDFM[1:0] bits are not 10b, only write 0 to IDE.
Page 726 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function DLC[3:0] Data Length Code 0x0: Data length = 0 byte 0x1: Data length = 1 byte 0x2: Data length = 2 bytes 0x3: Data length = 3 bytes 0x4: Data length = 4 bytes 0x5: Data length = 5 bytes 0x6: Data length = 6 bytes 0x7: Data length = 7 bytes...
Page 727: Mier : Mailbox Interrupt Enable Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function 15:8 TSH[7:0] Time Stamp Higher Byte The TSH[7:0] and TSL[7:0] bits store the counter value of the time stamp when received messages are stored in the mailbox. 27.2.7 MIER : Mailbox Interrupt Enable Register Base address: CAN0 = 0x4005_0000 Offset address: 0x42C Bit position:...
Page 728: Mctl_Tx[J] : Message Control Register For Transmit (J = 0 To 31)
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function MB24 Transmit FIFO Interrupt Enable 0: Disable interrupt 1: Enable interrupt MB25 Transmit FIFO Interrupt Generation Timing Control 0: Generate every time transmission completes 1: Generate when the transmit FIFO empties on transmission completion 27:26 —...
Page 729 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function TRMABT *1 *2 Transmission Abort Complete Flag 0: Transmission started, transmission abort failed because transmission completed, or transmission abort not requested 1: Transmission abort complete — This bit is read as 0. The write value should be 0. ONESHOT *2 *3 One-Shot Enable...
Page 730: Mctl_Rx[J] : Message Control Register For Receive (J = 0 To 31)
RA2L1 User's Manual 27. Controller Area Network (CAN) Module When the RECREQ bit is set to 1, the associated mailbox is configured for reception of a data or remote frame. When the RECREQ bit is set to 0, the associated mailbox is not configured for reception of a data or remote frame. Due to hardware protection, the RECREQ bit cannot be set to 0 through a software write during the following period: ●...
Page 731 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function — This bit is read as 0. The write value should be 0. RECREQ *2 *3 *4 *5 Receive Mailbox Request 0: Do not configure for reception 1: Configure for reception TRMREQ *2 *4 Transmit Mailbox Request...
Page 732: Rfcr : Receive Fifo Control Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module When setting the RECREQ bit to 1, do not set the TRMREQ bit to 1. To change the configuration of a mailbox from transmission to reception, first abort the transmission, then set the SENTDATA and TRMABT flags to 0 before changing to reception.
Page 733 RA2L1 User's Manual 27. Controller Area Network (CAN) Module When the RFE bit is set to 0, the receive FIFO is disabled for reception and becomes empty (RFEST bit = 1). Write 0 to the RFE bit simultaneously with the RFMLF flag setting. Do not set this bit to 1 in normal mailbox mode (MBM bit in CTLR = 0).
Page 734: Rfpcr : Receive Fifo Pointer Control Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Receive FIFO mailbox Frame 1 Frame 2 Frame 3 Frame 4 CAN bus Frame 1 Frame 2 Frame 3 Frame 4 Frame 1 Frame 2 Frame 3 Frame 4 Internal bus RFCR.RFEST flag RFCR.RFWST flag RFCR.RFFST bit...
Page 735: Tfcr : Transmit Fifo Control Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.2.13 TFCR : Transmit FIFO Control Register Base address: CAN0 = 0x4005_0000 Offset address: 0x84A Bit position: Bit field: TFEST TFFST — — TFUST[2:0] Value after reset: Symbol Function Transmit FIFO Enable 0: Disable transmit FIFO 1: Enable transmit FIFO TFUST[2:0]...
Page 736: Tfpcr : Transmit Fifo Pointer Control Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module TFEST bit (Transmit FIFO Empty Status) The TFEST bit is set to 1 (no message in transmit FIFO) when the number of unsent messages in the transmit FIFO is 0. The TFEST bit is set to 1 when transmission from the transmit FIFO is aborted. The TFEST bit is set to 0 (message in transmit FIFO) when the number of unsent messages in the transmit FIFO is not 0.
Page 737: Str : Status Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.2.15 STR : Status Register Base address: CAN0 = 0x4005_0000 Offset address: 0x842 Bit position: RECS TRMS RSTS FMLS NMLS Bit field: — BOST EPST SLPST HLTST TABST TFST RFST SDST NDST Value after reset: Symbol...
Page 738 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function — This bit is read as 0. NDST flag (NEWDATA Status Flag) The NDST flag is set to 1 when at least one NEWDATA flag in MCTL_RX[j] (j = 0 to 31) is 1, regardless of the value of MIER or MIER_FIFO.
Page 739: Msmr : Mailbox Search Mode Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module TRMST flag (Transmit Status Flag) The TRMST flag is set to 1 when the CAN module performs as a transmitter node or is in the bus-off state. The TRMST flag is set to 0 when the CAN module performs as a receiver node or is in the bus-idle state. RECST flag (Receive Status Flag) The RECST flag is set to 1 when the CAN module performs as a receiver node.
Page 740: Cssr : Channel Search Support Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function SEST Search Result Status 0: Search result found 1: No search result MBNST[4:0] bits (Search Result Mailbox Number Status) In all mailbox search modes, the MBNST[4:0] bits output the smallest found mailbox number. In receive mailbox search mode, transmit mailbox search mode, and message lost search mode, the value of the mailbox (the search result to be output) is updated under the following conditions: ●...
Page 741: Afsr : Acceptance Filter Support Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Address CAN0 0x4005_0851 CSSR 8/3 encoder CAN0 0x4005_0852 MSSR (1st read) (Search result: Channel no. 0 read) (2nd read) (Search result: Channel no. 3 read) (3rd read) (Search result: Channel no. 6 read) (4th read) (Search result: No corresponding channel no.) Figure 27.4...
Page 742: Eier : Error Interrupt Enable Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Address CAN0 When writing* 0x4005_0856 3/8 decoder CAN0 When reading 0x4005_0856 Column (bit) position in data table Row (byte offset) position in data table Note 1. Write the same value as the 16-bit unit data, including the SID[10:0] bits in MBj_ID (j = 0 to 31). Figure 27.5 Write and read operations in the AFSR register 27.2.20...
Page 743: Eifr : Error Interrupt Factor Judge Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module EWIE bit (Error-Warning Interrupt Enable) When the EWIE bit is 0, no error interrupt request occurs even if the EWIF flag in EIFR is 1. When the EWIE bit is 1, an error interrupt request is generated if the EWIF flag is set to 1.
Page 744 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Symbol Function ORIF Receive Overrun Detect Flag 0: No receive overrun detected 1: Receive overrun detected OLIF Overload Frame Transmission Detect Flag 0: No overload frame transmission detected 1: Overload frame transmission detected BLIF Bus Lock Detect Flag 0: No bus lock detected...
Page 745: Recr : Receive Error Count Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Table 27.7 Behavior of BOEIF and BORIF flags for each CTLR.BOM[1:0] setting BOM[1:0] bits BOEIF flag BORIF flag Set to 1 on entry to the bus-off state Sets to 1 on exit from the bus-off state Do not set to 1 Set to 1 on exit from the bus-off state Set to 1 if normal bus-off recovery occurs before the CANM[1:0] bits are set...
Page 746: Tecr : Transmit Error Count Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.2.23 TECR : Transmit Error Count Register Base address: CAN0 = 0x4005_0000 Offset address: 0x84F Bit position: Bit field: Value after reset: Symbol Function Transmit error count function. TECR increments or decrements the counter value based on the error status of the CAN module during transmission.
Page 747: Tsr : Time Stamp Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Note 2. To write 0 to the SEF, FEF, AEF, CEF, BE1F, BE0F, and ADEF bits, use the transfer (MOV) instruction to ensure that only the specified bit is set to 0 and the other bits are set to 1. Note 3.
Page 748: Tcr : Test Control Register
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.2.26 TCR : Test Control Register Base address: CAN0 = 0x4005_0000 Offset address: 0x858 Bit position: Bit field: — — — — — TSTM[1:0] TSTE Value after reset: Symbol Function TSTE CAN Test Mode Enable 0: Disable CAN test mode 1: Enable CAN test mode...
Page 749: Operation Modes
RA2L1 User's Manual 27. Controller Area Network (CAN) Module CAN transceiver CTXi CRXi CTXi CRXi (internal) (internal) Figure 27.7 Connection when self-test mode 0 is selected (i = 0) Self-test mode 1 (internal loopback) Self-test mode 1 is provided for self-test functions. In this mode, the protocol controller treats its transmitted messages as received messages and stores them into the receive mailbox.
Page 750: Can Reset Mode
RA2L1 User's Manual 27. Controller Area Network (CAN) Module CPU reset CANM[1:0] = 01b or 11b when SLPM = 0 CANM[1:0] = 00b CAN sleep mode CAN reset mode CAN operation mode CANM[1:0] SLPM = 1 = 01b, 11b CANM[1:0] CANM[1:0] = 10b = 00b when SLPM = 0...
Page 751: Can Halt Mode
RA2L1 User's Manual 27. Controller Area Network (CAN) Module ● MIER and MIER_FIFO ● EIER ● BCR ● CSSR ● ECSR (only the EDPM bit) ● MBj_ID, MBj_DL, MBj_Dm and MBj_TS ● MKRk ● FIDCR0 and FIDCR1 ● MKIVLR ● AFSR ●...
Page 752: Can Sleep Mode
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Note 4. If a CAN bus error or arbitration-lost occurs during transmission after CAN reset mode or CAN halt mode is requested, the CAN module transitions to the requested CAN mode. 27.3.3 CAN Sleep Mode CAN sleep mode reduces power consumption by stopping the clock supply to the CAN module.
Page 753: Can Operation Mode (Bus-Off State)
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.3.5 CAN Operation Mode (Bus-Off State) The CAN module enters the bus-off state based on the incrementing or decrementing rules for the transmit and error counters defined in the CAN specifications. The following cases apply when the CAN module is recovering from the bus-off state.
Page 754: Data Transfer Rate
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Bit time TSEG1 TSEG2 Sample point The range of each segment: Bit time = 8 Tq to 25 Tq SS = 1 Tq TSEG1 = 4 Tq to 16 Tq TSEG2 = 2 Tq to 8 Tq SJW = 1 Tq to 4 Tq Setting of TSEG1 and TSEG2: TSEG1 >...
Page 755 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Offset Address SID10 SID9 SID8 SID7 SID6 16 × j + 0 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 16 × j + 1 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 16 ×...
Page 756: Acceptance Filtering And Masking Functions
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Offset Address SID10 SID9 SID8 SID7 SID6 4 × n + 0 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 4 × n + 1 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 4 ×...
Page 757 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Normal mailbox mode FIFO mailbox mode Mailbox [0] Mailbox [0] MKR0 register MKR0 register Mailbox [3] Mailbox [3] Mailbox [4] Mailbox [4] MKR1 register MKR1 register Mailbox [7] Mailbox [7] Mailbox [8] Mailbox [8] MKR2 register MKR2 register...
Page 758: Reception And Transmission
RA2L1 User's Manual 27. Controller Area Network (CAN) Module 27.7 Reception and Transmission Table 27.10 lists the CAN communication mode settings. Table 27.10 Settings for CAN receive and transmit modes MCTL_TX[j].TRMREQ MCTL_TX[j].RECREQ MCTL_TX[j].ONESHOT MCTL_RX[j].TRMREQ MCTL_RX[j].RECREQ MCTL_RX[j].ONESHOT Mailbox communication mode Mailbox disabled or transmission being aborted Can be configured only when transmission or reception from a mailbox programmed in one-shot mode is aborted...
Page 759 RA2L1 User's Manual 27. Controller Area Network (CAN) Module Receive message in mailbox j Receive message in mailbox j IFS SOF CAN bus Acceptance filtering Acceptance filtering MCTL_RX[j] RECREQ MCTL_RX[j] INVALDATA MCTL_RX[j] NEWDATA MCTL_RX[j] MSGLOST CANi reception complete interrupt STR. RECST CANi error interrupt...
Page 760: Transmission
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Receive message in mailbox j Receive message in mailbox j IFS SOF CAN bus Acceptance filtering Acceptance filtering MCTL_RX[j] RECREQ MCTL_RX[j] INVALDATA MCTL_RX[j] NEWDATA MCTL_RX[j] MSGLOST CANi reception complete interrupt STR. RECST CANi error interrupt...
Page 761: Interrupts
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Transmission message in mailbox j Transmission message in mailbox k IFS SOF delimiter delimiter CAN bus Next transmission scan Next transmission scan Next transmission scan MCTL_TX[j] TRMREQ MCTL_TX[j] TRMACTIVE MCTL_TX[j] SENTDATA MCTL_TX[k] TRMREQ MCTL_TX[k]...
Page 762: Usage Notes
RA2L1 User's Manual 27. Controller Area Network (CAN) Module Eight interrupt sources are available for CANi error interrupts. Check EIFR to determine the interrupt sources: ● Bus error ● Error-warning ● Error-passive ● Bus-off entry ● Bus-off recovery ● Receive overrun ●...
Page 763: Serial Peripheral Interface (Spi)
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) 28.1 Overview The Serial Peripheral Interface (SPI) provides high-speed full-duplex synchronous serial communications with multiple processors and peripheral devices. Table 28.1 lists the SPI specifications, Figure 28.1 shows a block diagram, and Table 28.2 lists the I/O pins.
Page 764: Spi Block Diagram
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Table 28.1 SPI specifications (2 of 2) Parameter Specifications Other functions ● Switching between CMOS output and open-drain output ● SPI initialization function ● Loopback mode Module-stop function Module-stop state can be set to reduce power consumption. Note 1.
Page 765: Register Descriptions
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Table 28.2 SPI I/O pins Channel Pin name Description SPI0 RSPCKA Clock input/output pin MOSIA Master transmit data input/output MISOA Slave transmit data input/output SSLA0 Slave selection input/output SSLA1 to SSLA3 Output Slave selection output SPI1 RSPCKB...
Page 766 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPMS bit (SPI Mode Select) The SPMS bit selects SPI operation (4-wire method) or clock synchronous operation (3-wire method). The SSLn0 to SSLn3 pins are not used in clock synchronous operation. The RSPCKn, MOSIn, and MISOn pins handle communications.
Page 767: Sslp : Spi Slave Select Polarity Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.2.2 SSLP : SPI Slave Select Polarity Register Base address: SPIn = 0x4007_2000 + 0x0100 × n (n = 0, 1) Offset address: 0x01 Bit position: Bit field: — — — — SSL3P SSL2P SSL1P SSL0P Value after reset: Symbol...
Page 768: Spsr : Spi Status Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPLP2 bit (SPI Loopback 2) The SPLP2 bit selects the mode of the SPI pins. When this bit is set to 1, the SPI shuts off the path between the MISOn pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIn pin and the shift register if the SPCR.MSTR bit is 0.
Page 769: Multi-Master Mode
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) OVRF flag (Overrun Error Flag) The OVRF flag indicates the occurrence of an overrun error. In master mode (SPCR.MSTR bit = 1) and when the RSPCK clock auto-stop function is enabled (SPCR1.SCKASE bit = 1), overrun errors do not occur. This flag does not set to 1. For details, see section 28.3.8.1.
Page 770: Spdr/Spdr_Ha : Spi Data Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) PERF flag (Parity Error Flag) The PERF flag indicates the occurrence of a parity error. [Setting condition] ● When a serial transfer ends while the SPCR.TXMD bit is 0 and the SPCR2.SPPE bit is 1, triggering a parity error. [Clearing condition] ●...
Page 771: Bus Interface
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Symbol Function 31:0 SPI Data SPDR/SPDR_HA is the interface with the buffers that hold data for transmission and reception by the SPI. When accessing this register in words (the SPDCR.SPLW bit is 1), access SPDR. When accessing it in halfwords (the SPLW bit is 0), access SPDR_HA.
Page 772: Spbr : Spi Bit Rate Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPTX0 Note: SPDR = SPDR/SPDR_HA Figure 28.3 Configuration of SPDR/SPDR_HA for write access Even when the specified number of frames is written to the transmit buffer (SPTXn), the value of the buffer is not updated after completion of the writing and before generation of the next transmit buffer empty interrupt (when SPTEF is 0).
Page 773: Spdcr : Spi Data Control Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Symbol Function Bit rate SPBR sets the bit rate in master mode. When the SPI is in slave mode, the bit rate depends on the bit rate of the input clock, regardless of the settings in SPBR and the SPCMD0.BRDV[1:0] bits (bit rate division setting).
Page 774: Spckd : Spi Clock Delay Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPRDTD bit (SPI Receive/Transmit Data Select) The SPRDTD bit selects whether the SPDR/SPDR_HA reads values from the receive buffer or from the transmit buffer. If reading is from the transmit buffer, the last value written to SPDR/SPDR_HA register is read. Read the transmit buffer after an SPI transmit buffer empty interrupt is generated.
Page 775: Spnd : Spi Next-Access Delay Register
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Symbol Function SLNDL[2:0] SSL Negation Delay Setting 0 0 0: 1 RSPCK 0 0 1: 2 RSPCK 0 1 0: 3 RSPCK 0 1 1: 4 RSPCK 1 0 0: 5 RSPCK 1 0 1: 6 RSPCK 1 1 0: 7 RSPCK 1 1 1: 8 RSPCK...
Page 776 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Symbol Function SPPE Parity Enable 0: Do not add parity bit to transmit data and do not check parity bit of receive data 1: When SPCR.TXMD = 0: Add parity bit to transmit data and check parity bit of receive data When SPCR.TXMD = 1: Add parity bit to transmit data but do not check parity bit of receive data...
Page 777: Spcmd0 : Spi Command Register 0
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.2.12 SPCMD0 : SPI Command Register 0 Base address: SPIn = 0x4007_2000 + 0x0100 × n (n = 0, 1) Offset address: 0x10 Bit position: SCKD SLND SPND Bit field: LSBF SPB[3:0] —...
Page 778: Operation
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Set this register while the transmit buffer is empty (SPSR.SPTEF is 1 and data for the next transfer is not set), and before the setting of data to be transmitted when this register is referenced. If the contents of SPCMD0 are changed while the SPCR.SPE bit is 1, do not perform subsequent operations.
Page 779: Overview Of Spi Operation
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.3.1 Overview of SPI Operation The SPI is capable of synchronous serial transfers in the following modes: ● Slave mode (SPI operation) ● Single master mode (SPI operation) ● Multi-master mode (SPI operation) ●...
Page 780: Controlling The Spi Pins
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Table 28.4 Relationship between SPCR settings and SPI modes (2 of 2) Slave (clock Master (clock Slave (SPI Single-master Multi-master (SPI synchronous synchronous Mode operation) (SPI operation) operation) operation) operation) Underrun error detection Supported Not supported Not supported...
Page 781: Spi System Configuration Examples
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) The SPI in single-master mode (SPI operation) or multi-master mode (SPI operation) determines the MOSI signal values during the SSL negation period based on the MOIFE and MOIFV bit settings in SPPCR, as listed in Table 28.6.
Page 782 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPI master MCU (slave) SPCK RSPCKn MOSI MOSIn MISOn MISO SSLn0 SSLn1 SSLn2 SSLn3 Figure 28.6 Single-master/single-slave configuration example with the MCU as a slave and CPHA = 0 SPI master MCU (slave) SPCK RSPCK RSPCKn...
Page 783 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) MCU (master) SPI slave 0 RSPCKn RSPCK SPCK MOSIn MOSI MISOn MISO SSLn0 SSL0 SSLn1 SSL1 SSLn2 SSL2 SSLn3 SSL3 SPI slave 1 SPCK MOSI MISO SPI slave 2 SPCK MOSI MISO SPI slave 3 SPCK MOSI...
Page 784 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPI master MCU (slave X) SPCK RSPCK RSPCKn MOSI MOSI MOSIn MISO MISOn MISO SSLn0 SSLX SSL0 SSLn1 SSLY SSL1 SSLn2 SSL2 SSLn3 SSL3 MCU (slave Y) RSPCK RSPCKn MOSIn MOSI MISOn MISO SSLn0 SSL0...
Page 785 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) MCU (master Y) MCU (master X) RSPCKn RSPCKn RSPCK RSPCK MOSI MOSIn MOSI MOSIn MISO MISO MISOn MISOn SSL0 SSL0 SSLn0 SSLn0 SSL1 SSL1 SSLn1 SSLn1 SSL2 SSL2 SSLn2 SSLn2 SSL3 SSL3 SSLn3 SSLn3 Port Y...
Page 786: Data Formats
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) MCU (master) SPI slave RSPCKn RSPCK SPCK MOSIn MOSI MOSI MISOn MISO MISO SSLn0 SSL0 SSLn1 SSL1 SSLn2 SSL2 SSLn3 SSL3 Figure 28.11 Clock synchronous master/slave configuration example with the MCU as a master 28.3.3.7 Master and slave in clock synchronous mode with the MCU as a slave Figure 28.12...
Page 787 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) With parity disabled Dn-2 Dn-1 SPCMD0.SPB[3:0] With parity enabled Dn-2 Dn-1 SPCMD0.SPB[3:0] Figure 28.13 Data format with parity disabled and enabled 28.3.4.1 Operation when parity is disabled (SPCR2.SPPE = 0) When parity is disabled, data for transmission is copied to the shift register with no pre-processing. This section describes the connection between the SPI Data Register (SPDR/SPDR_HA) and the shift register in terms of the combination of MSB- or LSB-first order and data length.
Page 788: Serial Peripheral Interface (Spi)
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0 Input Copy Bit 31 Bit 0 Receive buffer Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 28.14...
Page 789 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 23 Bit 31 Bit 0 Copy Output Bit 23 Bit 31 Bit 0 Shift register Transfer end Shift register Bit 24 Bit 23 Bit 31 Bit 0 Input Copy Bit 24...
Page 790 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0 Input Copy Bit 31 Bit 0 Receive buffer Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 28.16...
Page 791 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Input Shift register Bit 31 Bit 0 Copy Bit 31 Bit 0 Receive buffer Note: Output = MOSI (master)/MISO (slave), input = MISO (master)/MOSI (slave) Figure 28.17...
Page 792 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0 Input Copy Bit 31 Bit 0 Receive buffer Note:...
Page 793 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 23 Bit 31 Bit 0 Parity added Copy Output Bit 23 Bit 31 Bit 0 Shift register Transfer end Shift register Bit 24 Bit 23 Bit 31 Bit 0 Input Copy...
Page 794 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Shift register Bit 31 Bit 0 Input Copy Bit 31...
Page 795: Transfer Formats
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transfer start Transmit buffer Bit 31 Bit 0 Parity calculated Parity added Bit 31 Bit 0 Copy Output Bit 31 Bit 0 Shift register Transfer end Input Shift register Bit 31 Bit 0 Copy Bit 31 Bit 0...
Page 796 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start Serial transfer period RSPCK cycle RSPCKn (CPOL = 0) RSPCKn (CPOL = 1) Sampling timing MOSIn MISOn SSLni Figure 28.22 SPI transfer format when CPHA = 0 28.3.5.2 When CPHA = 1 Figure 28.23 shows an example transfer format for the serial transfer of 8-bit data when the SPCMD0.CPHA bit is 1.
Page 797: Data Transfer Modes
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start Serial transfer period RSPCK cycle RSPCKn (CPOL = 0) RSPCKn (CPOL = 1) Sampling timing MOSIn MISOn SSLni Figure 28.23 SPI transfer format when CPHA = 1 28.3.6 Data Transfer Modes Full-duplex synchronous serial communications or transmit operations can only be selected in the Communications Operating Mode Select bit (SPCR.TXMD).
Page 798: Transmit Buffer Empty And Receive Buffer Full Interrupts
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 1. When a serial transfer ends with the receive buffer of SPDR_HA empty, the SPI generates a receive buffer full interrupt request (SPIi_SPRI), the SPI sets the SPSR.SPRF flag to 1, and copies the received data in the shift register to the receive buffer.
Page 799 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) The numbers given for RSPCKn in the waveform represent the number of RSPCK cycles, such as the number of transferred bits. SPDR_HA access RSPCKn (CPHA = 0, CPOL = 0) Transmit buffer state Empty Full Empty...
Page 800: Error Detection
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) when received data is not copied from the shift register to the receive buffer in an overrun error status, on completion of the serial transfer, the SPI determines that the shift register is empty, so data transfer from the transmit buffer to the shift register is enabled.
Page 801 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Table 28.7 Relationship between non-normal transfer operations and SPI error detection (2 of 2) Operation Occurrence condition SPI operation Error detection The SSLn0 input signal is negated during serial ● Serial transfer is suspended Mode fault error transfer in slave mode.
Page 802 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 3. If the serial transfer ends with the OVRF flag set to 1 (overrun error occurred), the SPI does not copy data in the shift register to the receive buffer (the SPRF flag does not set to 1). A receive buffer full interrupt is not generated. Even when the SPPE bit is 1, parity errors are not detected.
Page 803: Parity Errors
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start Start Serial transfer period Serial transfer period SPDR_HA access RSPCK RSPCK cycle cycle Clock is stopped RSPCKn (CPOL = 0) RSPCKn (CPOL = 1) Sampling timing MOSIn MISOn SSLni Receive buffer Empty Full Full...
Page 804 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) SPSR access RSPCKn (CPHA = 1, CPOL = 0) PERF OVRF Figure 28.31 Operation example of the PERF flag The operation of the flags at timings (1) to (3) in Figure 28.31 is as follows: 1.
Page 805: Initializing The Spi
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) When the MODF flag is 1, writing 1 to the SPE bit is ignored by the SPI. To enable the SPI function after the detection of an underrun error, the MODF flag must be set to 0. 28.3.9 Initializing the SPI If 0 is written to the SPCR.SPE bit or if the SPI sets the SPE bit to 0 because it detected a mode fault error or an underrun...
Page 806 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) RSPCK delay (t1) The RSPCK delay value of the SPI in master mode depends on the SPCMD0.SCKDEN bit setting and the SPCKD.SCKDL[2:0] bits setting. The SPI determines an RSPCK delay using the SPCMD0.SCKDEN bit and SPCKD.SCKDL[2:0] bits, as listed in Table 28.8.
Page 807: Initialization Flow
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Table 28.10 Relationship between the SPCMDm.SPNDEN bit, SPND.SPNDL[2:0] bits, and next-access delay (2 of 2) SPCMD0.SPNDEN bit SPND.SPNDL[2:0] bits Next-access delay 000b 1 RSPCK + 2 PCLKB 001b 2 RSPCK + 2 PCLKB 010b 3 RSPCK + 2 PCLKB 011b...
Page 808 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start of initialization in master mode Set SPI Slave Select Polarity Register • Set polarity of SSL signal (SSLP) • Set output mode Set SPI Pin Control Register (SPPCR) • Set MOSI signal value when transfer is in idle state Set SPI Bit Rate Register (SPBR) •...
Page 809 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Transmit processing flow When transmitting data, with the SPIi_SPII interrupt enabled, the CPU is notified of the completion of data transmission after the last data write for transmission. Transmission processing Start transmission Pre-transfer processing processing End of initial settings...
Page 810 When a mode fault error is generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. Then Renesas recommends clearing the SPCR.SPE bit to stop operations for errors other than mode fault errors. When an error is detected using an interrupt, clear the ICU.IELSRn.IR flag in the error processing routine. If this is not done, the ICU.IELSRn.IR flag might continue to indicate the SPIi_SPTI or SPIi_SPRI interrupt request.
Page 811: Slave Mode Operation
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Error processing Pre-transfer processing Start error processing End of initial settings SPIi_SPEI interrupt? SPSR.MODF/OVRF/PERF/UDRF Clear SPSR.MODF, OVRF, = 1? [1] Clear error sources. PERF, and UDRF flags Set SPCR2.SPIIE = 0 [2] Disable SPIi_SPII interrupts. SPSR.MODF = 0? [3] Set the SPE bit to enabled.
Page 812: Burst Transfer
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) The final sampling timing changes depending on the bit length of transfer data. In slave mode, the SPI data length is determined by the SPCMD0.SPB[3:0] bits setting. The polarity of the SSLn0 input signal is determined by the SSLP.SSL0P bit setting.
Page 813 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start of initialization in slave mode Set SPI Slave Select Polarity • Set polarity of SSLn0 input signal Register (SSLP) Set SPI Data Control Register (SPDCR) • Set parity function Set SPI Control Register 2 (SPCR2) •...
Page 814 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Software processing flow Transmit processing flow Pre-transfer processing Processing for transmission Start processing End of initial settings for transmission Clear SPSR.MODF, OVRF, [1] Clear error sources SPIi_SPTI interrupt? UDRF, and PERF flags SPSR.SPTEF = 1? [2] Disable SPIi_SPII interrupts Set SPCR2.SPIIE = 0...
Page 815 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Pre-transfer processing Processing for reception Start processing End of initial settings for reception Clear the SPSR.MODF, OVRF, SPIi_SPRI interrupt? [1] Clear error sources. UDRF, and PERF flags SPSR.SPRF = 1? [2] Disable SPIi_SPII interrupts. 　 Set SPCR2.SPIIE = 0 Read receive data from SPDR register...
Page 816: Clock Synchronous Operation
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Error processing Pre-transfer processing Start error processing End of initial settings SPIi_SPEI interrupt? Clear SPSR.MODF, OVRF, SPSR.MODF/OVRF/PERF/UDRF [1] Clear error sources. UDRF, and PERF flags = 1? Set SPCR2.SPIIE = 0 [2] Disable SPIi_SPII interrupts. SPSR.MODF = 0? [3] Set the SPE bit to enabled.
Page 817 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Terminating serial transfer The SPI terminates the serial transfer after transmitting an RSPCKn edge corresponding to the sampling timing. If free space is available in the receive buffer (the SPSR.SPRF flag is 0), on termination of serial transfer, the SPI copies data from the shift register to the receive buffer of the SPI Data Register (SPDR/SPDR_HA).
Page 818 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start of initialization in master mode Set SPI Pin Control Register • Set MOSI signal value when transfer is in idle state (SPPCR) Set SPI Bit Rate Register (SPBR) • Set transfer bit rate Set SPI Data Control Register (SPDCR) Set SPI Clock Delay Register...
Page 819 RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.3.11.2 Slave mode operation Starting serial transfer When the SPCR.SPMS bit is 1, the first RSPCKn edge triggers the start of a serial transfer in the SPI, and the SPI drives the MISOn output signal.
Page 820: Loopback Mode
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Software processing flow Software processing during clock synchronous slave operation is the same as that for SPI slave operation. For details, see (6)Software processing flow. Mode fault errors do not occur in clock synchronous mode. 28.3.12 Loopback Mode When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the SPI shuts off the path between the MISOn pin and the...
Page 821: Interrupt Sources
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) Start of self-diagnosis of parity circuit Select full-duplex synchronous serial communications (SPCR.TXMD = 0) Enable parity circuit self-diagnosis function (SPCR2.PTE = 1) Enable parity function (SPCR2.SPPE = 1) Select loopback mode (SPPCR.SPLP2 = 1) Parity error occurred Add correct parity bit to transmit data and transfer it...
Page 822: Event Link Controller Event Output
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) ● Receive buffer full ● Transmit buffer empty ● SPI error (mode-fault, underrun, overrun, or parity error) ● SPI idle ● Transmission-complete The DTC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer. Because the vector address for the SPIi_SPEI (SPI error interrupt) is allocated to interrupt requests on mode-fault, underrun, overrun, and parity errors, the actual interrupt source must be determined from the flags.
Page 823: Transmit Buffer Empty Event Output
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.4.2 Transmit Buffer Empty Event Output This event signal is output when data for transmission is transferred from the transmit buffer to the shift register and when the value of the SPE bit changes from 0 to 1. 28.4.3 Mode-Fault, Underrun, Overrun, or Parity Error Event Output This event signal is output when mode-fault, underrun, overrun, or parity error is detected.
Page 824: Usage Notes
RA2L1 User's Manual 28. Serial Peripheral Interface (SPI) 28.5 Usage Notes 28.5.1 Settings for the Module-Stop State The Module Stop Control Register B (MSTPCRB) can enable or disable the SPI operation. The SPI is initially stopped after reset. Releasing the module-stop state enables access to the registers. For details on the Module Stop Control Register B, see section 10, Low Power Modes.
Page 825: Cyclic Redundancy Check (Crc) Calculator
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator Cyclic Redundancy Check (CRC) Calculator 29.1 Overview The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the data. The bit order of CRC calculation results can be switched for LSB-first or MSB-first communication. Additionally, various CRC-generation polynomials are available.
Page 826: Register Descriptions
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator Data bus CRCDOR/ CRCCR0 CRCDOR_HA/ CRC snoop block CRCDOR_BY CRCSAR CRC code generation circuit Control signal CRCDIR/ CRCDIR_BY CRCCR1 Address bus Figure 29.1 CRC calculator block diagram 29.2 Register Descriptions 29.2.1 CRCCR0 : CRC Control Register 0 Base address: CRC = 0x4007_4000 Offset address: 0x00...
Page 827: Crccr1 : Crc Control Register 1
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator GPS[2:0] bits (CRC Generating Polynomial Switching) The GPS[2:0] bits select the CRC generating polynomial. LMS bit (CRC Calculation Switching) The LMS bit selects the bit order of generated CRC code. Transmit the lower byte of the CRC code first for LSB-first communication and the upper byte first for MSB-first communication.
Page 828: Crcdor/Crcdor_Ha/Crcdor_By : Crc Data Output Register
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator 29.2.4 CRCDOR/CRCDOR_HA/CRCDOR_BY : CRC Data Output Register Base address: CRC = 0x4007_4000 Offset address: 0x08 Bit position: 31 Bit field: Value after reset: Symbol Function 31:0 CRC output data The CRCDOR register is a 32-bit read/write register for CRC-32 or CRC-32C calculation. The CRCDOR_HA (CRCDOR[31:16], address: 0x4007_4008) register is a 16-bit read/write register for CRC-16 or CRC-CCITT calculation.
Page 829 RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator The following examples show CRC code generation for input data (0xF0) using the 16-bit CRC-CCITT generating polynomial (X + 1). In these examples, the value of the CRC Data Output Register (CRCDOR_HA) is cleared before CRC calculation.
Page 830 RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator 1. Write 0xC3 to CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY 2. Write 0xF0 to the CRC Data Input Register (CRCDIR_BY) CRCDIR_BY CRCDOR_HA CRC code generation 3. Read the calculation result in the CRC Data Output Register (CRCDOR_HA) CRC code = 0xEF1F 4.
Page 831 RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator 1. 8-bit serial reception (LSB-first) CRC code Data Input 2. Write 0x83 to the CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY 3. Write 0xF0 to the CRC Data Input Register (CRCDIR_BY) CRCDIR_BY CRCDOR_HA CRC code generation...
Page 832: Crc Snoop Function
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator 1. 8-bit serial reception (MSB-first) CRC code Data Input 2. Write 0xC3 to CRC Control Register 0 (CRCCR0) CRCCR0 CRCDOR_HA Clear CRCDOR/CRCDOR_HA/CRCDOR_BY 3. Write 0xF0 to the CRC Data Input Register (CRCDIR_BY) CRCDIR_BY CRCDOR_HA CRC code generation...
Page 833: Usage Notes
RA2L1 User's Manual 29. Cyclic Redundancy Check (CRC) Calculator When the CRC code is generated by using CRC-8, CRC-16, and CRC-CCITT generating polynomial, the target register is accessed in 1 byte (8 bits). Similarly, when the CRC code is generated by using CRC-32 and CRC-32C generating polynomial, the target register is accessed in words (32 bits).
Page 834: Bit A/D Converter (Adc12)
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 12-Bit A/D Converter (ADC12) 30.1 Overview The MCU includes one 12-bit successive approximation A/D converter (ADC12) unit. Up to 19 analog input channels, temperature sensor output, internal reference voltage, and CTSU TSCAP voltage, can be selected for conversion. The ADC12 supports the following operating modes: ●...
Page 835 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.1 ADC12 specifications (2 of 3) Parameter Specifications ● 19 registers for analog input Data registers ● One register for A/D-converted data duplication in double trigger mode ● Two registers for A/D-converted data duplication during extended operation in double trigger mode ●...
Page 836 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.1 ADC12 specifications (3 of 3) Parameter Specifications Interrupt sources ● In single scan mode (double trigger deselected), an A/D scan end interrupt request (ADC120_ADI) and ELC event signal (ADC120_ADI) can be generated on completion of single scan. –...
Page 837 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Bus interface AVCC0 AVSS0 A/D data register A/D control register Power generator (for self-diagnosis) Interrupt requests Internal reference voltage (ADC120_ADI,ADC120_GBADI, Temperature sensor output ADC120_CMPAI, ADC120_CMPBI) CTSU TSCAP voltage Event output to the ELC AN020 Comparator (ADC120_ADI,ADC120_WCMPM,...
Page 838: Register Descriptions
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.2 Register Descriptions 30.2.1 ADDRn : A/D Data Registers n Base address: ADC120 = 0x4005_C000 Offset address: 0x020 + 0x2 × n (n = 00 to 14, 17 to 20) Bit position: Bit field: ADDRn [15:0] Value after reset:...
Page 839: Addbldr : A/D Data Duplexing Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.5 Example of bit assignment for 12-bit accuracy when A/D-converted value addition mode is selected Accuracy Right-justified When 16 Added Value 15 to 0: data with 12-bit conversion times 16-bit sum of A/D conversion results accuracy is specified When 1, 2, 3, or...
Page 840: Addbldrn : A/D Data Duplexing Register N (N = A, B)
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) specific channel. The value is stored in the A/D data register based on the setting of the A/D Data Register Format Select bit in the same way as for normal A/D conversion. When A/D-converted value addition mode is selected For 12-bit accuracy, 1, 2, 3, or 4 times can be selected in the A/D-converted value addition mode.
Page 841: Adtsdr : A/D Temperature Sensor Data Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) When A/D-converted value addition/average mode is not selected Table 30.8 shows the example of bit assignment for 12-bit accuracy. Table 30.8 Example of bit assignment for 12-bit accuracy Accuracy Right-justified data with These bits are read as 0.
Page 842 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function 15:0 ADTSDR [15:0] Converted Value 15 to 0 Functions vary depending on the selected mode and accuracy. See Table 30.10 Table 30.11. ADTSDR register is a 16-bit read-only register to store A/D conversion result of the temperature sensor output. The following conditions determine the formats for data in the A/D data registers: ●...
Page 843: Adocdr : A/D Internal Reference Voltage Data Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.11 Example of bit assignment for 12-bit accuracy when A/D-converted value addition mode is selected (2 of 2) Accuracy Left-justified data When 16 Added Value 15 to 0: with 12-bit conversion times 16-bit sum of A/D conversion results accuracy is specified...
Page 844: Adctdr : A/D Ctsu Tscap Voltage Data Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) For 12-bit accuracy, 16 times can also be selected in the A/D-converted value addition mode. In A/D-converted value addition mode, this register indicates the value that is obtained by adding A/D-converted values on a specific channel. A/D conversion results are stored in the A/D data register as a 4-bit-extended value of the specified conversion accuracy.
Page 845: Adrd : A/D Self-Diagnosis Data Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.14 Example of bit assignment for 12-bit accuracy (2 of 2) Accuracy Left-justified data with 12- Converted Value 11 to 0: These bits are read as 0. bit accuracy 12-bit A/D-converted value When A/D-converted value average mode is selected A/D-converted value average mode can be selected when 2 or 4 times is specified in the A/D-converted value addition mode.
Page 846: Adcsr : A/D Control Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function 15:14 DIAGST[1:0] Self-Diagnosis Status 0 0: Self-diagnosis not executed after power-on. 0 1: Self-diagnosis was executed using the 0 V voltage. 1 0: Self-diagnosis was executed using the reference power supply voltage ×...
Page 847 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function EXTRG Trigger Select 0: Start A/D conversion by the synchronous trigger (ELC). 1: Start A/D conversion by the asynchronous trigger (ADTRG0). TRGE Trigger Start Enable 0: Disable A/D conversion to be started by the synchronous or asynchronous trigger 1: Enable A/D conversion to be started by the synchronous or asynchronous trigger ADHSC A/D Conversion Mode Select...
Page 848 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.18 Relationship between DBLANS bit Settings and Double-trigger Enabled Channels (2 of 2) DBLANS45:0] Duplication channel 0x06 AN006 0x07 AN007 0x08 AN008 0x09 AN009 0x0A AN010 0x0B AN011 0x0C AN012 0x0D AN013 0x0E AN014...
Page 849 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) In single scan mode, A/D conversion is performed for the analog inputs of the channels selected in the ADANSA0 and ADANSA1 registers, in ascending order of channel number (CTSU TSCAP voltage can be regarded as AN016). When 1 cycle of A/D conversion completes for all the selected channels, the scan conversion stops.
Page 850: Adansa0 : A/D Channel Select Register A0
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ● The asynchronous trigger is detected when the ADCSR.TRGE and ADCSR.EXTRG bits are set to 1 and the ADSTRGR.TRSA[5:0] bits are set to 0x00. ● When group priority operation mode is enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit = 1), the ADGSPCR.GBRP bit is set to 1, and each time A/D conversion on the group with the lowest priority is started.
Page 851: Adansa1 : A/D Channel Select Register A1
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.2.10 ADANSA1 : A/D Channel Select Register A1 Base address: ADC120 = 0x4005_C000 Offset address: 0x006 Bit position: ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA ANSA Bit field:...
Page 852: Adansb1 : A/D Channel Select Register B1
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ANSBn bits (A/D Conversion Channels Select) The ADANSB0 register selects any combination of analog input channels in group B for A/D conversion when group scan mode is selected. The ADANSB0 register is used for group scan mode only and not for any other modes. Do not select channels specified in group A as selected in the ADANSA0 and ADANSA1 registers or the ADCSR.DBLANS[4:0] bits in double trigger mode.
Page 853: Adads1 : A/D-Converted Value Addition/Average Channel Select Register 1
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ADSn bits (A/D-Converted Value Addition/Average Channel Select) The ADSn bits determine which A/D-converted channels are subject to A/D-converted value addition/averaging. When an ADSn bit associated with a channel selected for A/D conversion is set to 1, A/D conversion of the analog input of the respective channel is performed successively 1, 2, 3, 4, or 16 times, as specified in the ADC[2:0] bits in the ADADC register.
Page 854: Adadc : A/D-Converted Value Addition/Average Count Select Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function 15:0 ADSn A/D-Converted Value Addition/Average Channel Select Bit 15 (ADS31) is associated with AN031 and bit 1 (ADS17) is associated with AN017. Bit 0 (ADS16) is associated with CTSU TSCAP 0: Do not select associated input channel.
Page 855: Adcer : A/D Control Extended Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.20 Settable combinations of ADADC register Average mode select A/D Conversion Accuracy Conversion time (AVEE) (ADCER.ADPRC[1:0]) 1-time 2-times 3-times 4-times 16-times 1'b0 12-bit (ADPRC[1:0] = 00b) ✓ ✓ ✓ ✓ ✓ 1'b1 —...
Page 856: Adstrgr : A/D Conversion Start Trigger Select Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ACE bit (A/D Data Register Automatic Clearing Enable) The ACE bit enables or disables automatic clearing (all 0) of the ADDRy, ADRD, ADDBLDR, ADDBLDRA, ADDBLDRB, ADTSDR, or ADOCDR register after any of these registers is read by the CPU or DTC. Automatic clearing of the A/D data registers enables detection of failures that are not updated in the A/D data registers.
Page 857 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function 13:8 TRSA[5:0] A/D Conversion Start Trigger Select Select the A/D conversion start trigger in single scan mode and continuous scan mode. In group scan mode, the A/D conversion start trigger for group A is selected. 15:14 —...
Page 858: Adexicr : A/D Conversion Extended Input Control Registers
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.22 Selection of A/D activation sources in the TRSA[5:0] bits (2 of 2) Source Remarks TRSA[5] TRSA[4] TRSA[3] TRSA[2] TRSA[1] TRSA[0] ELC_AD01 ELC_AD00, ELC_AD01 30.2.18 ADEXICR : A/D Conversion Extended Input Control Registers Base address: ADC120 = 0x4005_C000 Offset address: 0x012 Bit position:...
Page 859: Adsstrn/Adsstrl/Adsstrt/Adsstro : A/D Sampling State Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Only set the TSSA bit when the ADCSR.ADST bit is 0. When executing A/D conversion of the temperature sensor output, the ADDISCR register is set to 0x0F and the A/D converter executes discharge (15 ADCLK) before executing sampling. The required sampling time is 5 µs or more. The A/D converter executes discharge each time A/D conversion is executed on the temperature sensor output.
Page 860: Addiscr : A/D Disconnection Detection Control Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.23 Relationship between A/D sampling state register and associated channels (2 of 2) Bit name Associated channels ADSSTRO.SST[7:0] bits Internal reference voltage Note 1. When the self-diagnosis function is selected, the sampling time set in the ADSSTR0.SST[7:0] bits is applied. Note 2.
Page 861: Adacsr : A/D Conversion Operation Mode Select Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.2.21 ADACSR : A/D Conversion Operation Mode Select Register Base address: ADC120 = 0x4005_C000 Offset address: 0x07E Bit position: ADSA Bit field: — — — — — — — Value after reset: Symbol Function —...
Page 862: Adcmpcr : A/D Compare Function Control Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Note 2. When the GBRP bit is set to 1, single scan is performed continuously for the group with the lower-priority regardless of the setting in the GBRSCN bit. PGS bit (Group Priority Operation Setting) Set the PGS bit to 1 to enable group priority operation.
Page 863 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function — This bit is read as 0. The write value should be 0. CMPAE Compare Window A Operation Enable 0: Disable compare window A operation. Disable ADC120_WCMPM and ADC120_WCMPUM outputs. 1: Enable compare window A operation.
Page 864: Adcmpansr0 : A/D Compare Function Window A Channel Select Register 0
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) CMPAIE bit (Compare A Interrupt Enable) The CMPAIE bit enables or disables the ADC120_CMPAI interrupt output when the comparison conditions (window A) are met. 30.2.24 ADCMPANSR0 : A/D Compare Function Window A Channel Select Register 0 Base address: ADC120 = 0x4005_C000 Offset address: 0x094 Bit position:...
Page 865: Adcmpanser : A/D Compare Function Window A Extended Input Select Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.2.26 ADCMPANSER : A/D Compare Function Window A Extended Input Select Register Base address: ADC120 = 0x4005_C000 Offset address: 0x092 Bit position: CMPO CMPT Bit field: — — — — — — Value after reset: Symbol Function...
Page 866: Adcmplr1 : A/D Compare Function Window A Comparison Condition Setting Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) CMPLCHAn bits (Compare Window A Comparison Condition Select) The CMPLCHAn bits specify the comparison conditions for channels to which Window A comparison conditions are applied. These bits can be set for each analog input to be compared. When the comparison result of each analog input meets the set condition, the ADCMPSR0.CMPSTCHAn flag sets to 1 and a compare interrupt (ADC120_CMPAI) is generated.
Page 867: Adcmpler : A/D Compare Function Window A Extended Input Comparison Condition Setting Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function 15:0 CMPLCHAn Compare Window A Comparison Condition Select These bits set comparison conditions for channels to which Window A comparison conditions are applied. Bit 15 (CMPLCHA31) is associated with AN031 and bit 1 (CMPLCHA17) is associated with AN017.
Page 868: Adcmpdrn : A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register (N = 0, 1)
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function — These bits are read as 0. The write value should be 0. CMPLTSA bit (Compare Window A Temperature Sensor Output Comparison Condition Select) The CMPLTSA bit specifies comparison conditions when the temperature sensor output is the target for the Window A comparison condition.
Page 869: Adwinnlb : A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register (N = L, U)
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Write Timing Write Timing ADCMPDR1/ ADCMPDR0/ ADWINULB ADWINLLB Upper reference Upper reference (before rewrite) (after rewrite) Lower reference Lower reference (before rewrite) (after rewrite) A/D conversion 1 A/D conversion 2 A/D conversion 3 Compare the reference Compare the reference after Compare the upper reference...
Page 870 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Set these registers so that the upper reference is not less than the lower reference ( and ADWINULB ≥ ADWINLLB). and ADWINULB are not used when the window function is disabled. Note 1. The lower and the upper references are changed when each register is written. For example, when the upper reference value is changed and the lower reference value is being changed, the MCU compares the upper reference (after rewrite), and the lower reference (before rewrite) with the A/D conversion result.
Page 871: Adcmpsr0 : A/D Compare Function Window A Channel Status Register 0
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.2.32 ADCMPSR0 : A/D Compare Function Window A Channel Status Register 0 Base address: ADC120 = 0x4005_C000 Offset address: 0x0A0 Bit position: CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS CMPS...
Page 872: Adcmpser : A/D Compare Function Window A Extended Input Channel Status Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) CMPSTCHAn flags (Compare Window A Flag) The CMPSTCHAn flags indicate the comparison results for channels to which Window A comparison conditions are applied. When the comparison condition set in ADCMPLR1.CMPLCHAn is met at the end of A/D conversion, the associated CMPSTCHAn flag sets to 1.
Page 873: Adcmpbnsr : A/D Compare Function Window B Channel Select Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) [Setting condition] ● The condition set in ADCMPLER.CMPLOCA is met when ADCMPCR.CMPAE = 1. [Clearing condition] ● Writing 0 after reading 1. 30.2.35 ADCMPBNSR : A/D Compare Function Window B Channel Select Register Base address: ADC120 = 0x4005_C000 Offset address: 0x0A6 Bit position:...
Page 874: Adcmpbsr : A/D Compare Function Window B Status Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Set the CMPCHB[5:0] bits while the ADCSR.ADST bit is 0. CMPLB bit (Compare Window B Comparison Condition Setting) The CMPLB bit specifies the comparison conditions for channels for Window B. When the comparison result of an analog input meets the set condition, the associated ADCMPBSR.CMPSTB flag sets to 1 and a compare interrupt request (ADC120_CMPBI) is generated.
Page 875: Adwinmon : A/D Compare Function Window A/B Status Monitor Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Symbol Function CMPSTB Compare Window B Flag When Window B operation is enabled (ADCMPCR.CMPBE = 1), this bit indicates the comparison result of channels to which Window B comparison conditions are applied, temperature sensor output, internal reference voltage, and CTSU TSCAP voltage.
Page 876: Adhvrefcnt : A/D High-Potential/Low-Potential Reference Voltage Control Register
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ● The combined result does not meet the combination condition set in the ADCMPCR.CMPAB[1:0] bits. ● ADCMPCR.CMPAE = 0 or ADCMPCR.CMPBE = 0. MONCMPA bit (Comparison Result Monitor A) The read-only MONCMPA bit is read as 1 when the A/D-converted value of the Window A target channel meets the condition set in ADCMPLR0/ADCMPLR1 and ADCMPLER.
Page 877: Operation
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) When setting the register, make sure that HVSEL[1:0] = 11b is set. Before selecting the internal reference voltage (HVSEL[1:0] = 10b), set HVSEL[1:0] = 11b to discharge the path of the high-potential reference voltage. After the discharge completes, set HVSEL[1:0] = 10b and start the A/D conversion. When the internal reference voltage is selected as the high-potential reference voltage (HVSEL[1:0] = 10b), A/D conversion is possible for analog channels, and CTSU TSCAP voltage, but A/D conversion of the internal reference voltage and the temperature sensor output is prohibited.
Page 878: Single Scan Mode
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) A/D conversion data with even number trigger (ELC_AD01) is stored in A/D Data Duplexing Register B (ADDBLDRB). In the extended operation of double trigger mode, when one of the trigger combinations occurs at the same time, the data duplexing register settings for the specified triggers do not work, and A/D conversion data is stored in A/D Data Duplexing Register B (ADDBLDRB).
Page 879 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 2. When A/D conversion for self-diagnosis completes, the A/D conversion result is stored in the A/D Self-Diagnosis Data Register (ADRD). A/D conversion is then performed for the ANn channels selected in the ADANSA0 and ADANSA1 registers, starting from the channel with the smallest number n.
Page 880 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Auto discharge Sampling (5 µs) A/D conversion (15 ADCLK) TSSA/OCSA ADDISCR[4:0] 0x0F ADST Interrupt Interrupt generated Note 1. ADC120_ADI Figure 30.9 Example basic operation in single scan mode when temperature sensor output or internal reference voltage is selected 30.3.2.4 A/D conversion in double-trigger mode...
Page 881 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) synchronous trigger A/D conversion A/D conversion performed once performed once A/D conversion ADST started A/D conversion time A/D conversion time Channel 3 A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion (AN003) Stored...
Page 882: Continuous Scan Mode
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) synchronous trigger A/D conversion is A/D conversion is executed once. executed once. A/D conversion ADST started A/D conversion time A/D conversion time Channel 3 A/D conversion 1 A/D conversion 2 Waiting for conversion Waiting for conversion Waiting for conversion (AN003)
Page 883 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) A/D conversion performed repeatedly Cleared A/D conversion ADST started A/D conversion time Channel 0 A/D conversion 1 Waiting for conversion A/D conversion 4 Waiting for conversion A/D conversion 6 Waiting for conversion (AN000) Channel 1 Waiting for conversion...
Page 884: Group Scan Mode
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Self-diagnosis and scanning performed repeatedly Cleared A/D conversion ADST started A/D conversion time Reference voltage A/D conversion for A/D conversion for A/D conversion for Waiting for conversion Waiting for conversion Waiting for conversion (×0, ×½, ×1) self-diagnosis1 self-diagnosis 2...
Page 885 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Timer count synchronous trigger 2 from GPT event synchronous trigger 1 from GPT event Time synchronous trigger 1 Group A scanned synchronous trigger 2 Group B scanned Scan end interrupt Scan end interrupt for group B Note 1.
Page 886 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 4. When the first scan of group A completes, the conversion result is stored in the associated A/D Data Register y (ADDRy); an ADC120_ADI interrupt request is not generated. 5. The second scan of group A is started by the second ELC_AD01 trigger. 6.
Page 887 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) The channels to be scanned must be selected in the registers shown in section 30.3.4. Group Scan Mode. Start Are the ADCSR.ADCS[1:0] bits set to 01b (group scan mode)? To disable trigger input, set the ADSTRGR.TRSA[5:0] bits to 0x3F. Are the ADCSR.ADCS[1:0] bits set to 10b (continuous scan mode)? To disable trigger input, set the ADSTRGR register to 0x3F3F...
Page 888 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.24 Control of A/D conversion operations according to ADGSPCR.GBRSCN bit setting (2 of 2) A/D conversion operation Trigger input ADGSPCR.GBRSCN = 0 ADGSPCR.GBRSCN = 1 When A/D conversion for Input of trigger for group A A/D conversion for group B is ●...
Page 889 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) A/D conversion on group A First A/D conversion on group B A/D conversion on group B (Group priority (Group B is activated by input of a group B trigger.) (Group B is automatically activated for rescanning.) operation) Group A trigger Group B trigger...
Page 890 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Second A/D conversion on group B A/D conversion on (Group B is A/D conversion on First A/D conversion on group B group A automatically group A Third A/D conversion on group B (Group B is activated by a group B (Group priority activated for...
Page 891 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) First A/D conversion on group A (Group A is activated A/D conversion on group B by a group A trigger.) (Group B is automatically activated for rescanning.) Group A trigger Group B trigger A/D conversion started ADST bit...
Page 892 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) A/D conversion on group A A/D conversion on group B (Group priority (Group B is activated by input of a group B trigger.) operation) Group A trigger Group B trigger Scan started ADST bit Group A Channel 0 (AN000)
Page 893: Compare Function For Windows A And B
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 9. If ADGSPCR.GBRP = 1 is set (performing single scan continuously), A/D conversion for the group B analog input channels selected in the ADANSB0 and ADANSB1 registers restarts according to the conversion order from the channel with the smallest number n while the ADCSR.ADST remains 1 (starting A/D conversion).
Page 894 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) request is generated. In the same way, when Window B meets the condition set in ADCMPBNSR.CMPLB, the Compare Window B Flag (ADCMPBSR.CMPSTB) sets to 1. At this time, if the ADCMPCR.CMPBIE bit is 1, an ADC120_CMPBI interrupt request is generated.
Page 895 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) One channel from analog input, internal reference voltage, CTSU TSCAP voltage, and temperature sensor output is selectable for window B. Additionally, if the internal reference voltage is selected as the high-potential reference voltage, the internal reference voltage or the temperature sensor output cannot be A/D converted.
Page 896 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) When CMPAB[1:0] = 10b Scanning performed once Scanning performed once A/D conversion ADST started Channel 0 (AN000) A/D conversion 1 Waiting for conversion A/D conversion 3 Waiting for conversion Waiting for conversion Channel 1 (AN001) Waiting for conversion A/D conversion 2...
Page 897: Analog Input Sampling And Scan Conversion Time
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.3.6 Analog Input Sampling and Scan Conversion Time Scan conversion can be activated either by a software trigger, a synchronous trigger (ELC), or an asynchronous trigger (ADTRG0). After the start-of-scanning-delay time (t ) has elapsed, processing for disconnection detection assistance, and processing of conversion for self-diagnosis all proceed, followed by processing for A/D conversion.
Page 898 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.25 Conversion times during scanning (in numbers of cycles of ADCLK and PCLKB) Type/Conditions Asynchronous Software Item Symbol Synchronous trigger trigger trigger Unit Scan start A/D conversion on Group B is to be stopped 3 PCLKB + 6 ADCLK —...
Page 899: Usage Example Of A/D Data Register Automatic Clearing Function
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 1) Single Scan SCAN DIAG CONV Software trigger Synchronous trigger ADST bit A/D converter Waiting DIAG conversion A/D conversion processing 2) Continuous Scan (2 channels) DIAG CONV CONV CONV DIAG Software trigger Synchronous trigger ADST bit A/D converter...
Page 900: A/D-Converted Value Addition/Average Mode
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) for some reason, the cleared data (0x0000) remains as the ADDRy value. If this ADDRy value is read into a general- purpose register using an A/D scan end interrupt, 0x0000 is saved in the general-purpose register. Occurrence of an ADDRy update failure can be determined by checking that the read data value is 0x0000.
Page 901 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Precharge Precharge control signal Example of the external circuit VREFH0 Discharge control signal R = 1 MΩ Analog input Sampling capacitance Disconnection Note 1. The converted result should be used after it is fully evaluated because the result data when disconnection occurs varies depending on the external circuit.
Page 902: Starting A/D Conversion With An Asynchronous Trigger
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Precharge control signal Discharge control signal Analog input Discharge Sampling capacitance Disconnection R = 1 MΩ VREFL0 Example of the external circuit Note 1. The converted result should be used after it is fully evaluated because the result data when disconnection occurs varies depending on the external circuit.
Page 903: Starting A/D Conversion With A Synchronous Trigger From A Peripheral Module
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.3.11 Starting A/D Conversion with a Synchronous Trigger from a Peripheral Module A/D conversion can be started by a synchronous trigger (ELC). To do this, set the ADCSR.TRGE bit to 1 and the ADCSR.EXTRG bit to 0, and select the relevant sources in the ADSTRGR.TRSA[5:0] and ADSTRGR.TRSB[5:0] bits.
Page 904: Event Link Function
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Table 30.26 The interrupt source and ELC event of ADC12 (2 of 2) Operation Compare Double trigger function Interrupt request or ELC Scan mode mode Window A/B event Function Group scan Deselected Deselected ADC120_ADI ✓...
Page 905: Selecting Reference Voltage
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) 30.6 Selecting Reference Voltage The ADC12 can select VREFH0, AVCC0, or internal reference voltage as the high-potential reference voltage, and can select VREFL0 or AVSS0 as the low-potential reference voltage. Set these reference voltages before starting A/D conversion.
Page 906: Constraints On Stopping A/D Conversion
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) ● A/D Temperature Sensor Data Register ● A/D Internal Reference Voltage Register ● A/D CTSU TSCAP Voltage Data Register ● A/D Self-Diagnosis Data Register If a register is read twice in byte units, that is, the upper byte and lower byte are read separately, the A/D-converted value read initially might disagree with the A/D-converted value read subsequently.
Page 907 RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Start Is the ADGSPCR.PGS bit set to 1? Set the ADGSPCR.PGS bit to 0 Are the ADCSR.ADCS[1:0] bits set to 01b (group scan mode)? To disable trigger inputs, set the ADSTRGR register to To disable trigger inputs, set the 0x3F3F (set the TRSA[5:0] and TRSB[5:0] bits to 0x3F ADSTRGR.TRSA[5:0] bits to 0x3F...
Page 908: A/D Conversion Restart And Termination Timing
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Notes on Modes and Status Bits If necessary, individually initialize or set again the voltage status for self-diagnosis, the judgment of the even number or odd number specified for double-trigger mode, and the monitor flags of the compare function. ●...
Page 909: Constraints On Operating Modes And Status Bits
RA2L1 User's Manual 30. 12-Bit A/D Converter (ADC12) Note: Do not reset the Sleep bit when the A/D Conversion Select bit (ADCSR.ADHSC) is 1. After this bit is set to 0 or the operating mode transitions to the module-stop mode, reset the Sleep bit using the ADCSR.ADHSC bit rewriting procedure.
Page 910: Port Settings When Using The Adc12 Input
Port Settings When Using the ADC12 Input When using the high-precision channels, do not use PORT0 as general I/O and CTSU input pins. Renesas recommends that you do not use the digital output that is also used as the AD analog input if normal-precision channel is used. If the digital output that is also used as the AD analog input is used for output signals, perform A/D conversion several times, eliminate the maximum and minimum values, and obtain the average of the other results.
Page 911: Bit D/A Converter (Dac12)
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) 12-Bit D/A Converter (DAC12) 31.1 Overview The MCU provides a 12-bit D/A Converter (DAC12) with an output amplifier. Table 31.1 lists the DAC12 specifications, Figure 31.1 shows a block diagram, and Table 31.2 lists the I/O pins.
Page 912: Register Descriptions
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) 31.2 Register Descriptions 31.2.1 DADR0 : D/A Data Register 0 Base address: DAC12 = 0x4005_E000 Offset address: 0x00 Bit position: Bit field: Value after reset: DADR0 register is 16-bit read/write registers that store data for D/A conversion. When an analog output is enabled, the values in DADR0 are converted and output to the analog output pins.
Page 913: Dadpr : Dadr0 Format Select Register
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) 31.2.3 DADPR : DADR0 Format Select Register Base address: DAC12 = 0x4005_E000 Offset address: 0x05 Bit position: DPSE Bit field: — — — — — — — Value after reset: Symbol Function —...
Page 914: Davrefcr : D/A Vref Control Register
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) 31.2.5 DAVREFCR : D/A VREF Control Register Base address: DAC12 = 0x4005_E000 Offset address: 0x07 Bit position: Bit field: — — — — — — — Value after reset: Symbol Function D/A Reference Voltage Select 0: No reference voltage selected.
Page 915: Reducing Interference Between D/A And A/D Conversion
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) Write to Write to Write to Write to DADR0 DACR DACR DADR0 Conversion data (1) Conversion data (2) DADR0 DACR.DAOE0 Conversion result (2) Conversion result High-impedance state DCONV DCONV : D/A conversion time DCONV Figure 31.2 Example of DAC12 operation...
Page 916 RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) ADCLK PCLK 12-bit A/D conversion (1) Halted A/D conversion 1 A/D conversion 2 ADST bit 12-bit A/D converter synchronous D/A conversion enable input signal (internal signal) 12-bit D/A conversion Standby D/A conversion A D/A conversion C DAADSCR.DAADST bit DACR.DAOE0 bit...
Page 917: Event Link Operation Setting Procedure
RA2L1 User's Manual 31. 12-Bit D/A Converter (DAC12) 31.4 Event Link Operation Setting Procedure This section describes the procedures used in event link operation. 31.4.1 DA0 Event Link Operation Setting Procedure To set up DA0 event link operation: 1. Set the DADPR.DPSEL bit and the data for D/A conversion in the DADR0 register. 2.
Page 918: Temperature Sensor (Tsn)
RA2L1 User's Manual 32. Temperature Sensor (TSN) Temperature Sensor (TSN) 32.1 Overview The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for reliable operation of the device. The sensor outputs a voltage directly proportional to the die temperature, and the relationship between the die temperature and the output voltage is fairly linear.
Page 919: Using The Temperature Sensor
● Slope: Temperature gradient of the temperature sensor (V / °C), slope = (V2 - V1) / (T2 -T1) Characteristics vary between sensors, so Renesas recommends measuring two different sample temperatures as follows: 1. Use the 12-bit A/D converter to measure the voltage V1 output by the temperature sensor at temperature T1.
Page 920: Procedures For Using The Temperature Sensor
RA2L1 User's Manual 32. Temperature Sensor (TSN) ±12.0 ±10.0 ±8.0 ±6.0 ±4.0 ±2.0 ±0.0 Measured temperature [°C] Figure 32.2 Error in the measured temperature (designed values) 32.3.2 Procedures for Using the Temperature Sensor For details, see section 30, 12-Bit A/D Converter (ADC12).
Page 921: Low Power Analog Comparator (Acmplp)
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Low Power Analog Comparator (ACMPLP) 33.1 Overview The Low-Power Analog Comparator (ACMPLP) compares a reference input voltage with an analog input voltage. Comparator channels ACMPLP0 and ACMPLP1 are independent of each other. The comparison result of the reference input voltage and analog input voltage can be read by software.
Page 922 RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) CPLOUT1 VCOUT CPLOUT0 C1VRF C1MON C1EDG C0VRF SPDMD C0MON C0EDG CMPIN1 Noise reduction filter (same value ACMP_LP1 else CMPREF1 Edge sampled 3 times) interrupt request selector ELC event request Internal Vref CPLOUT1 Internal Vref Noise reduction...
Page 923: Register Descriptions
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Table 33.2 Comparator pin configuration Comparator Reference voltage input pin Analog voltage input pin Output pin ACMPLP0 CMPREF0 CMPIN0 VCOUT ACMPLP1 CMPREF1 CMPIN1 Note 1. ACMPLP0 and ACMPLP1 compare outputs are bundled on the VCOUT pin. 33.2 Register Descriptions 33.2.1...
Page 924: Compfir : Acmplp Filter Control Register
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Note 3. The initial value is 0 immediately after a reset is released. However, the value is undefined when C0ENB is set to 0 and C1ENB is set to 0 after operation of the comparator is enabled once. Note 4.
Page 925: Operation
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Symbol Function C0OP ACMPLP0 VCOUT Output Polarity Selection 0: Non-inverted 1: Inverted — These bits are read as 0. The write value should be 0. C1OE ACMPLP1 VCOUT Pin Output Enable 0: Disabled 1: Enabled C1OP...
Page 926 RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Note 2. Can be set in high-speed mode (SPDMD = 1). Note 3. After the setting of the comparator, a spurious interrupt may occur until operation becomes stable, so initialize the interrupt flag. Note 4.
Page 927: Noise Filter
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) Reference input voltage (IVREF1) Reference input voltage (IVREF0) COMPMDR.CiMON bit (i = 0, 1) IELSRn.IR flag in Interrupt Controller Unit Set to 0 by program Figure 33.4 Operating example of ACMPLPi (i = 0, 1) when window function is enabled Figure 33.4 applies when the following conditions are met: ●...
Page 928: Acmplp Interrupts
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) C1MON C1EDG C0MON C0EDG Noise reduction filter (same value ACMPLP1 else ACMP_LP1 Edge sampled 3 times) signal interrupt request selector ELC event request CPLOUT1 Noise reduction filter (same value ACMPLP0 else ACMP_LP0 Edge sampled 3 times)
Page 929: Elc Event Output
RA2L1 User's Manual 33. Low Power Analog Comparator (ACMPLP) 33.6 ELC Event Output The ELC uses the ACMPLP interrupt request signal as an ELC event signal, enabling link operation for the preset module. To use the ELC events of the ACMPLP, select them in the ELSRn register in the ELC. When using ELC event request, set the COMPFIR.CiFCK[1:0] bits to 01b, 10b, or 11b.
Page 930: Capacitive Sensing Unit 2 (Ctsu)
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Capacitive Sensing Unit 2 (CTSU) 34.1 Overview The Capacitive Sensing Unit 2 (CTSU) measures the electrostatic capacitance of the sensor. Changes in the electrostatic capacitance are determined by software that enables the CTSU to detect whether a finger is in contact with the sensor. The electrode surface of the sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode.
Page 931 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Table 34.1 CTSU specifications Parameter Specifications Operating clock PCLKB, PCLKB/2, PCLKB/4, or PCLKB/8 Pins Electrostatic capacitance measurement 32 channels TSCAP Low Pass Filter (LPF) connection pin Measurement modes Self-capacitance measurement mode The electrostatic capacitance is measured by the charge and discharge current to the electrodes in the self-capacitance method.
Page 932: Register Descriptions
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) I/O Block Capacitive Sensing Unit Channel Port Trigger Port control Event input from the ELC control control control block Port block block control PCLK Clock Sensor drive pulse Operating PCLK/2 Sensor drive Clock control pulse generator...
Page 933 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function CTSU Measurement Operation Start Trigger Select 0: Software trigger 1: External trigger CTSU Wait State Power-Saving Enable 0: Disable power-saving function during wait state 1: Enable power-saving function during wait state CFCON CTSU CFC Power On Control 0: CFC power off...
Page 934 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 19:18 LOAD[1:0] CTSU Load Control During Measurement 0 0: 2.5 µA constant current load 0 1: No load 1 0: 20 µA constant current load and overcurrent detector disabled 1 1: Resistance load for calibration.
Page 935 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) ● While waiting for an external trigger: CTSUSR.STC[2:0] flags = 000b ● When the CTSU is not used, set this bit to 0. If software sets the STRT bit to 1 when the bit is already 1, the write is ignored and operation continues. To force operation to stop through software when the STRT bit is 1, set the STRT bit to 0 and the INIT bit to 1 simultaneously.
Page 936 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) ATUNE2 and ATUNE1 bits (CTSU Current Range Adjustment) The ATUNE2 and ATUNE1 bits set the current range at the time of measurement. In general, setting these bits to 00b is recommended. CLK[1:0] bits (CTSU Operating Clock Select) The CLK[1:0] bits select the operating clock.
Page 937: Ctsucrb/Ctsucrbh/Ctsucrbl/Ctsudclkc/Ctsusst/Ctsusdprs : Ctsu Control Register B
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) 34.2.2 CTSUCRB/CTSUCRBH/CTSUCRBL/CTSUDCLKC/CTSUSST/CTSUSDPRS : CTSU Control Register B Base address: CTSU = 0x4008_2000 Offset address: 0x04 (CTSUCRB/CTSUCRBL/CTSUSDPRS) 0x05 (CTSUSST) 0x06 (CTSUCRBH) 0x07 (CTSUDCLKC) Bit position: Bit field: — — SSCNT[1:0] — SSMOD[2:0] —...
Page 938 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 31:30 — These bits are read as 0. The write value should be 0. The CTSU Control Register B (CTSUCRB/CTSUCRBH/CTSUCRBL/CTSUDCLKC/CTSUSST/CTSUSDPRS) is a 32-bit, 16-bit, and 8-bit read/write register. The CTSUCRB is accessed in 32-bit units. The CTSUCRBH (bits [31:16] in CTSUCRB) and CTSUCRBL (bits [15:0] in CTSUCRB) are accessed in 16-bit units.
Page 939: Ctsumch/Ctsumchh/Ctsumchl/Ctsumfaf/Ctsumch1/Ctsumch0 : Ctsu Measurement Channel Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) 34.2.3 CTSUMCH/CTSUMCHH/CTSUMCHL/CTSUMFAF/CTSUMCH1/CTSUMCH0 : CTSU Measurement Channel Register Base address: CTSU = 0x4008_2000 Offset address: 0x08 (CTSUMCH/CTSUMCHL/CTSUMCH0) 0x09 (CTSUMCH1) 0x0A (CTSUMCHH/CTSUMFAF) Bit position: Bit field: — — — — — — — —...
Page 940 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 13:8 MCH1[5:0] CTSU Measurement Channel 1 In single scan mode, these bits set the transmit channel to be measured. Setting undefined pin for these bits is prohibited. In multi-scan modes, these bits indicate the transmit channel that is currently being measured.
Page 941: Ctsuchaca/Ctsuchacah/Ctsuchacal/Ctsuchac3/Ctsuchac2/Ctsuchac1/ Ctsuchac0 : Ctsu Channel Enable Control Register A
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) MCH1[5:0] bits (CTSU Measurement Channel 1) In single scan mode, the MCH1[5:0] bits set the transmit channel to be measured. In this mode, only specify the enabled channels (0x00, 0x02, 0x04 to 0x12, 0x15 to 0x23) and only specify the measure channels that are set by CTSUCHACA and CTSUCHACB registers.
Page 942: Ctsuchacb/Ctsuchacbl/Ctsuchac4 : Ctsu Channel Enable Control Register B
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function CHAC02 CTSU Channel Enable Control A These bits select whether the associated TS pin is measured. This bit specifies the TS02-CFC pin. 0: Do not measure. 1: Measure. — This bit is read as 0.
Page 943: Ctsuchtrca/Ctsuchtrcah/Ctsuchtrcal/Ctsuchtrc3/Ctsuchtrc2/ Ctsuchtrc1/Ctsuchtrc0 : Ctsu Channel Transmit/Receive Control Register A
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 31:4 — These bits are read as 0. The write value should be 0. The CTSU Channel Enable Control Register B (CTSUCHACB/CTSUCHACBL/CTSUCHAC4) is a 32-bit, 16-bit, and 8- bit read/write register. The CTSUCHACB is accessed in 32-bit units.
Page 944: Ctsuchtrcb/Ctsuchtrcbl/Ctsuchtrc4 : Ctsu Channel Transmit/Receive Control Register B
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 31:21 CHTRC21 to CTSU Channel Transmit/Receive Control A CHTRC31 These bits control the TS21 to TS25 and TS26-CFC to TS31-CFC pins reception/ transmission. 0: Reception 1: Transmission The CTSU Channel Transmit/Receive Control Register A (CTSUCHTRCA/CTSUCHTRCAH/CTSUCHTRCAL/ CTSUCHTRC3/CTSUCHTRC2/CTSUCHTRC1/CTSUCHTRC0) is a 32-bit, 16-bit, and 8-bit read/write register.
Page 945: Ctsusr/Ctsusrh/Ctsusrl/Ctsusr2/Ctsust/Ctsusr0 : Ctsu Status Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) CHTRC32 to CHTRC35 bits (CTSU Channel Transmit/Receive Control B) The CHTRC32 to CHTRC35 bits assign the associated TS pins to reception or transmission. CHTRC32 bit is associated with TS32-CFC and CHTRC35 bit is associated with TS35-CFC. When CTSUCRA.MD1 = 0, the channel set for transmission can be used as the output of the active shield signal.
Page 946 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function SENSOVF CTSU Sensor Counter Overflow Flag This flag indicates an overflow on the sensor counter. 0: No overflow occurred 1: Overflow occurred SUOVF CTSU SUCLK Counter Overflow Flag This flag indicates an overflow of the SUCLK counter for the drive pulse clock or the frequency spreading clock.
Page 947 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) ICOMPRST bit (CTSU CTSUICOMP1 Flag Reset) When 1 is written to the ICOMPRST bit, the ICOMP0 and ICOMP1 bits are cleared. ICOMP1 bit (CTSU Sense Current Error Monitor) The ICOMP1 bit specifies that the measurement current is equal to the measurement range set by the ATUNE[1:0] bit. This is set to 1 when the current is excessive.
Page 948: Ctsuso/Ctsuso1/Ctsuso0 : Ctsu Sensor Offset Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) 34.2.9 CTSUSO/CTSUSO1/CTSUSO0 : CTSU Sensor Offset Register Base address: CTSU = 0x4008_2000 Offset address: 0x20 (CTSUSO/CTSUSO0) 0x22 (CTSUSO1) Bit position: 31 24 23 Bit field: SDPA[7:0] SSDIV[3:0] — — SNUM[7:0] SO[9:0] Value after reset: Symbol Function...
Page 949: Ctsuscnt/Ctsusc : Ctsu Sensor Counter Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) The number of repetitions is (SNUM[5:0] bits + 1). When CTSUCRA.SDPSEL bit is 1, the SNUM[7:0] bits set the time of measurements using the following formula: Measurement time = (STCLK cycle × 8) × SNUM[7:0] bits + 1) SSDIV[3:0] bits (Spread Spectrum Frequency) The SSDIV[3:0] bits set the division setting value of the spread spectrum clock based on the division setting of the base clock.
Page 950: Ctsucalib/Ctsudbgr1/Ctsudbgr0 : Ctsu Calibration Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function 31:16 SUCKCNT[15:0] CTSU SUCLK Counter These bits indicate the measurement result of SUCLK clock count results. They read 0xFFFF when an overflow occurs. The CTSU Sensor Counter Register (CTSUSCNT/CTSUSC) is a 32-bit and 16-bit read-only register. The CTSUSCNT is accessed in 32-bit units.
Page 951 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) Symbol Function SUCLKEN SUCLK Forced Oscillation Control This bit oscillates the SUCLK oscillator when not measuring. 0: SUCLK oscillation only during measurement 1: SUCLK always oscillates TSOC Switched Capacitor Operation Stop This bit stop the switched capacitor operation 0: Operation 1: Stop...
Page 952 RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) The CTSUCALIB is accessed in 32-bit units. The CTSUDBGR1 (bits [31:16] in CTSUCALIB) and CTSUDBGR0 (bits [15:0] in CTSUCALIB) are accessed in 16-bit units. TSOD bit (All TS Pin Control) The TSOD bit controls the output of all TS pins. When the TSOD = 1, the valid channel outputs the value of the IOC bit according to the power supply of the TXVSEL[1:0] bits.
Page 953: Ctsusuclka/Ctsusuclk1/Ctsusuclk0 : Ctsu Sensor Unit Clock Control Register A
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) CCOCALIB bit (Calibration Selection of Current Controlled Oscillator for Measurement) When CCOCALIB = 1, the input current of the SUCLK current control oscillator and the measurement current control oscillator are swapped. The characteristics of the measurement current controlled oscillator can be calibrated by supplying the input current of the SUCLK current controlled oscillator to the measurement current controlled oscillator.
Page 954: Ctsusuclkb/Ctsusuclk3/Ctsusuclk2 : Ctsu Sensor Unit Clock Control Register B
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) These bits compare the STCLK with the SUCLK divided by the SUMULTI0[7:0] and SUMULTI1[7:0] bits setting, and the SUMULTI0[7:0] and SUMULTI1[7:0] are updated based on comparison result. 34.2.13 CTSUSUCLKB/CTSUSUCLK3/CTSUSUCLK2 : CTSU Sensor Unit Clock Control Register B Base address: CTSU = 0x4008_2000 Offset address: 0x30 (CTSUSUCLKB/CTSUSUCLK2)
Page 955: Ctsucfccnt/Ctsucfccntl : Ctsu Cfc Counter Register
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) 34.2.14 CTSUCFCCNT/CTSUCFCCNTL : CTSU CFC Counter Register Base address: CTSU = 0x4008_2000 Offset address: 0x34 Bit position: 31 Bit field: — — — — — — — — — — — —...
Page 956: Ctsutrimb : Ctsu Trimming Register B
RA2L1 User's Manual 34. Capacitive Sensing Unit 2 (CTSU) 34.2.16 CTSUTRIMB : CTSU Trimming Register B Base address: FLCN = 0x407E_C000 Offset address: 0x03A8 Bit position: 31 24 23 16 15 Bit field: TRESULT3[7:0] TRESULT2[7:0] TRESULT1[7:0] TRESULT0[7:0] Value after reset: Symbol Function TRESULT0[7:0]...
Page 957: Data Operation Circuit (Doc)
RA2L1 User's Manual 35. Data Operation Circuit (DOC) Data Operation Circuit (DOC) 35.1 Overview The Data Operation Circuit (DOC) compares, adds, and subtracts 16-bit data. When a selected condition applies, 16-bit data is compared and an interrupt can be generated. Table 35.1 lists the DOC specifications and Figure 35.1...
Page 958: Dodir : Doc Data Input Register
RA2L1 User's Manual 35. Data Operation Circuit (DOC) Symbol Function OMS[1:0] Operating Mode Select 0 0: Data comparison mode 0 1: Data addition mode 1 0: Data subtraction mode 1 1: Setting prohibited Detection Condition Select DCSEL 0: Set DOPCF flag when data mismatch is detected 1: Set DOPCF flag when data match is detected —...
Page 959: Dodsr : Doc Data Setting Register
RA2L1 User's Manual 35. Data Operation Circuit (DOC) 35.2.3 DODSR : DOC Data Setting Register Base address: DOC = 0x4005_4100 Offset address: 0x04 Bit position: Bit field: Value after reset: Symbol Function 15:0 It stores 16-bit data used as a reference in data comparison mode. This register also stores the results of operations in data addition and subtraction modes.
Page 960: Data Subtraction Mode
RA2L1 User's Manual 35. Data Operation Circuit (DOC) DOCR.OMS[1:0] bits xxxx 0xFFF0 0xFFF4 0xFFFA 0x0002 DODSR register DODIR register xxxx 0x0004 0x0006 0x0008 Write 1 to DOCR.DOPCFCL bit DOCR.DOPCF flag Figure 35.3 Example of operation in data addition mode 35.3.3 Data Subtraction Mode Figure 35.4 shows an example operation in data subtraction mode.
Page 961: Output Of An Event Signal To The Event Link Controller (Elc)
RA2L1 User's Manual 35. Data Operation Circuit (DOC) Table 35.2 Interrupt request from DOC Interrupt request Status flag Interrupt source DOC interrupt DOPCF ● The result of data comparison matches the condition selected in the DOCR.DCSEL bit. ● The result of data addition is greater than 0xFFFF. ●...
Page 962: Sram
RA2L1 User's Manual 36. SRAM SRAM 36.1 Overview The MCU provides an on-chip, high-density SRAM module with either parity-bit checking or Error Correction Code (ECC). The first 16 KB area of the SRAM0 is the ECC. Parity check is performed on the other areas. Table 36.1 lists the SRAM specifications.
Page 963: Sramprcr : Sram Protection Register
RA2L1 User's Manual 36. SRAM 36.2.2 SRAMPRCR : SRAM Protection Register Base address: SRAM = 0x4000_2000 Offset address: 0x04 Bit position: SRAM Bit field: KW[6:0] PRCR Value after reset: Symbol Function SRAMPRCR Register Write Control 0: Disable writes to protected registers 1: Enable writes to protected registers KW[6:0] Write Key Code...
Page 964: Ecc2Sts : Ecc 2-Bit Error Status Register
RA2L1 User's Manual 36. SRAM 36.2.4 ECC2STS : ECC 2-Bit Error Status Register Base address: SRAM = 0x4000_2000 Offset address: 0xC1 Bit position: ECC2 Bit field: — — — — — — — Value after reset: Symbol Function ECC2ERR ECC 2-Bit Error Status 0: No 2-bit ECC error occurred 1: 2-bit ECC error occurred —...
Page 965: Ecc1Sts : Ecc 1-Bit Error Status Register
RA2L1 User's Manual 36. SRAM 36.2.6 ECC1STS : ECC 1-Bit Error Status Register Base address: SRAM = 0x4000_2000 Offset address: 0xC3 Bit position: ECC1 Bit field: — — — — — — — Value after reset: Symbol Function ECC1ERR ECC 1-Bit Error Status R/(W) 0: No 1-bit ECC error occurred 1: 1-bit ECC error occurred...
Page 966: Eccprcr2 : Ecc Protection Register 2
RA2L1 User's Manual 36. SRAM 36.2.8 ECCPRCR2 : ECC Protection Register 2 Base address: SRAM = 0x4000_2000 Offset address: 0xD0 Bit position: ECCP Bit field: KW2[6:0] RCR2 Value after reset: Symbol Function ECCPRCR2 Register Write Control 0: Disable writes to the protected registers 1: Enable writes to the protected registers KW2[6:0] Write Key Code...
Page 967: Eccoad : Sram Ecc Error Operation After Detection Register
RA2L1 User's Manual 36. SRAM 36.2.10 ECCOAD : SRAM ECC Error Operation After Detection Register Base address: SRAM = 0x4000_2000 Offset address: 0xD8 Bit position: Bit field: — — — — — — — Value after reset: Symbol Function Operation After Detection 0: Non-maskable interrupt 1: Reset —...
Page 968: Operation
RA2L1 User's Manual 36. SRAM Table 36.3 Address of CoreSight (2 of 2) Address Register MTB_BASE + 0xFCC Device Type Identifier MTB_BASE + 0xFC8 Device Configuration MTB_BASE + 0xFBC Device Architecture MTB_BASE + 0xFB8 Authentication Status MTB_BASE + 0xFB4 Lock Status MTB_BASE + 0xFB0 Lock Access Note:...
Page 969: Ecc Decoder Testing
RA2L1 User's Manual 36. SRAM 36.3.3 ECC Decoder Testing Figure 36.1 shows the ECC decoder testing. Start Initialize the target address to 0x0000_0000 Write 0xF1 to the SRAM0 (ECC area) Protection Register and enable writes to the SRAM-related registers Write 0x03 to the SRAM0 (ECC area) Operating Mode Control Register and set the ECC enable mode Write 4-byte data to the target address.
Page 970: Parity Calculation Function
RA2L1 User's Manual 36. SRAM 36.3.4 Parity Calculation Function The IEC60730 standard requires the checking of SRAM data. When data is written, a parity bit is added to every 8-bit data in the SRAM which has 32-bit data width, and when data is read, the parity is checked. When a parity error occurs, a parity- error notification is generated.
Page 971: Sram Error Sources
RA2L1 User's Manual 36. SRAM <MAIN processing> <NMI processing> Start of check Initial setting (parity NMI) Check SRAM Parity error generated RPEST Check SRAM RETURN RPEST Normal SRAM failure operation processing Note 1. RPEST: SRAM Parity Error Interrupt Status Flag (NMISR.RPEST bit) Figure 36.3 Flow of SRAM parity check when SRAM parity interrupt is enabled 36.3.5...
Page 972: Access Cycle
SRAM area that is not initialized, ECC error or a parity error might occur. Initialize the additional 2-byte area from the end address of a program with a 4-byte boundary. Renesas recommends using the NOP instruction for data initialization.
Page 973: Flash Memory
RA2L1 User's Manual 37. Flash Memory Flash Memory 37.1 Overview The MCU provides up to 256-KB code flash memory and 8-KB data flash memory. The Flash Control Block (FCB) controls the programming commands. Table 37.1 lists the specifications of the code flash memory and data flash memory, and Figure 37.1 shows a block diagram of the related modules.
Page 974: Memory Structure
RA2L1 User's Manual 37. Flash Memory Internal peripheral bus 9 Data flash memory Flash ready Prefetch interrupt Code flash memory Buffer (FCU_FRDYI) MD pin Mode control Figure 37.1 Flash memory-related modules block diagram 37.2 Memory Structure Figure 37.2 shows the mapping of the code flash memory, and Table 37.2 shows the read and programming and erasure (P/E) addresses of the code flash memory.
Page 975: Register Descriptions
RA2L1 User's Manual 37. Flash Memory The data area of the data flash memory is divided into 1-KB blocks, with each being a unit for erasure. Figure 37.3 shows the mapping of the data flash memory, and Table 37.3 shows the read and programming and erasure addresses of the data flash memory.
Page 976: Pfber : Prefetch Buffer Enable Register
RA2L1 User's Manual 37. Flash Memory 37.3.2 PFBER : Prefetch Buffer Enable Register Base address: FLCN = 0x407E_C000 Offset address: 0x3FC8 Bit position: Bit field: — — — — — — — PFBE Value after reset: Symbol Function PFBE Prefetch Buffer Enable bit 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled —...
Page 977: Fpr : Protection Unlock Register
RA2L1 User's Manual 37. Flash Memory [Clearing conditions] ● Data is written by byte access. ● A value other than 0xAA is set to the FEKEY[7:0] bits and written to the FENTRYR register. ● Set 0xAA00 to the FENTRYR register. ●...
Page 978: Fpmcr : Flash P/E Mode Control Register
RA2L1 User's Manual 37. Flash Memory PERR bit (Protect Error Flag) When the FPMCR register is not accessed as described in the procedure to unlock protection, data is not written to the register and this flag is set to 1. [Setting condition] ●...
Page 979: Fisr : Flash Initial Setting Register
RA2L1 User's Manual 37. Flash Memory 37.3.7 FISR : Flash Initial Setting Register Base address: FLCN = 0x407E_C000 Offset address: 0x01D8 Bit position: Bit field: SAS[1:0] PCKA[5:0] Value after reset: Symbol Function PCKA[5:0] Peripheral Clock Notification These bits set the frequency of the Flash IF clock (ICLK). SAS[1:0] Startup Area Select 1 0: The startup area is switched to the default area temporarily...
Page 980: Fresetr : Flash Reset Register
RA2L1 User's Manual 37. Flash Memory ● When switching the startup area to the default area temporarily with 10b written to the SAS[1:0] bits, the startup area is switched to the default area immediately after data is written to the register, regardless of the startup area settings of the extra area.
Page 981: Fcr : Flash Control Register
RA2L1 User's Manual 37. Flash Memory 37.3.10 FCR : Flash Control Register Base address: FLCN = 0x407E_C000 Offset address: 0x0114 Bit position: Bit field: OPST STOP — CMD[3:0] Value after reset: Symbol Function CMD[3:0] Software Command Setting 0x1: Program 0x3: Blank check (code flash) 0x4: Block erase 0x5: Consecutive read 0x6: Chip erase...
Page 982: Fexcr : Flash Extra Area Control Register
RA2L1 User's Manual 37. Flash Memory Reads the flash macro from the start address pointed by the FSARH and FSARL registers to the end address pointed by the FEARH and FEARL registers. The read data is stored in the FRBH and FRBL registers. The consecutive read command is allowed to execute within the region of the flash macros.
Page 983 RA2L1 User's Manual 37. Flash Memory When programming using the FEXCR register, the programming area is erased automatically before execution, therefore it is not necessary to erase beforehand. CMD[2:0] bits (Software Command Setting) The CMD[2:0] bits select the software command from the: ●...
Page 984 RA2L1 User's Manual 37. Flash Memory Table 37.6 Mapping for the extra bit of the access window information program (address (P/E) : 0x0000_0010) (2 of 2) SASM — — — — FAWE[10:0] FSPR — — — — FAWS[10:0] Note 1. Once 0 is set as data in these bits, it cannot be changed to 1. [OCDID1-4 program] These commands set the OCDID[127:0] bits.
Page 985: Fsarh : Flash Processing Start Address Register H
RA2L1 User's Manual 37. Flash Memory 37.3.12 FSARH : Flash Processing Start Address Register H Base address: FLCN = 0x407E_C000 Offset address: 0x0110 Bit position: Bit field: FSARH[15:0] Value after reset: Symbol Function 15:0 FSARH[15:0] Flash Processing Start Address H Flash Processing Start Address upper 16 bits Note: The write value should be 0 for b8 to b5, and those bits are read as 0.
Page 986: Fearl : Flash Processing End Address Register L
RA2L1 User's Manual 37. Flash Memory Symbol Function 15:0 FEARH[15:0] Flash Processing End Address H Flash processing end address upper 16 bits Note: The write value should be 0 for b8 to b5, and those bits are read as 0. FEARH[15:0] bits (Flash Processing End Address H) The FEARH register is allowed to set or clear only in the P/E mode.
Page 987: Fwbh0 : Flash Write Buffer Register H0
RA2L1 User's Manual 37. Flash Memory 37.3.17 FWBH0 : Flash Write Buffer Register H0 Base address: FLCN = 0x407E_C000 Offset address: 0x0138 Bit position: Bit field: WDATA[15:0] Value after reset: Symbol Function 15:0 WDATA[15:0] Write Data Flash write buffer data upper 16 bits Note: The FSARH register is allowed to set or clear only in the P/E mode.
Page 988: Fstatr00 : Flash Status Register 0
RA2L1 User's Manual 37. Flash Memory Symbol Function 15:0 RDATA[15:0] Read Data H RDATA[15:0] store bits [31:16] of the read data of the code flash when the consecutive read command is executed. 37.3.20 FSTATR00 : Flash Status Register 0 Base address: FLCN = 0x407E_C000 Offset address: 0x0128 Bit position: EILGL...
Page 989: Fstatr2 : Flash Status Register 2
RA2L1 User's Manual 37. Flash Memory ● The chip erase command is executed when the access window is set (the start block address of the access window is not equal to the end one) ● The blank check, the block erase, consecutive read, and the chip erase commands are executed when the start address set to the FSARH and FSARL registers is larger than the end address set to the FEARH and FEARL registers ●...
Page 990: Fstatr1 : Flash Status Register 1
RA2L1 User's Manual 37. Flash Memory Symbol Function 15:6 — These bits are read as 0. 37.3.22 FSTATR1 : Flash Status Register 1 Base address: FLCN = 0x407E_C000 Offset address: 0x012C Bit position: EXRD DRRD Bit field: FRDY — — —...
Page 991: Feaml : Flash Error Address Monitor Register L
RA2L1 User's Manual 37. Flash Memory 37.3.24 FEAML : Flash Error Address Monitor Register L Base address: FLCN = 0x407E_C000 Offset address: 0x01E0 Bit position: Bit field: FEAML[15:0] Value after reset: Symbol Function 15:0 FEAML[15:0] Flash Error Address Monitor Register L Flash error address monitor lower 16 bits The error address is withdrawn from the FEAML and the FEAMH registers after a software command execution.
Page 992: Fawemr : Flash Access Window End Address Monitor Register
RA2L1 User's Manual 37. Flash Memory Note 1. The value of the blank product is 1. It is set to the same value set in bits [10:0] in the FWBH0 register after the access window information program command is executed. Symbol Function 10:0...
Page 993: Id Code Protection
The ID code in flash memory consists of four 32-bit words. ID code bits [127] and [126] determine whether ID code protection is enabled and the authentication method to use with the host. ID code bit [127] determines whether Renesas test mode is blocked.
Page 994: Overview Of Functions
Protection enabled ID code validation is not performed, the ID code is always mismatching, and connection to the programmer or the on-chip debugger is prohibited. In addition, Renesas test mode is blocked. 37.6 Overview of Functions By using a dedicated flash-memory programmer to program the on-chip flash memory through a serial interface (serial programming mode) or through SWD interface (on-chip debug mode), the device can be programmed before or after it is mounted on the target system.
Page 995: Security Functions
RA2L1 User's Manual 37. Flash Memory Table 37.14 Programming methods (2 of 2) Programming method Functional overview Operating mode SWD programming A dedicated flash-memory programmer or an on-chip debugger On-chip debug mode connected through SWD can program the on-board flash memory after the device is mounted on the target system.
Page 996: Configuration Area Bit Map
RA2L1 User's Manual 37. Flash Memory Table 37.17 Available operations and security settings Constraints on the security All security settings and erasure, programming, and read operations setting configuration Function Serial programming and on-chip debug mode Self-programming mode Self-programming mode ID authentication When the ID codes do not match: ●...
Page 997: Protection By Access Window
RA2L1 User's Manual 37. Flash Memory Address Before rewriting User program User program User program 0x0000_3FFF New start-up Original start-up No program program program (alternate area) (alternate area) (default area) 0x0000_1FFF Original start-up New start-up Original start-up program program program (default area) (alternate area) (default area)
Page 998: Programming Commands
RA2L1 User's Manual 37. Flash Memory Address 0x0003_FFFF Protected area Block 8 0x0000_4000 0x0000_3FFF Block 7 (end block) Block 6 Access Non-protected area Window Block 5 Block 4 (start block) 0x0000_2000 0x0000_1FFF Block 3 Block 2 Protected area Block 1 Block 0 0x0000_0000 Figure 37.7...
Page 999: Area Protection
RA2L1 User's Manual 37. Flash Memory Address Before rewriting 0x0001_FFFF User program User program User program 0x0000_7FFF New start-up Orignal start-up No program program program (alternate area) (alternate area) (default area) 0x0000_3FFF Orignal start-up New start-up Orignal start-up program program program (default area) (alternate area)
Page 1000: Serial Programming Mode
RA2L1 User's Manual 37. Flash Memory Address The address : That is set to the FWBH0 Disabled register in executing the Block 8 access window information 0x0000_4000 program command (the next Block 7 0x0000_3FFF block of the end block of the (end block) access window) Block 6...

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