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RX − 8801 SA / JE
2
8.6.6. I
C bus protocol
In the following sequence descriptions, it is assumed that the CPU is the master and the RX-8801 is the slave.
a. Address specification write sequence
Since the RX-8801 includes an address auto increment function, once the initial address has been specified, the
RX-8801 increments (by one byte) the receive address each time data is transferred.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8801's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RX-8801.
(4) CPU transmits write address to RX-8801.
(5) Check for ACK signal from RX-8801.
(6) CPU transfers write data to the address specified at (4) above.
(7) Check for ACK signal from RX-8801.
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.
(9) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
b. Address specification read sequence
After using write mode to write the address to be read, set read mode to read the actual data.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8801's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RX-8801.
(4) CPU transfers address for reading from 8801.
(5) Check for ACK signal from RX-8801.
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition [P]).
(7) CPU transfers RX-8801's slave address with the R/W bit set to read mode.
(8) Check for ACK signal from RX-8801 (from this point on, the CPU is the receiver and the RX-8801 is the
transmitter).
(9) Data from address specified at (4) above is output by the RX-8801.
(10) CPU transfers ACK signal to RX-8801.
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.
(12) CPU transfers ACK signal for "1".
(13) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
c. Read sequence when address is not specified
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read
operation is the previously accessed address + 1.
(1) CPU transfers start condition [S].
(2) CPU transmits the RX-8801's slave address with the R/W bit set to read mode.
(3) Check for ACK signal from RX-8801 (from this point on, the CPU is the receiver and the RX-8801 is the
transmitter).
(4) Data is output from the RX-8801 to the address following the end of the previously accessed address.
(5) CPU transfers ACK signal to RX-8801.
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RX-8801.
(7) CPU transfers ACK signal for "1".
(8) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
(3)
(4)
0
0
Address
R/W
(3)
(4)
(5)
(6)
0
0
Address
0
Sr
R/W
ACK from RX-8801
(3)
(4)
1
0
Data
R/W
ACK from RX-8801
(5)
(6)
(7)
0
Data
0
ACK signal from RX-8801
(7)
(8)
(9)
Slave address
1
0
Data
R/W
(5)
(6)
(7)
(8)
0
Data
1
P
ACK from CPU
Page - 25
(8)
(9)
Data
0
P
(10)
(11)
(12)
0
Data
ACK from CPU
ETM26E-03
(13)
1
P
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