RM0403-3-E01 Application Manua Real Time Clock Module RX-8564LC Model RX-8564LC Product Number Q418564C0xxxx00...
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13. Description of Functions 13.1. Description of registers 13.1.1. Control register 1 ( Reg 13.1.2. Control register 2 ( Reg 13.1.3. Clock counter ( Reg 13.1.4. Calendar counter ( Reg 13.1.5. Day counter ( Reg 13.1.6. Alarm registers ( Reg 13.1.7.
C bus interface real-time clock that has bult-in 32.768-kHz crystal oscillator. In addition to a calendar (year, month, day, weekday, hour, minute, second) function and a clock counter function, this module's real-time clock functions include an alarm function and a fixed-cycle timer interrupt function.
The CLKOUT pin is a clock output pin (C-MOS output) with the output control function. The CLKOE pin can be used in combination with the FE bit, FD1 bit, and FD0 bit to control the output mode of the CLKOUT output pin.
8564 LC 4. External Dimensions / Marking Layout 4.1. External Dimensions 8564 LC ( VSOJ 12pin ) External dimensions # 12 0.08 M 0.22 4.2. Marking Layout 8564 LC ( VSOJ 12pin ) Logo #1 Pin Mark Contents displayed indicate the general markings and display, but are not the standards for the fonts, sizes and positioning. 0.08 E 8564 A123B...
Aging This difference is 1 minute by 1 month. ( excluding offset ) Includes variation in frequency during two rounds of reflow processing. Reflow processing is performed under conditions specified by Seiko Epson Corporation. (See the relevant specifications.) Condition Between V...
8564 LC 8. Electrical Characteristics 8.1. DC characteristics Item Symbol Current consumption interface active Current consumption interface inactive = 0 Hz ) CLKOUT = disabled ( CLKOE = GND ) Current consumption interface inactive = 0 Hz ) CLKOUT = 32 kHz output ( LOAD is 0 pF ) "L"...
8564 LC 8.2. AC electrical characteristics Item SCL clock frequency Start condition set-up time Start condition hold time Data set-up time Data hold time Stop condition set-up time Bus free time between a STOP and START condition SCL "L" time SCL "H"...
1. Frequency and temperature characteristics can be approximated using the following equations. [ 1 / C [ C ] [ C ] 2. To determine overall clock accuracy, add the frequency precision and voltage characteristics. f/f = f/fo + f ! f/f ! f/fo 3.
8564 LC 10. External connection example 8564 SLAVE ADRS = 1010001 Pull up Registor device I C-BUS Page I C-BUS Master ETM12E-01...
8564 LC 11. Application notes 1) Notes on handling This module uses a C-MOS IC to realize low power consumption. (1) Static electricity While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be damaged by a large discharge of static electricity.
For details, see "13.3. Alarm Interrupt Function". 4) 32.768 kHz output function The 32.768 kHz clock signal (with precision equal to that of the on-chip crystal osillator) can be output (as C-MOS output) via the CLKOUT pin. If a different frequency is required, 32.768 kHz, For details, see "13.1.9.
If the CLKOE input pin is at high level ("H"), output from the CLKOUT output pin is at 32.768 kHz. The two TEST bits for address 00 (Control 1) are for use by Seiko Epson Corporation. When initializing, be sure to write "0". Afterward, be sure to write "0" whenever writing to these bits.
Function Control 1 This register is used to control stopping and starting of the clock function, calendar function, and other functions. 1) TEST bits (bit 7 and bit 3) These two TEST bits are for use by Seiko Epson Corporation.
8564 LC 13.1.2. Control register 2 ( Reg 01 [h] ) Address [h] Function Control 2 This register is used to monitor various interrupt event settings and the conditions under which various interrupt- related events occur. 1) TI / TP bit ( Interrupt Signal Output Mode Select. Interrupt / Periodic ) When a fixed-cycle timer interrupt event occurs (when the TF bit goes from "0"...
The data format is BCD format seconds. When overwriting time data, we recommend setting "1" to the STOP bit to stop the clock before overwriting. (This prevents unintentional carry operations from occurring while overwriting data.) Note with caution that writing non-existent time data may interfere with normal operation of the clock counter.
8564 LC 13.1.4. Calendar counter ( Reg 05 [h] , 07 [h] , 08 [h] ) Function Address [h] Days Months / Century Years The auto calendar function updates all dates, months, and years from January 1, 2001 to December 31, 2099. The data format is BCD format.
For details, see "9.2. Fixed-cycle Timer Interrupt Function ". 2) TD1,TD0 bits ( Timer countDown interval select 1, 0 ) These bits specify the fixed-cycle timer interrupt function's countdown period (source clock). Four different periods can be selected via combinations of these two bit values.
This register is used to control clock output via the CLKOUT output pin. This register is valid only when the CLKOE input pin is at high level, at which time clock output is enabled or disabled (stopped) depending on the settings in this register.
8564 LC 13.2. Fixed-cycle Timer Interrupt Function The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between 244.14 s and 255 minutes. There are two operation modes: "level interrupt mode" whereby the operation ends after one time, and "repeated interrupt mode"...
(Note) Note with caution that the preset value must be set or reset to enable correct operation. (2) When the TE bit = "1", the timer's down counter (Timer Register/Reg cycle (countdown cycle) of the source clock that was selected via the TD1 and TD0 bits (Timer countdown interval select bits 1 and 0).
2) The countdown when a 1-Hz source clock has been selected is linked to updating of the internal clock's seconds setting. Since the internal clock is linked to updating of the seconds setting, if the timer is started at a clock time of 0.9 seconds, the first countdown will occur only 0.1 second later. (The second and subsequent countdowns will occur at the correct time interval.)
When the fixed-cycle timer interrupt function is operating, the down counter counts down one step per source clock cycle, and when the count value goes from 01h to 00h, an event such as changing the TF bit value to "1" occurs.
Write / Read 13.2.3. Fixed-cycle timer interrupt interval (example) The combination of the source clock settings (settings in TD1 and TD0) and fixed-cycle timer countdown setting (Reg C setting) sets the fixed-cycle timer interrupt interval, as shown in the following examples.
(2) A fixed-cycle timer interrupt event occurs when the down counter value goes from 01h to 00h during a countdown in which the down counter's count value is decremented at each source clock cycle. (3) When a fixed-cycle timer interrupt event occurs, the TF bit value is changed to "1".
(1) When the TE bit value is changed from "0" to 1", the fixed-cycle timer's countdown begins. (2) A fixed-cycle timer interrupt event starts a countdown based on the countdown period (source clock). When the count value changes from 01h to 00h, an interrupt event occurs.
8564 LC 13.3. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred.
8564 LC 13.3.2. Alarm interrupt function registers Address [h] Function Control 2 Minutes Hours Days Weekdays Minute Alarm Hour Alarm Day Alarm Weekday Alarm Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts from occurring inadvertently while entering settings.
Four parameters can be set as alarm objects: minute, hour, day, and date. Hour settings are based on a 24-hour clock. To exclude a setting from possibly triggering an alarm interrupt, write "1" to the AE bit in the register corresponding to the setting in question.
8564 LC 13.4. /INT "L" Interrupt Output When Interrupt Function Operates 1) Setting interrupt events to occur in response to /INT "L" interrupt output The /INT interrupt output pin is shared as the output pin for two kinds of interrupt events: events related to the fixed-cycle timer interrupt function and events related to the alarm interrupt function.
The address auto increment function can be used to set continuous writing from Reg - 00[h] to 0F[h] during initialization. In such cases, be sure to write "1" to the STOP bit (to stop the clock) before starting the continuous write operation, and write "0" to the STOP bit (to start the clock) once initialization is completed.
When initializing be sure to initialize all of the data. Zero-clear the STOP bit to start (restart) the clock's operation. The clock starts from the set [second] + 500 ms (500 ms after the set second). (The first [second] update occurs 500 ms later.) The required information (among the [Year/Month/Day [day of week]:hour:minute:second] data) is read within one second.
2) Do not output interrupt when at low level Write "0" to the TIE bit. Set the timer's countdown period (= source clock). Select using a combination of TD1 and TD0 bit values. Set down counter's initial value. (Reg 0F[h]) (Note) Be sure to set or reset the down counter's initial value each time.
13.6.1. Overview of I2C-BUS The I C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data transfer signals, acknowledge signals, and so on.
8564 LC 13.6.3. Starting and stopping I2C bus communications START condition [ S ] 1) START condition, repeated START condition, and STOP condition (1) START condition The SDA level changes from high to low while SCL is at high level. (2) STOP condition This condition regulates how communications on the I 2 C-BUS are terminated.
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter.
8564 LC 13.6.6. I C bus protocol In the following sequence descriptions, it is assumed that the CPU is the master and the [ 8564 ] is the slave. 1) Address specification write sequence Since the [ 8564 ] includes an address auto increment function, once the initial address has been specified, the [ 8564 ] increments (by one byte) the receive address each time data is transferred.
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