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RX − 8801 SA / JE
8.2. Description of Registers
8.2.1. Register table
Address
Function
0
SEC
1
MIN
2
HOUR
3
WEEK
4
DAY
5
MONTH
6
YEAR
7
RAM
8
MIN Alarm
9
HOUR Alarm
WEEK Alarm
A
DAY Alarm
B
Timer Counter 0
C
Timer Counter 1
D
Extension Register
E
Flag Register
F
Control Register
Note
When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before
using the module.
Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or
time data is incorrect.
∗1)
During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".
∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.
∗2)
Only a "0" can be written to the UF, TF, AF, or VLF bit.
∗3)
Any bit marked with " " should be used with a value of "0" after initialization.
∗4)
Any bit marked with "•" is a RAM bit that can be used to read or write any data.
∗5)
The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
40
20
10
40
20
10
20
10
6
5
4
20
10
10
80
40
20
10
•
•
•
AE
40
20
10
•
AE
20
10
6
5
4
AE
•
20
10
128
64
32
16
•
•
•
TEST WADA USEL
TE
UF
TF
CSEL1 CSEL0
UIE
TIE
Page - 7
8
4
2
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
8
4
2
•
•
•
•
8
4
2
8
4
2
3
2
1
8
4
2
8
4
2
•
2048
1024
512
FSEL1 FSEL0 TSEL1 TSEL0
AF
VLF
AIE
Remark
∗3
1
∗3
1
∗3
1
∗3
0
∗3
1
∗3
1
−
1
•
∗4
−
1
∗4
1
0
∗4
1
−
1
∗4
256
∗1, ∗3, ∗5
∗1, ∗2, ∗3
VDET
∗3
RESET
ETM26E-03
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