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RA8804 CE
2
8.10.6. I
C bus protocol
In the following sequence descriptions, it is assumed that the CPU is the master and the RA8804 is the slave.
a. Address specification write sequence
Since the RA8804 includes an address auto increment function, once the initial address has been specified, the
RA8804 increments (by one byte) the receive address each time data is transferred.
(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RA8804.
(4) CPU transmits write address to RA8804.
(5) Check for ACK signal from RA8804.
(6) CPU transfers write data to the address specified at (4) above.
(7) Check for ACK signal from RA8804.
(8) Repeat (6) and (7) if necessary. Addresses are automatically incremented.
(9) CPU transfers stop condition [P].
(1)
S
Slave address
b. Address specification read sequence
After using write mode to write the address to be read, set read mode to read the actual data.
(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to write mode.
(3) Check for ACK signal from RA8804.
(4) CPU transfers address for reading from RA8804.
(5) Check for ACK signal from RA8804.
(6) CPU transfers RESTART condition [Sr] (in which case, CPU does not transfer a STOP condition
[P]).
(7) CPU transfers RA8804's slave address with the R/W bit set to read mode.
(8) Check for ACK signal from RA8804 (from this point on, the CPU is the receiver and the RA8804
is the transmitter).
(9) Data from address specified at (4) above is output by the RA8804.
(10) CPU transfers ACK signal to RA8804.
(11) Repeat (9) and (10) if necessary. Read addresses are automatically incremented.
(12) CPU transfers ACK signal for "1".
(13) CPU transfers stop condition [P].
(1)
(2)
S
Slave address
0
R/W
c. Read sequence when address is not specified
Once read mode has been initially set, data can be read immediately. In such cases, the address for each read
operation is the previously accessed address + 1.
(1) CPU transfers start condition [S].
(2) CPU transmits the RA8804's slave address with the R/W bit set to read mode.
(3) Check for ACK signal from RA8804 (from this point on, the CPU is the receiver and the RA8804 is
the transmitter).
(4) Data is output from the RA8804 to the address following the end of the previously accessed
address.
(5) CPU transfers ACK signal to RA8804.
(6) Repeat (4) and (5) if necessary. Read addresses are automatically incremented in the RA8804.
(7) CPU transfers ACK signal for "1".
(8) CPU transfers stop condition [P].
d. The address auto increment in Read/Write.
(1) In Basic time and calendar resister.
Address - - - - - - - 08 - 09 - 0A - 0B - 0C - 0D - 0E - 0F - 00 - 01 - 02 - -
(2) In Extension resister
Address - - - - - - - 18 - 19 - 1A - 1B - 1C - 1D - 1E - 1F - 10 - 11 - 12 - -
(2)
(3)
(4)
0
0
Address
R/W
(3)
(4)
(5)
(6)
0
Address
0
Sr
Slave address
ACK from RA8900
(1)
(2)
(3)
S
Slave address
1
0
R/W
ACK from RX8900
(5)
(6)
(7)
0
Data
0
ACK signal from RX8900
(7)
(8)
(9)
1
0
Data
R/W
(4)
(5)
(6)
Data
0
Data
ACK from CPU
Page - 34
(8)
(9)
Data
0
P
(10)
(11)
(12)
(13)
0
Data
1
P
ACK from CPU
(7)
(8)
1
P
ETM60E-02
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