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RX − 8801 SA / JE
7.2. AC Characteristics
Item
SCL clock frequency
Start condition setup time
Start condition hold time
Data setup time
Data hold time
Stop condition setup time
Bus idle time between
start condition and stop condition
=
Time when SCL
"L"
=
Time when SCL
"H"
Rise time for SCL and SDA
Fall time for SCL and SDA
Allowable spike time on bus
FOUT duty
Timing chart
START
Protocol
CONDITION
(S)
t
SU ; STA
SCL
(S)
SDA
t
HD ; STA
Caution:
When accessing this device, all communication from transmitting the start condition to transmitting the stop
condition after access should be completed within 0.95 seconds.
If such communication requires 0.95 seconds or longer, the I
timeout function.
Symbol
f
SCL
t
SU;STA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
SU;STO
t
BUF
t
LOW
t
HIGH
t
r
t
f
t
SP
t
/t
50% of V
W
BIT 7
BIT 6
MSB
(A7)
(A6)
t
t
1 / f
LOW
HIGH
SCL
t
t
r
f
t
t
SU ; DAT
HD ; DAT
GND = 0 V , V
DD
Condition
Min.
0.6
0.6
100
0
0.6
1.3
1.3
0.6
level
40
DD
BIT 0
ACK
LSB
(R/W)
(A)
(A)
t
SP
2
C bus interface is reset by the internal bus
Page - 5
* Unless otherwise specified,
= 1.8 V to 5.5 V , Ta = −40 °C to +85 °C
Typ.
Max.
400
900
0.3
0.3
50
50
60
STOP
START
CONDITION
CONDITION
(P)
(S)
t
SU ; STA
(P)
t
BUF
t
SU ; STO
ETM26E-03
Unit
kHz
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
ns
%
(S)
t
HD ; STA
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