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Reading/Writing Data Via The I 2 C Bus Interface; Overview Of I 2 C-Bus; System Configuration - Epson RX-8801SA/JE Applications Manual

Real time clock module
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RX − 8801 SA / JE
8.6. Reading/Writing Data via the I
2
8.6.1. Overview of I
C-BUS
2
The I
C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A
combination of these two signals is used to transmit and receive communication start/stop signals, data transfer
signals, acknowledge signals, and so on.
Both the SCL and SDA signals are held at high level whenever communications are not being performed.
The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at
high level.
During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and
on the receiving side the data is output while the SCL line is at high level.
2
The I
C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a
chip select pin, slave addresses are allocated to each device and the receiving device responds to communications
only when its slave address matches the slave address in the received data. In either case, the data is transferred
via the SCL line at a rate of one bit per clock pulse.

8.6.2. System configuration

All ports connected to the I
connections to multiple devices.
SCL and SDA are both connected to the V
at high level when the bus is released (when communication is not being performed).
Any device that controls the data transmission and data reception is defined as a "Master".
and any device that is controlled by a master device is defined as a "Slave".
The device transmitting data is defined as a "Transmitter" and the device receiving data is defined as a receiver"
In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a
transmitter or receiver depending on these conditions.
2
C Bus Interface
2
C bus must be either open drain or open collector ports in order to enable AND
line via a pull-up resistance. Consequently, SCL and SDA are both held
DD
V
DD
SDA
SCL
Master
Transmitter/
Receiver
CPU, etc.
Slave
Master
Transmitter/
Transmitter/
Receiver
Receiver
RX - 8801
Page - 22
Slave
Transmitter/
Receiver
2
Other I
C bus device
ETM26E-03

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