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This document is provided as a quick start guide for using the Texas Instruments BoC
(Break out Card). The breakout card is intended to provide communication support between
Texas Instruments EVM's which contain an AMC B+ interface. The EVM BoC is intended
to support EVM to EVM communication for SRIO, PCIe, SGMII, and AIF.
Abstract ........................................................................................................................................................................... 1
Table of Contents ........................................................................................................................................................... 1
Table of Figures .............................................................................................................................................................. 2
Table of Tables ............................................................................................................................................................... 2
I.
OVERVIEW ........................................................................................................................................................... 3
I.
Introduction ...................................................................................................................................................... 3
II.
Hardware Description...................................................................................................................................... 3
II. Hardware Configuration ....................................................................................................................................... 6
I.
Initial Installation Procedure ........................................................................................................................... 6
II.
Default Jumper and Pin Settings ...................................................................................................................... 6
III.
BoC Logic Power Source Selection [20].......................................................................................................... 6
IV.
EVM Power Source [16, 17, 18] ...................................................................................................................... 7
V.
Emulation Interface [1] .................................................................................................................................... 8
VI.
SGMII Interface ............................................................................................................................................... 8
VII.
PCIE Interface ................................................................................................................................................. 8
VIII.
SRIO (Serial RapidIO) Interface ...................................................................................................................... 9
IX.
AIF (Antenna Interface) Interface .................................................................................................................... 9
X.
I2C interface [5, 9, 11, 23] ............................................................................................................................... 9
XI.
Common REFCLK Source ............................................................................................................................. 10
REFCLK Oscillator Enable Header [19]....................................................................................................... 10
REFCLK Signal Levels................................................................................................................................... 10
XII.
Timer0 Output Headers [12, 22] .................................................................................................................... 12
XIII.
Timer0 Input Header [10, 24] ........................................................................................................................ 12
XIV.
Common RP1CLK Source .............................................................................................................................. 12
RP1CLK Oscillator Enable Header [8] ......................................................................................................... 12
RP1CLK Signal Levels ................................................................................................................................... 13
Alternate RP1CLK Inputs [15]....................................................................................................................... 14
XV.
Common TCLK_B Source .............................................................................................................................. 14
a.
TCLK_B Oscillator Enable Header [14] ....................................................................................................... 14
TCLK_B Signal Outputs [2, 13] ..................................................................................................................... 15
TCLK_A Signal Outputs [2, 13] ..................................................................................................................... 16
XVI.
Common PCIeREFCLK Source [25] ............................................................................................................. 17
Revision 0.4 - preliminary
Texas Instruments Dual EVM BoC Card
Abstract
Table of Contents
Users Guide
August 2011
- Quick Start Guide
High Density Multiprocessor DSP's
Page 1 of 31
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Summary of Contents for Texas Instruments CI2EVM BoC
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Page 1: Table Of Contents
High Density Multiprocessor DSP’s Abstract This document is provided as a quick start guide for using the Texas Instruments BoC (Break out Card). The breakout card is intended to provide communication support between Texas Instruments EVM’s which contain an AMC B+ interface. The EVM BoC is intended to support EVM to EVM communication for SRIO, PCIe, SGMII, and AIF. - Page 2 A_VCC12 GND_1 GND_56 TDI 7 PWR_12V_1 TDO_2_TDI TDO Output from Brd A to TDO_2_TDI 4 TRST# Board A TRST TRST# 4,7 TMS 4,7 JTAG Int RSRVD6 A_TCK 7 GND_2 GND_55 Board A A_DSP_RP1CLKP RSRVD8 Rx20+ A_DSP_RP1CLKN PWR_12V_2 Rx20- SGMII [0] GND_3 GND_54 A_AMC0_SGMII0_TX_DP...
- Page 3 GND_1 GND_56 B_VCC12 TDO_2_TDI TDO Output fr TDO_2_TDI 3 PWR_12V_1 TDO 7 TRST# TRST TRST# 3,7 TMS 3,7 RSRVD6 B_TCK 7 Board B GND_2 GND_55 B_DSP_RP1CLKP RSRVD8 Rx20+ SGMII [0] B_DSP_RP1CLKN PWR_12V_2 Rx20- GND_3 GND_54 B_AMC0_SGMII0_TX_DP B_EXP_SCL B_AMC0_SGMII0_TX_DP Rx0+ Tx20+ B_AMC0_SGMII0_TX_DN B_EXP_SDA FROM EVM B...
- Page 4 BRD3V3 CLOCK INTERFACE FULL SILK SCR NOTE: PLACE OSCILLATOR WITH NO STUBS U1 Output is LVPECL -U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72 SMA_SMT SMA_SMT -By default leave Disabled Resistors R20:R23 -Oscillator only installed on limited board RP1CLK SMT SMA have been configured -RPICLKP/N nets to be matched length from "T"...
- Page 5 J10 [ON = 0] DEFAULT J11 [ON = 0] DEFAULT 1 - A0 1 - A0 2 - A1 2 - A1 BRD3V3 BRD3V3 3 - A2 3 - A2 Board B i2c Expansion B_AMC_EXP_SCL B_AMC_EXP_SDA 219-3MST 219-3MST HDR_1x2 EEPROM EEPROM BRD3V3 BRD3V3...
- Page 6 U12 Output is LVPECL Resistors R71:R75 & R77:R83 POWER SUP have been configured for CML output. -Resistors will need to be changed to accommodate A_VCC12 BJ_MH1 Banana-2142- J6 Default 1: a different swing. 0.100" Header BJ_MH1 & BJ_MH2 1 shunt neede -All resistors to go close to U12 BRD3V3 -Mounting hole to...
- Page 7 EVM Dual BoC PCIeREFCLK Crystal-to-HCSL Output Enable Header [25] ............... 17 PCIeREFCLK Logic ............................18 Alternate PCIeREFCLK Inputs [4] ........................ 18 XVII. RP1FB Source [7]............................18 XVIII. RADSYNC & PHYSYNC Triggering [6] ......................18 XIX. Warnings and Cautions ..........................20 Pin Assignment [Board A] ..........................
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Page 8: Overview
EVM Dual BoC OVERVIEW Introduction The CI2EVM_BoC dual evm interface card is a high performance inter-communication card designed to provide DSP to DSP communication during software testing and analysis. Hardware Description The following illustrates the major components and areas of the CI2EVM_BoC breakout card. Figure 1 - BoC Top View Emulation Interface –... -
Page 9: Figure 2: Front View, Assembled Boc
EVM Dual BoC A_TCLKB & B_TCKB Source Input Clock Oscillator Enable Control – JP2 Auxilluary RP1CLK Clock Input SMA Connectors – CON1/CON2 Common Ground Banana Jack – BJ-MH3 Board B Power Banana Jack – BJ-MH2 Board A Power Banana Jack – BJ-MH1 Board A &... -
Page 10: Figure 3 - Block Diagram
EVM Dual BoC The following is a high level block diagram denoting the connectivity and functionality of the dual EVM BoC card. AMC HEADER 12Vin à 3.3V Out BOARD B CDCLVP 12V DC 12V DC SGMII TX Lane 1:0 SGMII RX Lane 1:0 SGMII RX Lane 1:0 SGMII TX Lane 1:0 PCIe TX Lane 3:0... -
Page 11: Hardware Configuration
EVM Dual BoC Hardware Configuration Initial Installation Procedure The following instructions define the basic minimum installation requirements for your BoC (Break out Card). Default Jumper and Pin Settings The following table defines the factory default configuration settings your BoC has been shipped with. -
Page 12: Evm Power Source [16, 17, 18]
EVM Dual BoC The following figure illustrates the basic power supply logic implemented on your BoC. POWER SUPPLY A_VCC12 BJ_MH1 REG1117-3.3 (0.8A) Banana-2142- J6 Default 1:2 REG1117 0.100" Header 1 shunt needed BRD3V3 Fuse 0154001.0 BRD3V3 B_VCC12 CON3BR Fuse 0154001.0 BJ_MH3 Banana-2142- BJ_MH2... -
Page 13: Emulation Interface [1]
EVM Dual BoC Emulation Interface [1] Your BoC contains a traditional Texas Instruments 60-pin emulation header (item 1). It should be noted that emulation voltages across the AMCC backplane are intended for 3.3Vdc. Your BoC has been designed so that the emulation interface is also 3.3V, before using this interface it will be necessary to confirm that your EVM’s can accommodate a... -
Page 14: Srio (Serial Rapidio) Interface
These headers (JP4 & JP5) can be used to program the individual on board EEPROMs. Your EEPROMS are blank from Texas Instruments. JP5 is the interface and programming header for Board A, and JP4 is the interface and programming header for Board B. -
Page 15: Common Refclk Source
EVM Dual BoC Table 2: JP5 & JP4 (Board A & B) I2C Switch Configuration EEPROM Address Switch WARNING: The I2C Interface is intended to operate at 3.3V, Confirm that your EVM level shifts this into to correct DSP range before using this interface or connecting your EVM’s. -
Page 16: Figure 7: Refclk Logic
EVM Dual BoC coupled, however they are biased. The current biasing scheme implemented is designed to provide the appropriate swing for most TI DSP’s available today. The following two figures illustrate the configuration for the REFCLK generation and biasing components. If a change in the output swing is needed, remove and replace the appropriate components carefully. -
Page 17: Timer0 Output Headers [12, 22]
EVM Dual BoC XII. Timer0 Output Headers [12, 22] The BoC incorporates a separate single header connected (through the AMC B+ connector) to each EVM’s DSP’s Timer0 output pin [ DSP Timer0_output ]. Header JP8 [22] is connected to Board B and header JP9 [12] is Timer0_output connected to Board A. -
Page 18: Rp1Clk Signal Levels
EVM Dual BoC Table 4: JP1 RP1CLK Enable Header Disabled Enabled b. RP1CLK Signal Levels The output of the low jitter 1:2 clock buffer is LVPECL (low voltage PECL). As such this logic level may not be adequate for your DSP. Consult your DSP data manual and the data manual for the CDCLVP1102 before using this hardware. -
Page 19: Alternate Rp1Clk Inputs [15]
EVM Dual BoC RP1CLK SMT SMA --Leave room for wrench-- od for LVDS swing) -must be skew matched between SMA's BRD3V3 and U10 input -NO STUBS CDCLVP1102 Zero stub between CON1/CON2 SMA and U2/U1 OScillator input, Gnd1 Nets must be identical length A_DSP_RP1CLKN 3 OUTN1 A_DSP_RP1CLKP 3... -
Page 20: Tclk_B Signal Outputs [2, 13]
EVM Dual BoC 30.72MHz to both EVM’s for TCLK_B. By default the shunt is installed and the REFCLK source is disabled. Table 5: JP2 TCLK_B Enable Header Disabled Enabled b. TCLK_B Signal Outputs [2, 13] There are two headers provided on your BoC; J1 & J2. Board A makes use of the 1 x 4 header whereas Board A interfaces with J2. -
Page 21: Tclk_A Signal Outputs [2, 13]
EVM Dual BoC The following two figures illustrate the configuration for the REFCLK generation and biasing components. If a change in the output swing is needed, remove and replace the appropriate components carefully. U6 Output is LVPECL BRD3V3 JP2 Default Settings Resistors R42:R45 -Install shunt R35 MUST be... -
Page 22: Common Pcierefclk Source [25]
EVM Dual BoC TCLKA_P TCLKA_P TCLKA_N TCLKA_N TCLKB_N TCLKB_P TCLKB_P TCLKB_N Figure 14: TCLK_B Interface CAUTION: Different versions of EVM’s have different pinout configurations, confirm that your EVM supports this interface and feature. Before using this interface to your BoC, confirm the logic levels and terminations are correct. -
Page 23: Pcierefclk Logic
EVM Dual BoC b. PCIeREFCLK Logic The following figure illustrates the support logic for the PCIeREFCLK gerneration circuit JP3 Default Settings BRD3V3 BRD3V3 -Install shunt between 1-2 NOTE: PLACE OSCILLATOR WITH NO STUBS -Output is Hi-Z -U5 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72 -By default leave Disabled -RPICLKP/N nets to be matched length from "T"... -
Page 24: Figure 16: Radsync & Physync Control
EVM Dual BoC Board B RADSYNC (Output) Board B PHYSYNC (Output) Board A PHYSYNC (Output) Board A RADSYNC (Output) Board A Timer0 (Input) Board B Timer0 (Input) Figure 16: RADSYNC & PHYSYNC Control The following figure illustrates the logic implemented to support this cross triggering. Placement of JP6/JP8 should be identical to JP7/JP9. -
Page 25: Warnings And Cautions
EVM Dual BoC The following table is provided for assistance in selecting the trigger souce and destination. Table 7: RADSYNC / PHYSYNC Trigger Configuration SWITCH POSITION 1-12 2-11 3-10 TimerOut0 Board B to Board A RADSYNC open open open closed closed open TimerOut0 Board B to Board A RADSYNC &... - Page 26 EVM Dual BoC Header / Pin Signal Header / Pin Signal Number Number Board A \ 18 12V Power Board A \ 153 RADSYNC Board A \ 19 Board A \ 152 Board A \ 20 SGMII1_TXp Board A \ 151 AIF5_TXp Board A \ 21 SGMII1_TXn...
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Page 27: Pin Assignment [Board B]
EVM Dual BoC Header / Pin Signal Header / Pin Signal Number Number Board A \ 71 Board A \ 100 SRIO3_RXp Board A \ 72 12V Power Board A \ 99 SRIO3_RXn Board A \ 73 Board A \ 98 Board A \ 74 A_TCLK_Ap Board A \ 97... - Page 28 EVM Dual BoC Header / Pin Signal Header / Pin Signal Number Number Board B \ 29 Board B \ 142 AIF4_RXp Board B \ 30 Board B \ 141 AIF4_RXn Board B \ 31 Board B \ 140 Board B \ 32 Board B \ 139 REFCLKp Board B \ 33...
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Page 29: Header Intra-Connections
EVM Dual BoC Header / Pin Signal Header / Pin Signal Number Number Board B \ 82 Board B \ 89 Board B \ 83 Board B \ 88 SRIO1_RXp Board B \ 84 12V Power Board B \ 87 SRIO1_RXn Board B \ 85 Board B \ 86... - Page 30 EVM Dual BoC Board Signal Board Signal Board A \ 151 AIF5_TXp Board B \ 148 AIF5_RXp Board A \ 150 AIF5_TXn Board B \ 147 AIF5_RXn Board A \ 148 AIF5_RXp Board B \ 151 AIF5_TXp Board A \ 147 AIF5_RXn Board B \ 150 AIF5_TXn...
- Page 31 EVM Dual BoC Board Signal Board Signal Board A \ 96 SRIO2_TXn Board B \ 93 SRIO2_RXn Board A \ 94 SRIO2_RXp Board B \ 97 SRIO2_TXp Board A \ 93 SRIO2_RXn Board B \ 96 SRIO2_TXn Board A \ 91 SRIO1_TXp Board B \ 88 SRIO1_RXp...
- Page 32 A_VCC12 GND_1 GND_56 TDI 7 PWR_12V_1 TDO_2_TDI TDO Output from Brd A to TDO_2_TDI 4 TRST# Board A TRST TRST# 4,7 TMS 4,7 JTAG Int RSRVD6 A_TCK 7 GND_2 GND_55 Board A A_DSP_RP1CLKP RSRVD8 Rx20+ A_DSP_RP1CLKN PWR_12V_2 Rx20- SGMII [0] GND_3 GND_54 A_AMC0_SGMII0_TX_DP...
- Page 33 GND_1 GND_56 B_VCC12 TDO_2_TDI TDO Output fr TDO_2_TDI 3 PWR_12V_1 TDO 7 TRST# TRST TRST# 3,7 TMS 3,7 RSRVD6 B_TCK 7 Board B GND_2 GND_55 B_DSP_RP1CLKP RSRVD8 Rx20+ SGMII [0] B_DSP_RP1CLKN PWR_12V_2 Rx20- GND_3 GND_54 B_AMC0_SGMII0_TX_DP B_EXP_SCL B_AMC0_SGMII0_TX_DP Rx0+ Tx20+ B_AMC0_SGMII0_TX_DN B_EXP_SDA FROM EVM B...
- Page 34 BRD3V3 CLOCK INTERFACE FULL SILK SCR NOTE: PLACE OSCILLATOR WITH NO STUBS U1 Output is LVPECL -U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72 SMA_SMT SMA_SMT -By default leave Disabled Resistors R20:R23 -Oscillator only installed on limited board RP1CLK SMT SMA have been configured -RPICLKP/N nets to be matched length from "T"...
- Page 35 J10 [ON = 0] DEFAULT J11 [ON = 0] DEFAULT 1 - A0 1 - A0 2 - A1 2 - A1 BRD3V3 BRD3V3 3 - A2 3 - A2 Board B i2c Expansion B_AMC_EXP_SCL B_AMC_EXP_SDA 219-3MST 219-3MST HDR_1x2 EEPROM EEPROM BRD3V3 BRD3V3...
- Page 36 U12 Output is LVPECL Resistors R71:R75 & R77:R83 POWER SUP have been configured for CML output. -Resistors will need to be changed to accommodate A_VCC12 BJ_MH1 Banana-2142- J6 Default 1: a different swing. 0.100" Header BJ_MH1 & BJ_MH2 1 shunt neede -All resistors to go close to U12 BRD3V3 -Mounting hole to...
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