Renesas mPD720231 User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Computer Hardware
  5. mPD720231
  6. User manual
Renesas mPD720231 User Manual

Renesas mPD720231 User Manual

Usb3.0 to sata3 bridge controller
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
μ
PD720231
USB3.0 to SATA3 BRIDGE CONTROLLER
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.1.00 Mar 2013

Advertisement

Table of Contents
loading

Related Manuals for Renesas mPD720231

Summary of Contents for Renesas mPD720231

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction.
  • Page 4 USB logo is a trademark of USB Implementers Forum, Inc.
  • Page 5 PREFACE Readers This manual is intended for engineers who need to be familiar with the capability μ of the PD720231 in order to develop application systems based on it. Purpose The purpose of this manual is to help users understand the hardware capabilities μ...

  • Page 6: Table Of Contents

    2.4 System Clock and Reset......................6 2.5 USB Interface ...........................6 2.6 Serial ATA Interface ........................6 2.7 General Purpose I/O Interface....................7 2.8 Renesas private signal ......................7 3. Endpoint Configuration ........................8 3.1 Super-speed UASP Mode .......................8 3.2 Super-speed BOT Mode......................9 3.3 High-speed UASP Mode ......................9 3.4 High-speed BOT Mode......................9...
  • Page 7 5.2 HDD/SSD boot mode ......................21 6. General Purpose I/O .........................22 6.1 Features..........................22 6.2 SPI interface...........................22 6.3 Disk Activity LED........................22 6.4 Reset signal for external device ..................23 6.5 Clockout function ........................23 6.6 External trigger in........................23 7. How to Connect to External Elements ...................24 7.1 Handling Unused Pins ......................24 7.2 Upstream Port Connection....................25 7.3 RREF Connection ........................26...
  • Page 8 LIST OF FIGURES Figure No. Title Page μ Figure 1-1. PD720231 Block Diagram......................... 2 Figure 1-2. Pin Configuration (Top View) ......................4 Figure 7-1. USB Upstream Port Connection ....................... 25 Figure 7-2. RREF Connection ..........................26 Figure 7-3. Crystal Connection..........................26 Figure 7-4.
  • Page 9 LIST OF TABLES Table No. Title Page Table 2-1. Power Supply ............................5 Table 2-2. Analog Signal ............................5 Table 2-3. VBUS and Regulator ..........................5 Table 2-4. System Clock and Reset ........................6 Table 2-5. USB Interface............................6 Table 2-6. Serial ATA Interface ..........................6 Table 2-7.

  • Page 10: Overview

    R19UH0094EJ0100 μ PD720231 Rev 1.00 ASSP (USB3.0 to SATA3 BRIDGE CONTROLLER) Mar 1, 2013 1. Overview μ PD720231 is a USB3.0 to SATA3 Bridge LSI which complies with Universal Serial Bus 3.0 (USB3.0) Specification Revision 1.0 and Serial ATA (SATA) Specification Revision 3.0. The LSI is integrated USB3.0 function controller and SATA III host controller with USB3.0 transceiver, USB2.0 transceiver and SATA III transceiver into one chip.

  • Page 11: Ordering Information

    μ PD720231 1. Overview Ordering Information Part Number Package Remark μ PD720231K8-611-BAE-A 48-pin QFN (6 x 6) Lead-free product Block Diagram μ Figure 1-1. PD720231 Block Diagram µ PD720231 SATA Work (1.5 G/3 G/6 Gbps) SATAIII SATA SATA Memory Host Gen3 LINK Controller...
  • Page 12 μ PD720231 1. Overview Integrated 32bit RISC CPU. CPU Peripherals Includes bus controller, interrupt controller, timer, GPIO and so on. Work RAM Integrated Work RAM for data. Integrated Boot ROM. SATA III Host The SATA III host supports SATA Gen1 1.5 Gbps, Gen2 3.0 Gbps, Controller and Gen3 6.0 Gbps.

  • Page 13: Pin Configuration

    μ PD720231 1. Overview Pin Configuration • 48-pin QFN (6 x 6) μ PD720231K8-611-BAE-A Figure 1-2. Pin Configuration (Top View) R19UH0094EJ0100 Rev 1.00 Page 4 of 30 Mar 1, 2013...

  • Page 14: Pin Function

    μ PD720231 2. Pin Function 2. Pin Function This section describes each pin’s function. Power supply and regulator Table 2-1. Power Supply Pin Name Pin No. Buffer Type Function VDD33 Power +3.3 V power supply +3.3 V power supply for GPIOs, except for VDDGPIO 5, 39 Power...

  • Page 15: System Clock And Reset

    μ PD720231 2. Pin Function System Clock and Reset Table 2-4. System Clock and Reset Pin Name Pin No. Direction Buffer Type Active Function Level − 30 MHz oscillator input. Connect to a 30 MHz crystal. − 30 MHz oscillator output. Connect to a 30 MHz crystal.

  • Page 16: General Purpose I/O Interface

    Note 1. Except for GPIO5 and GPIO6, all the other GPIOs are supplied power from VDDGPIO. GPIO5 and GPIO6 are supplied power from internal VDD33 line. mark 2. GPIO4 drives low in default. Other GPIO signals are open state in default. Renesas private signal Table 2-8. Test signal Pin Name Pin No.

  • Page 17: Endpoint Configuration

    μ PD720231 3. Endpoint Configuration 3. Endpoint Configuration μ PD720231 is capable of working in either USB Mass Storage Class Bulk Only Transport protocol (BOT) or UAS protocol (UASP) both in SS/HS mode. Configuration Interface, Alternate Setting for each speed mode is shown in table below. μ...

  • Page 18: Super-Speed Bot Mode

    μ PD720231 3. Endpoint Configuration 3.2 Super-speed BOT Mode Configuration for Super-speed BOT mode is show in Table 3-3. Table 3-3. Configuration for Super-speed BOT mode EP No. Direction Transfer Max Packet Max Burst Stream type Size Size − IN/OUT Control 512 bytes Bulk...

  • Page 19: Usb Descriptor Information

    09h or 40h Maximum packet size for this speed. 09h: 512 bytes for Super-speed. 40h: 64 bytes for High/Full-speed idVender 045Bh Vender ID of Renesas Electronics μ idProduct 021Fh/ PD720231’s product ID 0220h 021Fh: UASP support 0220h: Bulk Only support...

  • Page 20: Bos (Binary Device Object Store) Descriptor

    μ PD720231 4. USB Descriptor Information 4.2 BOS (Binary device Object Store) Descriptor The BOS descriptor defines a root descriptor that is similar to the configuration descriptor, and is the base descriptor for accessing a family of related descriptors. Offset Field Size Value...

  • Page 21: Configuration Descriptor (All Speeds)

    μ PD720231 4. USB Descriptor Information 4.3 Configuration Descriptor (All speeds) A configuration descriptor describes information about a specific device configuration. When the host requests the configuration descriptor, all related interface and endpoint descriptors are returned. Offset Field Size Value Description bLength Size of descriptor...

  • Page 22: Interface Descriptor For Uasp Mode (Super-/High-Speed Only)

    μ PD720231 4. USB Descriptor Information 4.4.2 Interface descriptor for UASP mode (Super-/High-speed only) Offset Field Size Value Description bLength Size of descriptor bDescriptorType Interface descriptor type bInterfaceNumber Number of supported interface bAlternateSetting Value used to select alternate setting for the interface identified in the prior field bNumEndpoints Number of endpoints used by this interface...

  • Page 23: Data-In

    μ PD720231 4. USB Descriptor Information SuperSpeed Endpoint Companion Descriptor (Super-speed only) Offset Field Size Value Description bLength Size of descriptor bDescriptorType SUPERSPEED_USB_ENDPOINT_COMPANION descriptor type. bMaxBurst Max. burst = 16 bmAttributes Stream not supported − wBytesPerInterval 0000h 4.5.1.2 Data-IN Endpoint Descriptor (All speeds) Offset Field Size...

  • Page 24: Uasp Mode (Super-/High-Speed Only)

    μ PD720231 4. USB Descriptor Information 4.5.2 UASP mode (Super-/High-speed only) 4.5.2.1 Data-OUT Endpoint Descriptor Offset Field Size Value Description bLength Size of descriptor bDescriptorType Endpoint descriptor type bEndpointAddress Address: 1, Direction: OUT bmAttributes Endpoint’s attributes (Bulk) wMaxPacketSize 0400h or Maximum packet size 0200h 0400h: 1024 bytes in Super-speed mode.

  • Page 25: Data-In

    μ PD720231 4. USB Descriptor Information 4.5.2.2 Data-IN Endpoint Descriptor Offset Field Size Value Description bLength Size of descriptor bDescriptorType Endpoint descriptor type bEndpointAddress Address: 2, Direction: IN bmAttributes Endpoint’s attributes (Bulk) wMaxPacketSize 0400h or Maximum packet size 0200h 0400h: 1024 bytes in Super-speed mode. 0200h: 512 bytes in High-speed mode.

  • Page 26: Uasp Command

    μ PD720231 4. USB Descriptor Information 4.5.2.3 UASP Command Endpoint Descriptor Offset Field Size Value Description bLength Size of descriptor bDescriptorType Endpoint descriptor type bEndpointAddress Address: 3, Direction: OUT bmAttributes Endpoint’s attributes (Bulk) wMaxPacketSize 0400h or Maximum packet size 0200h 0400h: 1024 bytes in Super-speed mode.

  • Page 27: Uasp Status

    μ PD720231 4. USB Descriptor Information 4.5.2.4 UASP Status Endpoint Descriptor Offset Field Size Value Description bLength Size of descriptor bDescriptorType Endpoint descriptor type bEndpointAddress Address 4, Direction: IN bmAttributes Endpoint’s attributes (Bulk) wMaxPacketSize 0400h or Maximum packet size 0200h 0400h: 1024 bytes in Super-speed mode.

  • Page 28: String Descriptor

    μ PD720231 4. USB Descriptor Information 4.6 String Descriptor String descriptors describe Language ID, Manufacturer, Product and/or Serial Number. This string information is defined with the serial ROM utility. Language ID (string descriptor index 0) Offset Field Size Value Description bLength Size of descriptor bDescriptorType...

  • Page 29: Device Qualifier Descriptor (High-/Full-Speed Only)

    μ PD720231 4. USB Descriptor Information 4.7 Device Qualifier Descriptor (High-/Full-speed only) A device qualifier descriptor describes general information about a high-speed capable device that would change if the device were operating at the other speed. For example, if the device is currently operating at full-speed, the device qualifier returns information about how it would operate at high-speed and vice-versa.

  • Page 30: Boot Mode

    μ PD720231 5. Boot Mode 5. Boot Mode μ There are 2 boot modes in the PD720231, SROM boot mode and HDD/SSD boot mode. HDD/SDD boot mode has Quick/Slow enumeration option. These are selected from GPIO setting during initialization. Table 5-1. Boot Mode selection GPIO0 GPIO1...

  • Page 31: General Purpose I/O

    μ PD720231 6. General Purpose I/O 6. General Purpose I/O 6.1 Features μ PD720231 supports 10 configurable GPIO pins with the following features. Each function is configured as shown in Table 6-1. SPI interface for external serial flash ROM. Disk Activity LED Reset/Clock output for external device External trigger input Table 6-1 Function configuration...

  • Page 32: Reset Signal For External Device

    μ PD720231 6. General Purpose I/O Reset signal for external device μ PD720231 provides reset signal for external device from GPIO4. GPIO4 drives low in default and it μ changes to Hi-Z after PD720231 read parameter from external SROM or SATA devices and confirms that this function is supported.

  • Page 33: How To Connect To External Elements

    μ PD720231 7. How to Connect to External Elements 7. How to Connect to External Elements 7.1 Handling Unused Pins Unused pins shall be connected as shown below. Table 7-1. Unused Pin Connection Direction Connection Method GPIO0/SPISO, Please refer to Table 5-1 GPIO1/SPISCK, GPIO2/SPISI, GPIO3/SPICSB...

  • Page 34: Upstream Port Connection

    μ PD720231 7. How to Connect to External Elements 7.2 Upstream Port Connection Figure 7-1. USB Upstream Port Connection µPD720231 USB3.0 signals SSRX+ U3RXP SSRX- U3RXN 0.1µF SSTX+ U3TXP SSTX- U3TXN 0.1µF USB2.0 signals VBUS Less than 10 µF VBUS U2DP U2DM μ...

  • Page 35: Rref Connection

    μ PD720231 7. How to Connect to External Elements 7.3 RREF Connection Figure 7-2. RREF Connection µPD720231 RREF 1.6 Kohm ± 1% Remark The board layout should minimize the total path length from RREF through the resistor to GND and path length to GND. GND must be stable. Due to analog sensitivity, 1.60 K within 1% must be used, and two or more resistors in series or ±...

  • Page 36: External Serial Rom Connection

    μ PD720231 7. How to Connect to External Elements 7.5 External Serial ROM Connection Figure 7-4. External Serial ROM Connection 3.3 V µPD720231 External Serial GPIO1/SPISCK GPIO3/SPICS0B HOLD# GPIO0/SPISO GPIO2/SPISI The supported serial ROMs are listed in Table 7-5. Table 7-5. Supported External Serial ROM (3.3V) list Manufacturer Product Name...

  • Page 37: Serial Ata Interface Connection

    μ PD720231 7. How to Connect to External Elements 7.6 Serial ATA Interface Connection Figure 7-6. Serial ATA Interface Connection SATA Connector µPD720231 0.01µF STXP STXN 0.01µF 0.01µF SRXN SRXP 0.01µF R19UH0094EJ0100 Rev 1.00 Page 28 of 30 Mar 1, 2013...

  • Page 38: On-Chip Ldo (5 V To 3.3 V) Connection

    μ PD720231 7. How to Connect to External Elements 7.7 On-Chip LDO (5 V to 3.3 V) Connection It is prohibited not to use internal LDO and V50IN must be always supplied. Figure 7-7. On-Chip LDO Pin Connection 3.3V μPD720231 V50IN VDD33OUT 4.7uF...

  • Page 39: On-Chip Switching Regulator (3.3 V To 1.0 V) Connection

    μ PD720231 7. How to Connect to External Elements 7.8 On-Chip Switching Regulator (3.3 V to 1.0 V) Connection Figure 7-8. On-Chip Switching Regulator Pin Connection µPD720231 VDD10 SW Regulator 1.0 V 4.7 µH Schottky 0.1 µF 22 µF Barrier Diode 3.3 V AVDD33IN1...
  • Page 40 μ REVISION HISTORY PD720231 User’s Manual: Hardware Rev. Date Description Page Summary − 1.00 Mar 1, 2013 First Edition issued C - 1...
  • Page 41 μ PD720231 User’s Manual: Hardware Publication Date: Rev. 1.00 Mar 1, 2013 Published by: Renesas Electronics Corporation...
  • Page 42 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
  • Page 43 μ PD720231 R19UH0094EJ0100...

Table of Contents