Table of Contents
Advertisement
μ
PD720231
CPU
CPU Peripherals
Work RAM
ROM
SATA III Host
Controller
SATA LINK
SATA Gen3 PHY
USB Endpoint
Controller (EPC)
USB LINK
USB3.0 PHY
USB2.0 PHY
CCU
OSC
3.3 V to 1.0 V
Regulator
5 V to 3.3 V Regulator
R19UH0094EJ0100 Rev 1.00
Mar 1, 2013
Integrated 32bit RISC CPU.
Includes bus controller, interrupt controller, timer, GPIO and so on.
Integrated Work RAM for data.
Integrated Boot ROM.
The SATA III host supports SATA Gen1 1.5 Gbps, Gen2 3.0 Gbps,
and Gen3 6.0 Gbps. Dedicated bus realizes SuperSpeed interface
between SATA III host and Direct Command Controller.
Link layer translates data packets between SATA host and SATA
PHY.
Integrated SATAIII Gen1 1.5Gbps, Gen2 3.0Gbps, and Gen3 6.0
Gbps compliance transceiver. This is controlled by SATAIII host.
Transport / Protocol layer. This block supports USB Mass Storage
class USB Attached SCSI Protocol and Bulk Only Transport.
Link layer defined in USB specification, which maintains Link
connectivity with USB host controller and hub.
For SuperSpeed Tx/Rx
For USB High/Full-speed Tx/Rx
Integrated clock controller to manage system power consumption, and
system reset controller.
Internal oscillator block.
Regulator to convert 3.3 V to 1.0 V
Regulator to convert 5 V to 3.3 V
1. Overview
Page 3 of 30
Advertisement
Table of Contents
