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USB Data Port 0 -
USB Data Port 0 +
Real Time Clock power line
Not Connected
Not Connected
LPC serial interrupt request
Power Ground
PCI-E lane 5 transmit +
PCI-E lane 5 transmit -
GP Input 0 / SDIO data signal 0
PCI-E lane 4 transmit +
PCI-E lane 4 transmit -
Power Ground
PCI-E lane 3 transmit +
PCI-E lane 3 transmit -
Power Ground
PCI-E lane 2 transmit +
PCI-E lane 2 transmit -
GP Input 1 / SDIO data signal 1
PCI-E lane 1 transmit +
PCI-E lane 1 transmit -
Power Ground
GP Input 2 / SDIO data signal 2
PCI-E lane 0 transmit +
PCI-E lane 0 transmit -
Power Ground
LVDS Ch. A Data 0 + / eDP Ch. Data 2+
LVDS Ch. A Data 0 - / eDP Ch. Data 2-
LVDS Ch. A Data 1+ / eDP Ch. Data 1+
LVDS Ch. A Data 1- / eDP Ch. Data 1-
CCOMe-C96
CCOMe-C96 - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by C.M. Copyright © 2021 SECO S.p.A.
USB0-
A45
USB0+
A46
VCC_RTC
A47
N.C.
A48
N.C.
A49
LPC_SERIRQ
A50
GND
A51
PCIE_TX5+
A52
PCIE_TX5-
A53
GPI0/SD_DATA0
A54
PCIE_TX4+
A55
PCIE_TX4-
A56
GND
A57
PCIE_TX3+
A58
PCIE_TX3-
A59
GND
A60
PCIE_TX2+
A61
PCIE_TX2-
A62
GPI1/SD_DATA1
A63
PCIE_TX1+
A64
PCIE_TX1-
A65
GND
A66
GPI2/SD_DATA2
A67
PCIE_TX0+
A68
PCIE_TX0-
A69
GND
A70
LVDS_A0+/eDP_TX2+
A71
LVDS_A0-/eDP_TX2-
A72
LVDS_A1+/eDP_TX1+
A73
LVDS_A1-/eDP_TX1-
A74
B45
USB1-
B46
USB1+
B47
EXCD1_PERST#
B48
N.C.
B49
SYS_RESET#
B50
CB_RESET#
B51
GND
B52
PCIE_RX5+
B53
PCIE_RX5-
B54
GPO1/SD_CMD
B55
PCIE_RX4+
B56
PCIE_RX4-
B57
GPO2/SD_WP
B58
PCIE_RX3+
B59
PCIE_RX3-
B60
GND
B61
PCIE_RX2+
B62
PCIE_RX2-
B63
GPO3/SD_CD#
B64
PCIE_RX1+
B65
PCIE_RX1-
B66
WAKE0#
B67
WAKE1#
B68
PCIE_RX0+
B69
PCIE_RX0-
B70
GND
B71
LVDS_B0+
B72
LVDS_B0-
B73
LVDS_B1+
B74
LVDS_B1-
USB Data Port 1-
USB Data Port 1+
eSPI enable Input
Not Connected
Reset Button Input
Board Reset Output
Power Ground
PCI-E lane 5 receive +
PCI-E lane 5 receive -
GP Output 1 / SDIO CMD output
PCI-E lane 4 receive +
PCI-E lane 4 receive -
GP Output 2 / SDIO WP input
PCI-E lane 3 receive +
PCI-E lane 3 receive -
Power Ground
PCI-E lane 2 receive +
PCI-E lane 2 receive -
GP Output 3 / SDIO CD# input
PCI-E lane 1 receive +
PCI-E lane 1 receive -
PCI-express wake up signal
General purpose wake up signal
PCI-E lane 0 receive +
PCI-E lane 0 receive -
Power Ground
LVDS Ch. B Data 0 +
LVDS Ch. B Data 0 -
LVDS Ch. B Data 1 +
LVDS Ch. B Data 1 -
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