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3.10 Header for Debug Signals
CCFL Signals (JP208)
•
CCFL_OFF
•
CCFL_IGNIT
•
CCFL_FET2
•
CCFL_FET1
2
I
C Signals from SAA7111A (JP211)
•
2
I
C_SCL
•
2
I
C_SDA
•
RES-out
SAA7111A Signals (JP304)
•
RTC0
•
VSC_IDENT
•
ALPHA
•
V
ref
•
H
ref
•
C
ref
•
HS
•
VS
•
GPSW
•
RES-out
VIC Signals (JP401)
•
BUS_VCS_D7-0 - Video scaler data input
•
VSC_CLKV
LVDS connector (JP402)
Signals for LVDS connector
Display Signals (JP501)
•
DIS_PIXCLK
•
A_RED
•
A_GREEN
•
A_BLUE
•
DIS_HSYNC
•
DIS_VSYNC
•
DIS_VREF
•
DIS_CK
Display Digital Signals (JP502, JP503, JP504)
•
BUS_DIS_D7-0
•
BUS_DIS_D15-8 - Digital display data
•
BUS_DIS_D23-16 - Digital display data
– CCFL supply control OFF
– CCFL supply control IGNITION
– CCFL FET driver2
– CCFL FET driver1
- Serial clock line
- Serial data line
- Reset output (active low)
- Real time control output
- Video scaler field identification
- Video scaler ALPHA
- Vertical reference output signal
- Horizontal reference output signal
- Clock reference output
- Horizontal sync output signal
- Vertical sync output signal
- General purpose switch output
- Reset output (active low)
- Video scaler clock
- Display pixel clock
- Analog red
- Analog green
- Analog blue
- Horizontal sync signal
- Vertical sync signal
- Display vertical reference signal
- Display clock
- Digital display data
9
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