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Schematic Diagrams
Ivy Bridge 2/7
PU/PD for JTAG signals
1.05VS_VTT
3.3VS
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
Sheet 3 of 55
Ivy Bridge 2/7
Buffered reset to CPU
25,31
B - 4 Ivy Bridge 2/7
All manuals and user guides at all-guides.com
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
*51_04
R39
XDP_PREQ#
RN5
56_8P4R_04
8
1
XDP_TMS
7
2
XDP_TDO_R
6
3
XDP_TDI_R
5
4
XDP_TCLK
XDP_TRST#
51_04
R263
H_SNB_IVB#
26
H_SNB_IVB#
SKTOCC#
XDP_DBR_R
R220
1K_04
H_CATERR#
R223
*10mil_short
22,26,37
H_PECI
H_PROCHOT#
R19
56_1%_04
H_PROCHOT#_D
43,45
H_PROCHOT#
26
H_THRMTRIP#
23
H_PM_SYNC
R24
*10mil_short
H_CPUPWRGD_R
26
H_CPUPWRGD
PMSYS_PWRGD_BUF
R84
130_1%_04
VDDPWRGOOD_R
BUF_CPU_RST#
1.05VS_VTT
3.3VS
R219
75_04
R217
R224
43.2_1%_04
BUF_CPU_RST#
10K_04
D
Q13B
5
G
MTDN7002ZHS6R
S
D
2
G
Q13A
PLT_RST#
S
MTDN7002ZHS6R
R221
*1.5K_1%_04
R218
C463
R222
100K_04
68p_50V_NPO_04
*750_1%_04
U15B
A28
CLK_EXP_P 22
BCLK
C26
A27
PROC_SELECT#
BCLK#
CLK_EXP_N 22
AN34
SKTOCC#
A16
CLK_DP_P 22
DPLL_REF_CLK
A15
CLK_DP_N 22
DPLL_REF_CLK#
AL33
CATERR#
AN33
R8
CPUDRAMRST#
PECI
SM_DRAMRST#
AL32
AK1
SM_RCOMP_0
PROCHOT#
SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4
SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY #
PRDY#
AP27
XDP_PREQ#
PREQ#
AR26
XDP_TCLK
TCK
AR27
XDP_TMS
TMS
AM34
AP30
XDP_TRST#
PM_SY NC
TRST#
AR28
XDP_TDI_R
TDI
AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35
XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
BPM#[0]
AR29
BPM#[1]
AR30
BPM#[2]
AR33
AT30
RESET#
BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
T2
6-86-27988-004 T2
PZ98821-362B-01H
6-86-27988-005 GF
479890730
H_PROCHOT#
Q12
G
C29
37
H_PROCHOT#_EC
MTN7002ZHS3
R216
47p_50V_NPO_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
2,6,12,19,21,22,23,25,26,27,28,30,31,32,36,38,40,41,42
9,10,11,12,21,22,23,24,25,26,27,28,30,31,33,34,35,36,37,38,43,45
Processor Pullups/Pull downs
H_PROCHOT#
R215
62_04
H_CPUPWRGD_R
R256
10K_04
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
SM_RCOMP_0
R388
140_1%_04
SM_RCOMP_1
R349
25.5_1%_04
SM_RCOMP_2
R351
200_1%_04
S3 circuit:- DRAM PWR GOOD logic
3.3V
3.3V
C651
R461
R456
1.5VS_CPU
R478
200_1%_04
1
23
PM_DRAM_PWRGD
4
PMSY S_PWRGD_BUF
2
23,40
1.8VS_PWRGD
U31
*MC74VHC1G08DFT1G
R474
*39_04
R470
*10mil_short
Q31
G
38,40,41,42
SUSB
*MTN7002ZHS3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R330
R332
*0_04
1K_04
Q21
MTN7002ZHS3
CPUDRAMRST#
S
D
R329
1K_04
DDR3_DRAMRST# 9,10,11
DRAMRST_CNTRL 6,22
R337
C579
4.99K_1%_04
0.047u_10V_X7R_04
6,38,41
1.5VS_CPU
6,9,10,11,28,38,41
1.5V
2,5,23,26,27,28,38
1.05VS_VTT
3.3V
3.3VS
1.05VS_VTT
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